Patents Issued in July 3, 2008
  • Publication number: 20080157328
    Abstract: In the multiple-layered semiconductor device and the method for manufacturing thereof according to the present invention, the resin is formed on the substrate around the semiconductor device, on which the semiconductor device is installed in the first semiconductor package. Therefore, a generation of a warpage of substrate is inhibited in the first semiconductor package. And since the first semiconductor package is stacked to and coupled to the second semiconductor package via the electric conductors that extend from the back surface of the second semiconductor package to the coupling lands on the substrate penetrating through the resin, a defective situation such as a coupling defective in the bump junction can be avoided when the junction of the second semiconductor package via the electric conductor is formed. Therefore, a considerably improved coupling reliability in the multiple-layered semiconductor device can be achieved.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 3, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Tsutomu KAWATA
  • Publication number: 20080157329
    Abstract: In an electronic component contained substrate in which electronic components are mounted between a pair of wiring substrates in a plural-stage stacked fashion, one wiring substrate and other wiring substrate are connected electrically mutually via solder balls, a first electronic component is mounted on one wiring substrate and then a second electronic component is mounted on the first electronic component, an opening portion for containing the second electronic component therein is provided in the other wiring substrate, the second electronic component is contained and mounted in the opening portion and is connected electrically to the other wiring substrate by a wire bonding, and a space between the pair of wiring substrates is sealed with a sealing resin.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 3, 2008
    Inventor: Akinobu INOUE
  • Publication number: 20080157330
    Abstract: A semiconductor device is disclosed. At least one semiconductor chip is mounted on a substrate and is contacted to contact elements of the substrate. The encapsulation of the semiconductor chip includes the substrate, a cover and a pocket within the connected substrate and cover. The pocket is able to fix the chip in its position, and the cover is composed of the same material as the substrate.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 3, 2008
    Inventors: Steffen Kroehnert, Kerstin Nocke, Juergen Grafe, Kashi Vishwanath Machani
  • Publication number: 20080157331
    Abstract: The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved.
    Type: Application
    Filed: November 20, 2007
    Publication date: July 3, 2008
    Inventor: Masanori Onodera
  • Publication number: 20080157332
    Abstract: A stacked semiconductor package may include: a substrate; semiconductor packages stacked on the substrate; an interconnection member formed on edges of the semiconductor packages; and a conductive reinforcement member formed on the interconnection member. Each of the semiconductor packages may include a conductive line. The interconnection member may electrically connect the conductive line of the semiconductor packages to the conductive line of at least one other semiconductor package.
    Type: Application
    Filed: December 12, 2007
    Publication date: July 3, 2008
    Inventors: Cha-Jea Jo, Seok-Ho Kim, Ju-Il Choi, Chang-Woo Shin
  • Publication number: 20080157333
    Abstract: A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.
    Type: Application
    Filed: May 10, 2007
    Publication date: July 3, 2008
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Chun-Ying Lin, Ya-Chi Chen, Yu-Ren Chen, I-Hsin Mao
  • Publication number: 20080157334
    Abstract: A memory module for improving impact resistance mainly comprises a multi-layer PWB (Printed Wiring Board) and a plurality of memory packages. The multi-layer PWB is rectangular and has two longer sides and two shorter sides, wherein a plurality of gold fingers are disposed along one of the longer sides, at least an arc notch and a plurality of first stress-absorbing slots are formed at the two shorter sides respectively. Preferably, plural second stress-absorbing slots are formed at another longer side far away from the gold fingers. The impact stress due to accidental drop may be absorbed by the first stress-absorbing slots or/and the second stress-absorbing slots to prevent the product from damaging.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventor: Wen-Jeng Fan
  • Publication number: 20080157335
    Abstract: A semiconductor package has a substrate. The substrate comprises a set of interconnects. An dielectric material may be provided under one or more of the interconnects to adjust the impedance of transmission line.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Jia Miao Tang, Xiang Yin Zeng, Dao Qiang Lu, Jiang Qi He
  • Publication number: 20080157336
    Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die disposed within the die receiving through hole; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 3, 2008
    Inventor: Wen-Kun Yang
  • Publication number: 20080157337
    Abstract: A semiconductor packaging substrate with improved capability of electrostatic dissipation comprises a dielectric layer, a plurality of leads, a plurality of first electrostatic guiding traces, a plurality of second electrostatic guiding traces and a solder mask. The first electrostatic guiding traces and the second electrostatic guiding traces are formed in pairs in a plurality of electrostatic dissipation regions on the dielectric layer, where each pair of the first and second electrostatic guiding traces are disposed in equal line spacing and are electrically isolated from each other. The solder mask partially covers the leads but exposes the first electrostatic guiding traces and the second electrostatic guiding traces. The first electrostatic guiding traces are connected to some of the leads to enhance protection against electrostatic discharge.
    Type: Application
    Filed: May 4, 2007
    Publication date: July 3, 2008
    Inventors: Tsung-Lung Chen, Ming-Hsun Li
  • Publication number: 20080157338
    Abstract: A manufacturing technology is provided capable of improving the reliability of a semiconductor module having a via contact connected to an electrode part of a semiconductor device. A conductive bump is formed on an insulating layer such that the end of the conductive bump is in contact with an electrode of a semiconductor substrate. By pressure-molding the assembly using a press machine, the semiconductor substrate, the conductive bump, and the insulating layer are integrated. With this, the conductive bump is allowed to embed itself in the insulating layer while maintaining contact with the electrode. The insulating layer is subject to laser irradiation from above so as to form an aperture exposing the conductive bump. Subsequently, the upper surface of the insulating layer and the interior surface of the aperture are plated with copper by electroless plating and electroplating so as to form a copper plating layer, and a via contact is formed in the aperture so as to coat the inner wall of the aperture.
    Type: Application
    Filed: December 14, 2007
    Publication date: July 3, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Mayumi Nakasato, Kiyoshi Shibata, Yoshio Okayama, Ryosuke Usui, Hideki Mizuhara
  • Publication number: 20080157339
    Abstract: A MEMS apparatus has a MEMS device sandwiched between a base and a circuit chip. The movable member of the MEMS device is attached at the side up against the circuit chip. The movable member may be mounted on a substrate of the MEMS device or formed directly on a passivation layer on the circuit chip. The circuit chip provides control signals to the MEMS device through wire bonds, vias through the MEMS device or a conductive path such as solder balls external to the MEMS device.
    Type: Application
    Filed: December 19, 2007
    Publication date: July 3, 2008
    Applicant: ANALOG DEVICES, INC.
    Inventors: Liam O Suilleabhain, Raymond Goggin, Eva Murphy, Kieran Harney
  • Publication number: 20080157340
    Abstract: The present invention discloses a structure of package comprising: a substrate with die receiving through holes, conductive connecting through holes and contact metal pads; a base attached on a portion of the lower surface of the substrate; multiple dice disposed within the die receiving through holes and attached on the base; multiple dielectric layers formed on the multiple dice and the substrate; multiple re-distribution layers (RDL) formed within the multiple dielectric layers and coupled to the multiple dice; a top layer formed over the RDL; and pluralities of terminal pads formed on the backside of the substrate and coupled to the RDL through the connecting through holes. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.
    Type: Application
    Filed: October 31, 2007
    Publication date: July 3, 2008
    Inventors: Wen-Kun Yang, Chun-Hui Yu, Chih-wei Lin
  • Publication number: 20080157341
    Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Wen-Kun Yang, Chun-Hui Yu, Chihwei Lin
  • Publication number: 20080157342
    Abstract: The present invention provides a semiconductor device package with a metal marking structure comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, wherein a terminal pad is formed under a lower surface of the substrate and a conductive trace formed on the lower surface of the substrate; a die attached within the die receiving cavity and having a plurality of bonding pads formed thereon; a first dielectric layer formed on the die and the substrate to expose the surface of the bonding pads and the through hole structure; a redistribution layer formed on the first dielectric layer to couple the bonding pads and the through hole structure; a second dielectric layer formed on the first dielectric layer and the redistribution layer trace; a metal marking layer formed on the second dielectric layer; and a heat sink layer formed on the metal marking layer.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 3, 2008
    Inventor: Wen-Kun Yang
  • Publication number: 20080157343
    Abstract: In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Sriram Dattaguru, Larry Binder, Cengiz A. Palanduz, Chris Jones, Dave Bach, Kaladhar Radhakrishnan, Timothe Litt
  • Publication number: 20080157344
    Abstract: A heat dissipation semiconductor package is disclosed according to the present invention. The heat dissipation semiconductor package comprises: a substrate that has a plurality of solder pads and at least one ground pad; a semiconductor chip that is mounted on the substrate and electrically connects to the solder pads; a plurality of passive elements that are mounted on the solder pads of the substrate; at least one metal bump or passive element of zero resistance, which are mounted on the at least one ground pad of the substrate; and a heat sink, which is capable of being mounted on the passive elements, and the at least one passive element of zero resistance or the metal bump, and the heat sink is electrically connecting to the at least one passive element of zero resistance or the metal bump, and then is further electrically coupling with the at least one ground pad of the substrate to form a ground return circuit, thus provides a shielding effect on electromagnetic interference (EMI).
    Type: Application
    Filed: April 4, 2007
    Publication date: July 3, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chin-Te Chen, Ke-Chuan Yang, Chung-Hsing Ko
  • Publication number: 20080157345
    Abstract: The formation of electronic assemblies is described. One embodiment relates to an electronic assembly including a die coupled to a substrate, the die including a curved surface. The assembly also includes a thermal interface material having a first curved surface and a second curved surface, the first curved surface coupled to the curved surface of the die. The assembly also includes a heat spreader having a curved surface, wherein the curved surface of the heat spreader is coupled to the second curved surface of the thermal interface material. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Daoqiang LU, Wei SHI
  • Publication number: 20080157346
    Abstract: A method for fabricating a heat-dissipating package and a heat-dissipating structure applicable thereto are disclosed. The method includes: mounting and electrically connecting to a chip carrier a semiconductor chip mounted with a heat-dissipating structure; disposing on the heat-dissipating structure a covering layer protrudingly formed with an abutting portion surrounding the covering layer, wherein the size of the heat-dissipating structure is greater than the predetermined one of the package to position the chip carrier in a cavity of a mold and encapsulate the heat-dissipating structure and semiconductor chip by encapsulant, and the protruding portion abuts against a top surface of the cavity and prevent the heat-dissipating structure from warping; and singulating the package and removing the encapsulant from the covering layer thereunder according to the predetermined size of the package.
    Type: Application
    Filed: April 26, 2007
    Publication date: July 3, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Min-Shun Hung, Ho-Yi Tsai, Chien-Ping Huang, Chun-Ming Liao, Cheng-Hsu Hsiao
  • Publication number: 20080157347
    Abstract: The present invention provides a heat spreader 1 which includes a substrate 7 composed of a metal-containing material and in which a second-component connection surface 6 of the substrate 7 is provided with wettability with a solder and a solder block layer 14 is formed in at least one of respective regions, adjacent to each other, of the second-component connection surface 6 and a side surface 13.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 3, 2008
    Applicant: A. L. M. T. Corp.
    Inventor: Kouichi Takashima
  • Publication number: 20080157348
    Abstract: The formation of electronic assemblies including a heat spreader coupled to a die through a thermal interface material is described. In one embodiment, the heat spreader includes a surface having a structure extending a distance outward therefrom. The thermal interface material includes a first region having a first thickness and a second region having a second thickness, the first thickness being smaller than the second thickness. The structure extending a distance outward from the heat spreader is positioned on the first region of the thermal interface material. The total of the first thickness of the thermal interface material and the distance the structure extends outward from the surface of the heat spreader is substantially the same as the second thickness. In one aspect of certain embodiments, the first region of the thermal interface material and the structure on the heat spreader are in alignment with a hot spot on the die. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Xuejiao HU, Chia-Pin CHIU
  • Publication number: 20080157349
    Abstract: An electrical assembly (100) includes an IC package (1), a CPU connector and a heat sink (14). The IC package comprises a substrate (11), a die (12) generating heat and located on the substrate and having an upper surface (123), a lower surface and a pair of side walls (121) and end walls (122) connecting the upper surface and the lower surface, and a load distributor frame (13) surrounding side walls (121) and end walls (122) of the die and having a top surface (131), a bottom surface attached on the substrate, an inner surface (133) and an outer surface (134). The load distributor is distant to the die.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Ming-Lun(Simon) Szu, David Gregory Howell
  • Publication number: 20080157350
    Abstract: Methods and apparatus to provide an improved package on package (PoP) design are described. In one embodiment, a central processing unit (CPU) package substrate and an embedded package (which may include one or more heat removal channels) are molded. Other embodiments are also described.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi
  • Publication number: 20080157351
    Abstract: A semiconductor device may includes a first semiconductor substrate provided on a second semiconductor substrate in a system-in-package arrangement. The first semiconductor substrate may include a plurality of through electrodes formed in first semiconductor substrate. The second semiconductor substrate may include a transistor layer formed over the second semiconductor substrate and a multilayer metal layer formed over the second semiconductor substrate. A plurality of connection electrodes for electrically connecting the first semiconductor substrate to the second semiconductor substrate.
    Type: Application
    Filed: October 30, 2007
    Publication date: July 3, 2008
    Inventor: Jae-Won Han
  • Publication number: 20080157352
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Shripad Gokhale, Kathy Wei Yan, Bijay S. Saha, Samir Pandey, Ngoc K. Dang, Munehiro Toyama
  • Publication number: 20080157353
    Abstract: A microelectronic device package interconnect for electrically connecting a plurality of substrates is provided. The microelectronic device package interconnect comprises an insulative layer positioned on a substrate, wherein the insulative layer has an opening extending through the insulative layer to the substrate. The microelectronic device package interconnect further comprises solder positioned in the opening.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Masako Watanabe, Masazumi Amagai
  • Publication number: 20080157354
    Abstract: A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 3, 2008
    Inventors: Fengyan Zhang, Sheng Teng Hsu
  • Publication number: 20080157355
    Abstract: A semiconductor device and methods of forming same are disclosed having multiple die redistribution layer. After fabrication of semiconductor die on a wafer and prior to singulation from the wafer, adjacent semiconductor die are paired together and a redistribution layer may be formed across the die pair. The redistribution layer may be used to redistribute at least a portion of the bond pads from the first die in the pair to a second die in the pair. One die in each pair will be a working die and the other die in each pair will be a dummy die. The function of the integrated circuit beneath the redistribution layer on the dummy die is at least partially sacrificed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Hem Takiar, Shrikar Bhagath
  • Publication number: 20080157356
    Abstract: Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Andrew Yeohi, Guotao Wang, Sairam Agraharam, Sudarshan Rangaraj
  • Publication number: 20080157357
    Abstract: A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.
    Type: Application
    Filed: May 29, 2007
    Publication date: July 3, 2008
    Inventors: Sung Min Kim, Min Suk Suh
  • Publication number: 20080157358
    Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through holes, a conductive connecting through holes structure and coupled a first contact pad on the upper surface of the substrate and a second contact pads on lower surface of the substrate; at least a die with metal pads disposed within the die receiving through holes; a surrounding material formed under the die and filled in the gap between the sidewall of die and sidewall of the die receiving though holes; a re-distribution layer (RDL) formed on the die, substrate and surrounding material; and coupled the metal pads of the die to the first contact pad; an isolating base having adhesion material formed over the RDL.
    Type: Application
    Filed: October 30, 2007
    Publication date: July 3, 2008
    Inventor: Wen-Kun Yang
  • Publication number: 20080157359
    Abstract: An electronic component according to the present invention includes a land 112 having a flat reference surface p1 and having a solder joint p3 to be solder bonded, wherein the solder joint p3 as a concave 113 recessed from the reference surface, and a nickel plate layer 114 is laminated on a surface of the land 112, and a position of an interface between (a) a tin-containing alloy layer 116 formed on the solder joint p3 of the nickel plate layer 114 in solder bonding the nickel plate layer 114 and (b) the nickel plate layer 114 deviates from a plane including the reference surface p1. This makes it possible to provide an electronic component including a solder joint which hardly cracks.
    Type: Application
    Filed: December 18, 2007
    Publication date: July 3, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masato Yokobayashi, Katsuyuki Tarui
  • Publication number: 20080157360
    Abstract: Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of conventional redistribution layers. An anisotropically conductive (z-axis) conductive layer in the form of a film or tape is applied to the active surface of a die and used as a base for conductive redistribution bumps formed on the anisotropically conductive layer, bonded to the ends of conductive columns thereof and wire bonded to the bond pads of the die. Packages so formed may be connected to substrates either with additional wire bonds extending from the conductive redistribution bumps to terminal pads or by flip-chip bonding using conductive bumps formed on the conductive redistribution bumps to connect to the terminal pads. The acts of the methods may be performed at the wafer level. Semiconductor die assemblies may be formed using the methods.
    Type: Application
    Filed: February 28, 2008
    Publication date: July 3, 2008
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Edmund Koon Tian Lua, Nam Yin Leng
  • Publication number: 20080157361
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact on a circuit side thereof in electrical communication with an integrated circuit, and a through interconnect in physical and electrical contact with the substrate contact configured to provide a signal path to a back side of the semiconductor substrate. The through interconnect includes an opening in the semiconductor substrate aligned with the substrate contact, and a projection on an interposer substrate (or alternately on a second semiconductor substrate) configured for mating physical engagement with the opening in the semiconductor substrate. The projection can also include a conductive via configured for electrical contact with a backside of the substrate contact and with a terminal contact for the component.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree
  • Publication number: 20080157362
    Abstract: A method of manufacturing a solder bump structure on a semiconductor device is provided. In one embodiment, a semiconductor substrate is provided having a bonding pad and a passivation layer formed thereabove, the passivation layer having an opening therein exposing a portion of the bonding pad. A first under bump metallization (UBM) layer is formed over the bonding pad and the passivation layer. A mask layer is placed over the first UBM layer, the mask layer having an opening therein exposing a portion of the first UBM layer. The mask layer is thereafter etched to create a recess at the edges between the first UBM layer and the mask layer. A second UBM layer is deposited in the opening of the mask layer, the second UBM layer filling the recess and a portion of the opening of the mask layer.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Blenny Chang, Hsiu-Mei Yu, Gil Huang, Sung-Cheng Chiu
  • Publication number: 20080157363
    Abstract: A method of forming a nanoscale structure includes providing a substrate having a first layer thereon, the first layer having an opening that exposes a region of the substrate, and contacting the substrate with a catalytic material, wherein the exposed region of the substrate has a first property that attracts the catalytic material, and the first layer has a second property that repels the catalytic material.
    Type: Application
    Filed: April 16, 2007
    Publication date: July 3, 2008
    Inventors: Subramanya Mayya Kolake, Sun-Woo Lee, In-Seok Yeo
  • Publication number: 20080157364
    Abstract: A display substrate having a fan-out and a method for manufacturing the display substrate are disclosed. The fan-out includes an insulating substrate, a first line, a second line, a resistance control pattern, and first and second detour pattern. The first line is disposed on the insulating substrate and is connected to a pad. The second line is formed from the same layer as the first line and is connected to a thin-film transistor (TFT). The resistance control pattern is formed from a different layer than the first and second lines. The first and second detour patterns are formed from a different layer than the first and second lines and the resistance control pattern, and connect the first and second lines with the resistance control pattern, respectively.
    Type: Application
    Filed: October 25, 2007
    Publication date: July 3, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Hoon YANG, So-Woon KIM, Chong-Chul CHAI, Joo-Ae YOUN, Kyoung-Ju SHIN, Yeon-Ju KIM, Soo-Wan YOON
  • Publication number: 20080157365
    Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Andrew Ott, Sean King, Ajay Sharma
  • Publication number: 20080157366
    Abstract: A semiconductor device and fabricating method thereof are disclosed. Embodiments relate to forming metal lines having a prescribed pattern over a lower insulating interlayer, forming a silicon oxide layer over surfaces of the metal lines and a surface of the lower insulating interlayer exposed between the metal lines, and forming an upper insulating interlayer over the silicon oxide layer.
    Type: Application
    Filed: December 11, 2007
    Publication date: July 3, 2008
    Inventor: Ji-Won Hyun
  • Publication number: 20080157367
    Abstract: A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer.
    Type: Application
    Filed: May 30, 2007
    Publication date: July 3, 2008
    Inventors: Soo Hyun KIM, Baek Mann KIM, Young Jin LEE, Dong Ha JUNG, Jeong Tae KIM
  • Publication number: 20080157368
    Abstract: A multi-layered metal line of a semiconductor device has a lower metal line and an upper metal line. The upper metal line includes a diffusion barrier, which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer.
    Type: Application
    Filed: May 31, 2007
    Publication date: July 3, 2008
    Inventors: Jeong Tae KIM, Baek Mann KIM, Soo Hyun KIM, Young Jin LEE, Dong Ha JUNG
  • Publication number: 20080157369
    Abstract: A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.
    Type: Application
    Filed: May 31, 2007
    Publication date: July 3, 2008
    Inventors: Jeong Tae Kim, Baek Mann Kim, Soo Hyun Kim, Young Jin Lee, Dong Ha Jung
  • Publication number: 20080157370
    Abstract: A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.
    Type: Application
    Filed: May 31, 2007
    Publication date: July 3, 2008
    Inventors: Dong Ha JUNG, Baek Mann KIM, Soo Hyun KIM, Young Jin LEE, Sun Woo HWANG, Jeong Tae KIM
  • Publication number: 20080157371
    Abstract: Disclosed are a metal line of a semiconductor device and a method of manufacturing the same. In one embodiment, the metal line includes a first interlayer dielectric layer pattern formed on a lower interconnection structure and having a via hole that exposes a lower interconnection of the lower interconnection structure, a first barrier pattern selectively covering a sidewall of the via hole and the lower interconnection, a second interlayer dielectric layer pattern on the first interlayer dielectric layer pattern and having a trench that exposes the via hole, a second barrier pattern covering an inner wall of the trench and the first barrier pattern, a seed pattern formed on the second barrier pattern, and a copper line formed on the seed pattern.
    Type: Application
    Filed: August 21, 2007
    Publication date: July 3, 2008
    Inventor: SEUNG HYUN KIM
  • Publication number: 20080157372
    Abstract: Provided is a method for forming a metal line of a semiconductor device. A trench is formed in an interlayer insulating layer formed on a semiconductor substrate. Copper is deposited in the trench to form a copper metal line, and a diffusion barrier layer is formed on the interlayer insulating layer and the copper metal line. A metal pad is formed on the diffusion barrier layer. In one embodiment, the diffusion barrier layer is formed of three layers, including TiSiN layers.
    Type: Application
    Filed: September 27, 2007
    Publication date: July 3, 2008
    Inventors: SUNG JOONG JOO, Han Choon Lee
  • Publication number: 20080157373
    Abstract: A metal line of semiconductor device and a method of forming the same are provided. An interlayer dielectric (ILD) layer is formed on a semiconductor substrate including a lower line. A via hole is formed in the ILD layer, and a diffusion barrier layer is formed on the ILD layer where the via hole is formed. A copper seed layer and a copper plating layer are repeatedly formed and etched until the hole is completely filled.
    Type: Application
    Filed: September 28, 2007
    Publication date: July 3, 2008
    Inventor: JI HO HONG
  • Publication number: 20080157374
    Abstract: A semiconductor device including an integrated device having a first device having a first pad part formed on a top metal layer, a second device arranged at the circumference of the first device and having a second pad part formed on the top metal layer, a connecting electrode electrically connecting the first pad part to the second pad part; and a bonding pad part connected the integrated device and connecting signals to the external.
    Type: Application
    Filed: October 17, 2007
    Publication date: July 3, 2008
    Inventor: Jae-Won Han
  • Publication number: 20080157375
    Abstract: Disclosed are a semiconductor device and a method for fabricating a metal interconnection of a semiconductor device. The method includes the steps of forming a dielectric layer on a semiconductor substrate including a lower interconnection, forming a trench in the interlayer dielectric layer that exposes the lower interconnection, forming a diffusion barrier in the trench and on the interlayer dielectric layer, forming a copper seed layer on the diffusion barrier, implanting a metal dopant into the copper seed layer, forming a copper metal interconnection on the copper seed layer into which the metal dopant is implanted, and forming an alloy layer from the copper seed layer and the metal dopant.
    Type: Application
    Filed: August 13, 2007
    Publication date: July 3, 2008
    Inventor: Han Choon Lee
  • Publication number: 20080157376
    Abstract: A semiconductor device and method for manufacturing the same are disclosed. A semiconductor device according to an embodiment comprises an interlayer insulating layer including a lower conductor wiring layer and a via hole exposing the lower conductor wiring layer, a conductor material filled inside the via hole, and an upper conductor wiring layer electrically connected to the lower conductor wiring layer through the conductor material filled inside the via hole. A barrier layer for inhibiting a loss of the conductor material filled inside the via hole is formed with a portion filling the upper portion of the via hole, and the upper conductor wiring layer is formed on the barrier layer.
    Type: Application
    Filed: October 30, 2007
    Publication date: July 3, 2008
    Inventor: JONG BOK LEE
  • Publication number: 20080157377
    Abstract: The present invention relates to a semiconductor device comprising a first wafer comprising an isolating layer formed on a silicon substrate, a barrier metal layer formed on the isolating layer, a first seed layer formed on the barrier metal layer, a first metal layer formed on the first seed layer, a surface of which is cleaned with NE14 or DHF, a barrier dielectric layer formed of SiCN on the first metal layer, a second seed layer formed on the barrier dielectric layer and a second metal layer formed on the second seed layer.
    Type: Application
    Filed: October 31, 2007
    Publication date: July 3, 2008
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Cheon Man Shim