Patents Issued in July 3, 2008
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Publication number: 20080157178Abstract: A flash memory device and fabricating method thereof are provided. A device isolating layer, a tunnel oxide film, and a floating gate can be formed on a substrate. An oxide-nitride-oxide (ONO) layer can be formed over the substrate, and a control gate can be formed on the ONO layer. A spacer can be formed of a high-temperature oxide film and a nitride film at sidewalls of the control gate.Type: ApplicationFiled: November 8, 2007Publication date: July 3, 2008Inventor: Dong Oog Kim
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Publication number: 20080157179Abstract: A nonvolatile memory device can include source selection lines, word lines, and a drain selection line formed over a substrate; spacers formed on sidewalls of the source selection lines and the drain selection line; source/drain electrodes having a lightly doped drain structure formed in the substrate; a buffer layer formed over the substrate including over the spacers; and a passivation layer composed of nitrogen gas formed over the buffer layer.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventor: Dong-Oog Kim
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Publication number: 20080157180Abstract: Cell gate patterns including first portions separated from each other with a first distance and second portions separated from each other with a second distance less than the first distance, and spacers are formed both sidewalls of the pair of cell gate patterns. The spacers formed on the sidewalls of the second portions are removed using a mask pattern. Accordingly, it is possible to prevent increase of an aspect ratio of a gap between the second portions with the small distance. Since the spacers formed on the sidewalls of the second portions separated from each other with the small distance are selectively removed, it is possible to minimize the increase of the aspect ratio of the gap between the second portions. Thus, it is possible to solve various problems which are caused due to occurrence of a void.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Inventor: Sung-Jin Kim
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Publication number: 20080157181Abstract: A non-volatile memory device and a fabrication method thereof. A high-k layer is formed between nitrogen-containing insulating layers. Accordingly, an interface reaction between an underlying oxide layer and the high-k insulating layer or between the oxide layer and a floating gate or a control gate can be prohibited and the electrical characteristics of the high-k layer can be improved, and a non-volatile memory device with high performance and high reliability can be fabricated.Type: ApplicationFiled: December 26, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jae Mun Kim, Jae Hyoung Koo, Dong Ho Lee, Kwon Hong, Woo Ri Jeong, Hee Soo Kim, Seung Woo Shin
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Publication number: 20080157182Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Inventors: Seung-hwan Song, Suk-pil Kim, Yoon-dong Park, Won-joo Kim, June-mo Koo, Kyoung-Iae Cho, Jae-Woong Hyun, Sung-jae Byun
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Publication number: 20080157183Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventors: Yukio Hayakawa, Hiroyuki Nansei
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Publication number: 20080157184Abstract: A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.Type: ApplicationFiled: January 3, 2007Publication date: July 3, 2008Inventors: Erh-Kun Lai, Yen-Hao Shih, Tzu-Hsuan Hsu, Shih-Chin Lee, Jung-Yu Hsieh, Kuang-Yeu Hsieh
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Publication number: 20080157185Abstract: A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer.Type: ApplicationFiled: June 29, 2007Publication date: July 3, 2008Applicant: Hynix Semiconductor IncInventors: Moon Sig Joo, Seung Ho Pyi, Yong Soo Kim
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Publication number: 20080157186Abstract: A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Inventors: Wan-jun Park, Jo-won Lee, Sang-hun Jeon, Chung-woo Kim
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Publication number: 20080157187Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width.Type: ApplicationFiled: March 14, 2008Publication date: July 3, 2008Applicant: SPANSION LLCInventors: Weidong QIAN, Mark T. RAMSBEY, Tazrien KAMAL
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Publication number: 20080157188Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.Type: ApplicationFiled: February 26, 2008Publication date: July 3, 2008Inventors: Brent Alan Anderson, Andres Bryant, William F. Clark, Edward Joseph Nowak
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Publication number: 20080157189Abstract: Disclosed is a power semiconductor device capable of transmitting a gate signal from any upward, downward, leftward, and rightward directions on a plane to reduce deviation in the gate signal's transmission speed and impedance.Type: ApplicationFiled: October 25, 2005Publication date: July 3, 2008Inventors: Young Won Lee, Moon Soo Cho
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Publication number: 20080157190Abstract: A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.Type: ApplicationFiled: June 26, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Tae Kyun Kim
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Publication number: 20080157191Abstract: A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate.Type: ApplicationFiled: October 1, 2007Publication date: July 3, 2008Applicant: Hynix Semiconductor Inc.Inventor: Kang Sik CHOI
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Publication number: 20080157192Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a second conduction type base region in the substrate, a high concentration first conduction type source region in the base region, and first and second trenches. The source region is formed in an opposite side of the substrate. The first and second trenches pass through the source region and the base region, and the first and second trenches have different widths and shapes, respectively.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Inventor: Sung Man PANG
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Publication number: 20080157193Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type on the semiconductor substrate, a base region of a second conductivity type on the epitaxial layer, the base region including subregions spaced apart from one another by a predetermined distance, a source region of the first conductivity type on the base region, a drain region of the first conductivity type between the subregions of the base region, a trench penetrating through the source region and the base region, a first gate conductive layer within the trench, and a second gate conductive layer on an exposed portion of the base region.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventor: Sung Man Pang
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Publication number: 20080157194Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.Type: ApplicationFiled: February 5, 2008Publication date: July 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Sam LEE, Min-Hee CHO
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Publication number: 20080157195Abstract: A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.Type: ApplicationFiled: December 26, 2007Publication date: July 3, 2008Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
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Publication number: 20080157196Abstract: A DMOS device and a method for fabricating the same are provided. A drift region and a well region are formed simultaneously to provide a DMOS device with the drift and well regions having the same depth. This DMOS device includes a high voltage transistor area and a low voltage transistor area, a drift diffused region formed in the high voltage transistor area, and a well region formed in the low voltage transistor area. A drift diffused region and a well region in the low voltage area are formed simultaneously to reduce the number of ion implantation processes, thereby simplifying the manufacturing process.Type: ApplicationFiled: December 28, 2007Publication date: July 3, 2008Inventor: Duck Ki Jang
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Publication number: 20080157197Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventors: Robin Hsieh, Tsai Chun Lin, Albert Yao, Pai-Kang Hsu, Tsung-Yi Huang, Ruey-Hsin Liu
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Publication number: 20080157198Abstract: A high-voltage semiconductor device capable of preventing a substrate current from forming is disclosed. The method of manufacturing the high-voltage semiconductor device comprises forming a well in a semiconductor substrate, forming a device isolation film in a portion of the semiconductor substrate, forming a series of drift regions below the surface of the semiconductor substrate, forming a gate electrode on the surface of the semiconductor substrate so as to overlap a portion of at least one drift region, and forming a source and a drain region below the surface of the semiconductor substrate drift regions formed on opposing sides of the gate electrode. Advantageously, the substrate current of the semiconductor device is reduced and the operational withstand voltage is increased, improving the characteristics of the high-voltage transistor.Type: ApplicationFiled: October 28, 2007Publication date: July 3, 2008Applicant: DONGBU HITEK CO., LTD.Inventors: Ji Hong KIM, Sang Hun JUNG
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Publication number: 20080157199Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.Type: ApplicationFiled: March 16, 2007Publication date: July 3, 2008Inventors: Vidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
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Publication number: 20080157200Abstract: The present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the source/drain regions that contacts an embedded stressor material. Considering that the facet in the prior art is due to an STI divot formed during several necessary wet etching processes, the MOSFET source/drain edge of the inventive structure is surrounded by a liner to prevent facet growth during the epitaxial growth of the stressor material. As such, a part of the semiconductor substrate edge is preserved. The liner employed in the present invention is a stress engineering material such as, for example, silicon nitride.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Applicant: International Business Machines CorporationInventors: Byeong Y. Kim, Shahid A. Butt, Xiaomeng Chen, Shwu-Jen J. Jeng, Hasan M. Nayfeh, Deepal Wehella-Gamage
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Publication number: 20080157201Abstract: A semiconductor device includes a fin-fuse and an SOI transistor. The SOI transistor is located on an SOI substrate and has a source region and a drain region. The fin-fuse is connected to one of the source/drain regions and has a fusible link located on the SOI substrate. The fusible link has a homogeneous dopant concentration.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: Texas Instruments IncorporatedInventor: Andrew Marshall
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Publication number: 20080157202Abstract: Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, Toshiharu Furukawa, Charles Koburger, Jack A. Mandelman, William Tonti
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Publication number: 20080157203Abstract: A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.Type: ApplicationFiled: December 12, 2007Publication date: July 3, 2008Inventor: Hyun-Soo Shin
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Publication number: 20080157204Abstract: Embodiments relate to a device for protecting a semiconductor IC device from an electrostatic discharge (ESD). According to embodiments, the device may have a rapid response speed and a stable operation against an ESD and may efficiently protect an internal circuit of a semiconductor IC from an ESD voltage lower than a junction breakdown voltage. According to embodiments, the device for protecting the semiconductor IC may include a pad, an internal circuit electrically connected to the pad, and a protection circuit which forms a discharge path between the pad and the internal circuit and disconnects the pad and the internal circuit, when an overvoltage due to an electrostatic discharge is applied to the pad.Type: ApplicationFiled: October 11, 2007Publication date: July 3, 2008Inventor: Sang-Soo Song
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Publication number: 20080157205Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.Type: ApplicationFiled: June 20, 2007Publication date: July 3, 2008Applicant: Hynix Semiconductor Inc.Inventors: Min-Gyu SUNG, Hong-Seon Yang, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim
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Publication number: 20080157206Abstract: A manufacturing method of a semiconductor device includes a step of defining an element region by etching a semiconductor substrate using a first dielectric film as a mask, a step of reducing the first dielectric film by isotropic etching, a step of forming a side wall on a side surface of the reduced first dielectric film, a step of removing the first dielectric film, and a step of forming a trench in the element region by etching using the side wall as a mask to form a plurality of fin portions at the element region.Type: ApplicationFiled: October 16, 2007Publication date: July 3, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Noriaki MIKASA
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Publication number: 20080157207Abstract: A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.Type: ApplicationFiled: March 7, 2008Publication date: July 3, 2008Applicant: INTEL CORPORATIONInventors: Willy Rachmady, Brian S. Doyle, Jack T. Kavalieros, Uday Shah
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Publication number: 20080157208Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
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Publication number: 20080157209Abstract: An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.Type: ApplicationFiled: March 17, 2008Publication date: July 3, 2008Inventor: Sehat Sutardja
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Publication number: 20080157210Abstract: This invention relates to a high-linearity and high-power CMOS structure and a method for the same and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain. An electric field is provided to significantly improve the RF linearity and output power of the CMOS component.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Applicant: Chang Gung UniversityInventors: Hsien-Chin Chiu, Chien-Cheng Wei, Wei-Hsien Lee, Wu-Shiung Feng
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Publication number: 20080157211Abstract: An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Applicant: Qimonda AGInventor: Peng-Fei Wang
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Publication number: 20080157212Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy
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Publication number: 20080157213Abstract: A method includes preparing a semiconductor substrate having a cell region, a core NMOS region, and a core PMOS region; defining a cell active region, an NMOS active region, and a PMOS active region in the cell region, the core NMOS region, and the core PMOS region, respectively, by forming an isolation layer in predetermined regions of the semiconductor substrate; forming a cell gate pattern, an NMOS gate pattern, and a PMOS gate pattern crossing the cell active region, the NMOS active region, and the PMOS active region, respectively; forming an interlayer-insulating layer on the semiconductor substrate having the gate patterns; simultaneously forming a storage node landing pad, a bit line landing pad, and NMOS landing pads; and patterning the interlayer-insulating layer of the core PMOS region to form PMOS interconnection contact holes that expose predetermined regions of the PMOS active region adjacent to the PMOS gate pattern.Type: ApplicationFiled: February 29, 2008Publication date: July 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Je-Min PARK
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Publication number: 20080157214Abstract: A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.Type: ApplicationFiled: February 27, 2008Publication date: July 3, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Kazuaki Nakajima, Kyoichi Suguro
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Publication number: 20080157215Abstract: Structures for reducing or even preventing the diffusion from an NFET side of a gate to a PFET side of the gate in a semiconductor device are disclosed, as well as manufacturing methods thereof. A diffusion barrier is formed in the shared gate at the N/P boundary between the NFET and the PFET. The diffusion barrier is doped with one or more types of ions, such as, but not limited to, oxygen, nitrogen, fluorine, silicon, germanium, or xenon ions. By using a diffusion barrier as disclosed herein, the diffusion of ions through a common gate from the NFET side to the PFET side in a CMOS technology semiconductor device node may be significantly reduced or even prevented altogether. This may further result in relatively higher performance of the NFET/PFET pair.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventor: Katsura Miyashita
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Publication number: 20080157216Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.Type: ApplicationFiled: January 3, 2007Publication date: July 3, 2008Applicant: International Business Machines CorporationInventors: Deok-kee Kim, Seong-Dong Kim, Oh-Jung Kwon
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Publication number: 20080157217Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Peter A. Burke, Sallie Hose, Sudhama C. Shastri
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Publication number: 20080157218Abstract: A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semiconductor substrate and the gate electrode and having a plurality of contact holes formed therein, and contact plugs formed within the contact holes. The contact plugs can include a first contact plug and a second contact plug electrically connected to the gate electrode, and a third contact plug and a fourth contact plug electrically connected to the source/drain regions.Type: ApplicationFiled: December 14, 2007Publication date: July 3, 2008Inventor: Jung-Ho Ahn
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Publication number: 20080157219Abstract: In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.Type: ApplicationFiled: March 12, 2008Publication date: July 3, 2008Inventors: Tsuyoshi FUJIWARA, Masahiro Ushiyama, Katsuhiko Ichinose, Naohumi Ohashi, Tetsuo Saito
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Publication number: 20080157220Abstract: A semiconductor device and a manufacturing method thereof are provided. A gate electrode and source/drain areas are disposed on a semiconductor substrate, and an interlayer dielectric layer is on the gate electrode, the source/drain areas, and the semiconductor substrate. Metal silicide layers are disposed in the gate electrode and the source/drain areas at regions exposed by contact holes.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Inventor: SUNG JOONG JOO
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Publication number: 20080157221Abstract: A method of manufacturing a semiconductor device for decreasing a chip area by changing a connecting structure of pull up transistors and pull down transistors are disclosed. The semiconductor device can include pull up and pull down transistors including a first pull down transistor, a first pull up transistor, a second pull up transistor and a second pull down transistor, the first pull down transistor, the first pull up transistor, the second pull up transistor and the second pull down transistor being sequentially arranged in a series form on a SRAM, and line type contacts and metal lines formed on the respective pull up and pull down transistors.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventor: Yong-Geun Lee
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Publication number: 20080157222Abstract: A differential pair of an RF integrated circuit device is disclosed. The differential pair of the integrated circuit device includes a first MOS formed by a multiple finger configuration, having a plurality of first gate fingers; a second MOS formed by the multiple fingers configuration, having a plurality of second gate fingers, wherein each two first gate fingers interdigitate with each two second gate fingers.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Applicant: MEDIATEK INC.Inventor: YuJen Wang
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Publication number: 20080157223Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Lee Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Zhao Lun, Shailendra Mishra
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Publication number: 20080157224Abstract: A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
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Publication number: 20080157225Abstract: Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a multi-gate SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a multi-gate logic transistor to improve performance of SRAM and logic transistors formed on the same substrate. In another embodiment, to reduce cell area, a first SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a second multi-gate SRAM transistor.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Suman Datta, Brian S. Doyle, Jack T. Kavalieros, Yih Wang
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Publication number: 20080157226Abstract: A MOS transistor capable of withstanding significant currents, having doped areas corresponding to first and second main terminals of elementary MOS transistors and having, in top view, the shape of parallel strips separated by gate regions; first conductive elements which do not extend on the doped areas corresponding to the second main terminals and dividing into first fingers extending at least partly on the doped areas corresponding to the first main terminals and connected thereto; and second conductive elements which do not extend on the doped areas corresponding to the first main terminals and divide into second fingers extending at least partly on the doped areas corresponding to the second main terminals and connected thereto, the second fingers being at least partly intercalated with the first fingers.Type: ApplicationFiled: December 26, 2007Publication date: July 3, 2008Applicant: STMicroelectronics S.A.Inventors: Sandrine Majcherczak, Carlo Tinella, Olivier Richard, Andreia Cathelin
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Publication number: 20080157227Abstract: An objective of the present invention is to provide a more miniaturized semiconductor device while maintaining low-resist contact. A semiconductor device comprises transistors Tr1, Tr2, a first contact 13 and second contacts 10. The transistors Tr1, Tr2 are formed on a semiconductor substrate 1 and adjacent to each other. The first contact 13 is formed between the transistors Tr1, Tr2 in a self-alignment structure, connected to a common source to the transistors Tr1, Tr2 and contains a metal. The second contacts 10 are connected to the drains in the transistors Tr1, Tr2, respectively and contain a metal.Type: ApplicationFiled: December 20, 2007Publication date: July 3, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Kazutaka Manabe