Abstract: Apparatus for sanitizing objects by use of ultraviolet light includes an enclosed container defining a first object entry opening and a second object exit opening. A first inclined slide is mounted within the container and is positioned adjacent to the first entry opening, and a second inclined slide is mounted within the container beneath the first slide and positioned adjacent to the second exit opening. The slides are positioned at angles with respect to horizontal such that the pull of gravity on the objects moving down each of the slides is greater than restraining electrostatic or frictional forces on the objects. A baffle is mounted within the container and is positioned with respect to the slides for redirecting objects from the first slide onto the second slide, and ultraviolet light sources are mounted in the container and positioned above the slides for irradiating the objects as they move down the slides.

Abstract: An optical detection apparatus and method thereof is provided, which is applicable for detecting the image signals of a labeled sample. First, a laser module provides excitation light, and the excitation light is continuously reflected by a scan module for providing linear scanning light by changing a reflection angle. The carrier moves the light module in a direction nonparallel to the linear direction so as to provide a two-dimensional testing zone. The labeled sample placed in the testing zone is excited by the linear scanning light and generates emission light to be received by the light receiver. Therefore, the light receiver forms the image signals of the labeled sample corresponding to the emission light.

Abstract: A free-space standoff optical detection platform for any detection scheme based on spontaneous emissions, such as for example, fluorescence detection. More particularly, the present invention relates to a detection system having SPCE beads. In one embodiment, the SPCE beads are dielectric spheres coated with a thin metal layer, which supports surface plasmon resonance (SPR) at the operation wavelength. For fluorescence detection, fluorescence reporters can be coated outside of SPCE beads. Upon the presence of the analyte, the fluorescence reporter changes its emitting signal. The SPCE beads amplify the field strength of the excitation via the lens effect and SPR enhancement. The spontaneous emitting signal is collected via the coupling between the SPR and emission, which results high collection efficiency and signal-to-noise ratio. This surface plasmon-coupled emission (SPCE) signal propagates in the beads in a curved path dictated by the SPR condition.

Abstract: Some embodiments include reception of a first instruction to enter an imaging mode, and, in response to the first instruction, automatic performance of at least one of: reduction of a focal spot size of a radiation beam, movement of a flattening filter out of a path of the radiation beam, replacement of a first target for photon emission with a second target for photon emission, or movement of a scatter-reducing filter into the path of the radiation beam. Embodiments may further include reception of a second instruction to enter a first radiation treatment mode, and, in response to the second instruction, automatic performance at least one of: increase of a focal spot size of the radiation beam, movement of the flattening filter into the path of the radiation beam, replacement of the second target with the first target, or movement of the scatter-reducing filter out of the path of the radiation beam.

Abstract: An exposure apparatus includes a loading device, a first energy-producing device, and a second energy-producing device. The loading device comprises a plurality of supporting elements, supporting a panel. The first and second energy producing devices are disposed above and below the loading device, respectively.

Abstract: Methods (300, 400) are described for calibrating the implantation angle of an ion implanter utilized in the manufacture of semiconductor products. One method (300) includes implanting (330) phosphorous ions into a pilot wafer held by a wafer platen held at a starting implantation angle in the ion implanter. The phosphorous implantation into a p-doped substrate of the pilot or blank wafer, for example, forms a semiconductive sheet. The method (300) then includes changing the implantation angle (340), and implanting another wafer (330) with phosphorous ions. The angle changing (340) and implanting (330) of other wafers continues in this manner until all wafers or angles are implanted (350) as desired. The phosphorous implanted wafers are then measured (360) with a four-point probe, for example, to obtain the sheet resistance of all the implanted wafers.

Abstract: A technique for tuning an ion implanter system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for tuning an ion implanter system having multiple beam-line elements. The method may comprise establishing one or more relationships among the multiple beam-line elements. The method may also comprise adjusting the multiple beam-line elements in a coordinated manner, based at least in part on the one or more established relationships, to produce a desired beam output.

Abstract: A technique for boron implantation is disclosed. In one particular exemplary embodiment, the technique may be realized by an apparatus for boron implantation. The apparatus may comprise a reaction chamber. The apparatus may also comprise a source of pentaborane coupled to the reaction chamber, wherein the source is capable of supplying a substantially pure form of pentaborane into the reaction chamber. The apparatus may further comprise a power supply that is configured to energize the pentaborane in the reaction chamber sufficiently to produce a plasma discharge having boron-bearing ions.

Abstract: A system, method and program product for determining parallelism of an ion beam using a refraction method, are disclosed. One embodiment includes determining a first test position of the ion beam while not exposing the ion beam to an acceleration/deceleration electrical field, determining a second test position of the ion beam while exposing the ion beam to an acceleration/deceleration electrical field, and determining the parallelism of the ion beam based on the first test position and the second test position. The acceleration/deceleration electrical field acts to refract the ion beam between the two positions when the beam is not parallel, hence magnifying any non-parallelism. The amount of refraction, or lateral shift, can be used to determine the amount of non-parallelism of the ion beam. An ion implanter system and adjustments of the ion implanter system based on the parallelism determination are also disclosed.

Abstract: A specimen fabrication apparatus, including: an ion beam irradiating optical system to irradiate a sample placed in a chamber, with an ion beam, a specimen holder to mount a specimen separated by the irradiation of the ion beam, a holder cassette to hold the specimen holder, and a sample stage to hold the sample and the holder cassette, wherein said holder cassette is transferred to outside of the chamber in a condition of holding said specimen holder with the specimen mounted.

Abstract: A specimen fabrication apparatus including: a vacuum chamber that accommodates a sample stage to mount a sample, an irradiating optical system that irradiates a focused ion beam to the sample to form a specimen, and a specimen holder placed in the vacuum chamber, to which said formed specimen is transferred by transferring means while the specimen chamber remains substantially sealed.

Abstract: A system for analyzing a semiconductor device, including: a first specimen fabricating apparatus including: a vacuum chamber in which a sample substrate is placed, an ion beam irradiating optical system for forming a specimen on the sample substrate, a specimen holder to mount the specimen, and a probe for removing the specimen from the sample substrate; a second specimen fabricating apparatus, and an analyzer to analyze the specimen, wherein said first specimen fabrication apparatus has a function to separate the specimen mounted on the specimen holder and the probe in a vacuum condition.

Abstract: An electron beam control method has the following steps, selecting one of a plurality of pattern openings by a character beam electrode having a plurality of electrode units to allow an electron beam to pass through any pattern opening on an aperture mask on which the plurality of pattern openings are formed, determining whether or not a synchronization error of deflected operation of the electron beam performed by the plurality of electrode units is equal to or less than a tolerance, determining whether or not the electron beam is irradiated with a sample by selecting the pattern openings in sequence by the character beam electrode in a state of controlling a path of the electron beam by a blanking electrode not to irradiate the sample with the electron beam, when determined that the synchronization error is equal to or less than the tolerance, and decreasing the tolerance when determined that the electron beam is irradiated with the sample.

Abstract: A particle beam therapy system comprises a charged particle beam generator for generating a charged particle beam, two or more treatment rooms provided with respective irradiation devices for irradiating the charged particle beam, a beam line for transporting the charged particle beam extracted from the charged particle beam generator to the irradiation device in selected one of the two or more treatment rooms, a beam detection processing/control unit for monitoring a beam state of the charged particle beam in one of the two or more irradiation devices, and a selector for switchably selecting one of the irradiation devices which is to be monitored by the beam detection processing/control unit. The selector is controlled such that the selector establishes connection with the irradiation device in the selected one treatment room to which the charged particle beam is transported through the beam line. The system configuration can be simplified while maintaining the operation efficiency.

Abstract: The Smith Purcell effect, in which a beam of electrons passes close to a conducting grating and induces electromagnetic radiation from the grating surface, can be used as a source of THz radiation. A grating composed of negative index metamaterial (NIM) enhances the output of the Smith Purcell source. Of particular interest is the use of a NIM grating in a Smith-Purcell source to provide a tunable coherent CW source of terahertz (THz) radiation.

Abstract: A lithographic apparatus includes a radiation system including a radiation source for the production of a radiation beam, and a contaminant trap arranged in a path of the radiation beam. The contaminant trap includes a plurality of foils or plates defining channels which are arranged substantially parallel to the direction of propagation of said radiation beam. The foils or plates are oriented substantially radially with respect to an optical axis of the radiation beam. The contaminant trap is provided with a gas injector which is configured to inject gas at least at two different positions directly into at least one of the channels of the contaminant trap.

Abstract: An optical information readout apparatus is disclosed having an image forming optical section 4 operative to shift first and second lenses 24, 25 along an optical axis “O” at areas in front of a photodetector 3. A cylindrical body 23 incorporates a lens holder means, including permanent magnets 26 to 28, by which the first lens 24 is halted and held in any of positions a1, a2 and the second lens 24 is halted and held in any of positions b1, b2. Coils 31, 32, 75, 76 and a control circuit 16 drivingly shift the lenses. The control circuit is operative to independently move the lenses to change a focusing range of the image forming optical section in four different stages in the occurrence of a failure in reading out a two-dimensional code.

Abstract: A method and system for controlling image quality in processing radiographic photothermographic sheet media. A cassette removably contains radiographic photothermographic sheet media and also has an information member. The information member stores information including size of the sheet media stored in the cassette and calibrated conditions for processing the sheet media. A thermal media processor processes an exposed sheet media in accordance with the calibrated processing conditions.

Abstract: The present invention is directed to a radiation image reading system. The system includes a radiation source for irradiating a radiation toward a subject. The radiation source has a size “D”. A radiation detector in which large number of detecting devices for detecting the radiation transmitted through the subject are arranged in an array form, for generating an image signal of the subject by detecting the radiation transmitted through the subject by each of the detecting devices. An aperture of each of the detecting devices has a size “A”. Also included is a sampling section for sampling the image signal. The size A of the aperture fulfills a condition of B?A?2B. B is a size of a penumbra on the radiation detector. The size B of the penumbra is represented by B=Dx (R2/R1), where R1 is a distance from the radiation source to the subject and R2 is a distance from the subject to the radiation detector.

Abstract: A memory cell device includes a bottom electrode, pipe shaped member comprising phase change material and a top electrode in contact with the pipe-shaped member. An electrically and thermally insulating material is inside the pipe-shaped member. An integrated circuit including an array of pipe-shaped phase change memory cells is described.

Abstract: A lateral phase change cell may be formed over a semiconductor substrate. The lateral cell, in some embodiments, may be exposed to light so that the same cell may be addressed by both optical and electrical signals.

Abstract: One aspect of the present invention is directed to a heterojunction bipolar transistor (HBT) comprising: a substrate; a buffer layer of undoped semiconductor material; a sub-collector layer; a collector layer; a base layer; an emitter layer; a emitter cap layer; and a contact layer; wherein a planar doping sheet is included between the substrate layer and the collector layer; and a collector electrode in electrical connection to said collector layer; a base electrode in electrical connection with said base layer; and an emitter electrode provided in electrical connection to said emitter layer.

Abstract: A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

Abstract: To provide a semiconductor display device capable of displaying an image having clarity and a desired color, even when the speed of deterioration of an EL layer is influenced by its environment. Display pixels and sensor pixels of an EL display each have an EL element, and the sensor pixels each have a diode. The luminance of the EL elements of each in the display pixels is controlled in accordance with the amount of electric current flowing in each of the diodes.

Abstract: The invention discloses an organic electroluminescent device comprising a pixel element. The pixel element comprises a substrate comprising a control area and a sensitive area, a switch device and a driving device overlying the control area, a photo diode serving as a photo sensor overlying the sensitive area, an OLED element disposed in the sensitive area and illuminating to the photo sensor, and a capacitor coupled to the photo sensor and the driving device. Specifically, a photo current corresponding to a brightness of the OLED element is generated by the photo diode responsive to the OLED element illuminating the photo diode such that a voltage of the capacitor is adjusted by the photo current to control the current passing through the driving device, thus changing the illumination of the OLED element. A method for fabricating the OLED is also provided.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.

Abstract: A light assembly for use with a low voltage power source. The light assembly semiconductor photo-emitters are electrically in series with a higher forward voltage drop than the associated low voltage power supply. To provide the necessary voltage the light assembly includes a current regulated step-up DC/DC converter. The semiconductor photo-emitters that are electrically in series are in the form of a monolithic light emitting diode array with a plurality of light emitting diode elements electrically and mechanically in series with a conductive, rigid bond region between the cathode region of the first light emitting diode element and the anode region of the second light emitting diode element. The first and second light emitting diode elements may differ in band gaps to emit different colors, that are additive to a non-primary color, such as white.

Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.

Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.

Abstract: A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.

Abstract: A four terminal field effect device comprises a silicon field effect device with a silicon N-type semiconductor channel and an N+ source and drain region. An insulator is deposited over the N-type semiconductor channel. An organic semiconductor material is deposited over the insulator gate forming a organic semiconductor channel and is exposed to the ambient environment. Drain and source electrodes are deposited and electrically couple to respective ends of the organic semiconductor channel. The two independent source electrodes and the two independent drain electrodes form the four terminals of the new field effect device. The organic semiconductor channel may be charged and discharged electrically and have its charge modified in response to chemicals in the ambient environment. The conductivity of silicon semiconductor channel is modulated by induced charges in the common gate in response to charges in the organic semiconductor channel.

Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: An exemplary array of thermally-assisted magnetic memory structures includes a plurality of magnetic memory elements, each magnetic memory element being near a diode. A diode near a selected magnetic memory element can be heated by absorbing energy from a radio frequency electromagnetic field. The heated diode can be used to elevate the temperature of the selected magnetic memory element to thermally assist in switching the magnetic state of the magnetic memory element upon application of a write current.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: Disclosed are a CMOS image sensor and a fabrication method thereof, which is adequate to reduce dark current. The CMOS image sensor comprises a device isolation region and an active region, which are formed on a semiconductor substrate; a photocharge generating portion formed on the active region for absorbing light externally and generating and accumulating charges; a transistor portion including at least one transistor for processing the charges accumulated in the photocharge generating portion; and a control terminal for preventing dark current from being introduced into the photocharge generating portion, and ejecting the dark current after temporally storing the dark current. The control terminal is operated to store the dark current for an integration time when a photodiode as the photocharge generating portion receives light, and eject the stored dark current by being grounded when the reset transistor is turned on.

Abstract: An aspect of the present invention is a thin film device. The thin film device includes at least one patterned thin film layer, a thermally conductive material coupled to at least one of the patterned thin-film layer and an electrically and thermally isolating material in contact with the thermally conductive material.

Abstract: A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor. The invention also relates to a display device and an arrangement for controlling a display device, which each comprise a non-volatile semiconductor memory.

Abstract: A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.

Abstract: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

Abstract: A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.

Abstract: Performance matching devices in SOI are improved by thermally isolating matched devices within a continuous body of active material. Matched devices are isolated by an insulating wall of silicon dioxide (which surrounds the devices) and the oxide layer beneath, and are arranged to minimize effects from external thermal sources.

Abstract: A thin-film transistor, such as a top-gate thin-film transistor, is provided herein. The thin-film transistor has a performance-enhancing layer, such as a performance-enhancing bottom layer, comprising a polymer other than a polyimide. In specific embodiments, the polymer is selected from the group consisting of polysiloxane, polysilsesquioxane, and mixtures thereof. In other embodiments, it is a self-assembling polymeric monolayer of a silane agent and an organophosphonic acid. The performance-enhancing layer directly contacts the substrate. The layer improves the carrier mobility and current on/off ratio of the thin film transistor.

Abstract: A FEOL/MEOL metal resistor that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure into a CMOS technology are provided.

Abstract: A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The lateral bipolar transistor includes an n-type emitter coupled to the first pad and an n-type collector coupled to the second pad. The emitter and collector are located in a p-well, which forms the base of the transistor. The p-well is located in an isolating n-well, which in turn, is located in a p-type substrate. The n-well is coupled to receive the VDD supply voltage and the p-substrate is coupled to a VSS reference voltage. A dielectric region can be located between the emitter and collector (in the p-well).

Abstract: According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situated between the first and second active regions. The ESD protection structure further includes at least one contact-via chain connected to the first active region, where the at least one contact-via chain includes a contact connected to a via. The at least one contact-via chain forms a ballast resistor for increased ESD current distribution uniformity. The contact is connected to the via by a first metal segment situated in a first interconnect metal layer of a die. The at least one contact-via chain is connected between the first active region and a second metal segment situated in a second interconnect metal layer of the die.

Abstract: A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.