Abstract: A method is described for determination of the content of at least one component of a sample by means of a nuclear magnetic resonance pulse spectrometer, with the magnetization of the sample being influenced by a sequence of radio-frequency pulses such that the signal amplitudes to be observed can be determined. The magnetization of the sample is initially saturated, and the signal amplitudes which are determined at each time by the longitudinal and transverse relaxation times T1 and T2 and/or T2* and/or T1p, from which a value for the content of the at least one component is determined, are measured at the same time in a cohesive experimental procedure.

Abstract: A fast and efficient method for reconstructing an image from undersampled, parallel MRI data sets acquired with non-Cartesian trajectories includes the calculation of unsampled k-space data from the acquired k-space data and sets of calculated reconstruction coefficients. To reduce the computation time, only a few reference reconstruction coefficients are calculated using a matrix inversion step and the remaining reconstruction coefficients are produced by interpolating between the reference reconstruction coefficients.

Abstract: A Class-E amplifier has been adapted for use in the radio frequency section that drives a transmit coil of a magnetic resonance imaging (MRI) system. The Class-E amplifier responds to a radio frequency carrier signal and a control signal by producing a radio frequency excitation signal for driving the transmit coil. The Class-E amplifier includes a pickup coil that senses a signal emitted from the transmit coil and produces a feedback signal that is used to alter the control signal and thereby control production of the radio frequency excitation signal.

Abstract: A magnetic resonance imaging (MRI) device for imaging a volume includes a main magnet for generating a magnetic field, an insulator sheet formed into a tube extending along an axis, a gradient coil disposed on an outside surface defining the tube for manipulating the magnetic field generated by the main magnet to image the volume, and a cooling circuit disposed between the gradient coil and a RF coil. The cooling circuit is disposed on an opposite inside surface defining the tube, wherein the cooling circuit shields the gradient coil from the RF coil while cooling the gradient coil.

Abstract: A surface coil arrangement of a gradient system for an MR tomography apparatus has coil elements mounted on a first antenna, the antenna being extendable by at least one further antenna that likewise includes an arrangement of at least one coil element, and which is detachably or movably fastened to the first antenna.

Abstract: A nuclear magnetic resonance probe head comprising at least two orthogonal coil/resonator configurations A1 and A2 having different resonance frequencies, wherein at feast one of the coil/resonator configurations A1 has two saddle-shaped coils S1 and S2, wherein each coil has a window about which N windings are disposed which are connected in series, wherein N?2. Each coil S1 and S2 is formed mirror-symmetrically relative to a central plane of the respective coil, which is perpendicular to the window of the respective coil, wherein the central planes of the coils S1 and S2 are identical to minimize the electromagnetic coupling between the two coil/resonator configurations A1 and A2 at the resonance frequency of A2. The NMR probe head reduces coupling between the two coil/resonator configurations.

Abstract: An apparatus for determining a quantitative property of a sample substance by means of magnetic resonance is disclosed. The apparatus comprises a conveyor for conveying sample containers containing the sample substance through a measuring station. The measuring station comprises a magnet system for generating a constant magnetic field of high homogeneity. The measuring station, further, comprises a probe head adapted for letting sample containers be conveyed therethrough and for generating a high frequency magnetic field. A magnetic resonance measuring unit determines the quantitative property of the sample substance contained in the probe head. The probe head excites and detects, resp., the magnetic resonance essentially only within that section of the sample container which contains the sample substance. The probe head comprises a split-ring resonator which, as seen in a conveying direction of the conveyor, has a passage cross-section for letting run the sample containers therethrough.

Abstract: An electrical amplifier comprising an output stage that can be supplied by an electrical energy source, is connected to a control device on the input side, the control signal of the control device controlling an output signal of the output stage dependent on a parameter value of the energy source. The amplifier is has a compensation device that is connected to the energy source and the control device, and is used to modify the control signal according to the parameter value of the energy source which can be, for example, the network voltage of the energy source. A method for controlling an electrical amplifier comprising an output stage supplied by an electrical energy source includes, determining parameter value of the energy source, deriving a compensation signal therefrom, and a control signal for the output stage is generated according to the compensation signal. The amplifier and method can be used in a gradient amplifier for a magnetic resonance appliance.

Abstract: Discriminating between a cable locating signal and a false cable locating signal is described. A reference signal, which contains a locating signal frequency impressed on it, is transmitted in a way which provides for detection of a phase shift between the locating signal and the false locating signal. Based on the phase shift, a receiver is used to distinguish the locating signal from the false locating signal.

Abstract: Phase-sensitive measurements are made by a resistivity imaging tool in a borehole having non-conductive mud in a conductive earth formation at a plurality of frequencies. From the phase sensitive measurements, the formation resistivity can be determined with higher sensitivity than is possible with the single frequency measurements. Tool standoff can also be determined from a knowledge of the mud resistivity and/or dielectric constant. Formation resistivity may also be determined when the effect of formation capacitance cannot be ignored.

Abstract: A device for testing connectivity is provided. The device includes a first connector including a contact pin and a spacer for biasing the contact pin away from a spring contact pin of a second connector, when the first connector is inserted into the second connector. The device also includes an indicator, coupled to the contact pin of the first connector, for indicating whether the contact pin of the first connector is in contact with the spring contact pin of the second connector.

Abstract: A method for accurately measuring feature sizes and quantifying the beam spot size in a CDSEM at real time is provided. The inventive method is based on a scanning microscope and it works on both conductive and non-conductive features. The measurement of conductive feature includes first providing a conductive feature on a surface of a substrate (the substrate maybe an insulator, a semiconductor or a material stack thereof). The conductive feature is then connected to ground and thereafter an electron beam probe raster scans the sample. When the electron beam probe hits the conductive feature the spot will have a negative potential. The potential difference between the spot and the ground will induce an electrical current flow. When the electrical beam is off the conductive feature, there will be no current flow. Therefore, by measuring the current response to the location of the beam spot, the dimension of the conductive feature can be derived.

Abstract: A transmission Line Pulse (TLP) device calibration method wherein the TLP device includes a pulse generator for generating a pulse, a cable having an input terminal coupled to said pulse generator, an output terminal, and at least one ground return terminal, for coupling said pulse to a device under test (DUT) when it is connected to said output terminal, and a sensor for sensing the voltage and current at a selected point in said cable to measure the pulsed voltage and current of the DUT as the pulses travel in the cable to and from the DUT.

Abstract: Methods for determining an electrical parameter of an insulating film are provided. One method includes measuring a surface potential of a leaky insulating film without inducing leakage across the insulating film and determining the electrical parameter from the surface potential. Another method includes applying an electrical field across the insulating film. Leakage across the insulating film caused by the electrical field is negligible. The method also includes measuring a surface potential of the specimen and determining a potential of the substrate. In addition, the method includes determining a pure voltage across the insulating film from the surface potential and the substrate potential. The method further includes determining the electrical parameter from the pure voltage. The electrical parameter may be capacitance or electrical thickness of the insulating film.

Abstract: A micro Kelvin probe assembly and method of accomplishing a micro Kelvin measurement that determines the resistance or impedance of a device under test (DUT) that has two spaced contacts. An ammeter is used to flow current through the DUT, and a voltmeter is used to measure the voltage drop across the DUT. There is a printed circuit board (PCB) carrying two pairs of contacts, with a trace leading to each contact. Anisotropic conductive elastomer (ACE) material as an electrical interposer is placed in electrical contact with each of the PCB contacts. The DUT is placed on the ACE such that each DUT contact is directly opposite one pair of PCB contacts. The ammeter is connected to one trace leading to one contact of each pair of PCB contacts to flow current through the DUT, and the voltmeter is connected to the other trace leading to the other contact of each pair of PCB contacts, so that voltmeter can measure the voltage drop across the DUT without an effect caused by the interposer.

Abstract: A positioning region of external terminals is divided into a plurality of positioning sections, and at least one side or perimeter of a chip is assigned to each positioning section. The external terminals in each positioning section are allocated to the perimeter to which the positioning section is assigned. The external terminals allocated to each perimeter are grouped into groups arranged perpendicularly to the perimeter, and pads of the chip are also grouped. The external terminals of the groups are assigned to the pads of the corresponding groups. The external terminals and the pads assigned to each other are connected by linear virtual wirings. Further, it is checked whether the virtual wirings cross each other. If there are crossing virtual wirings, the correspondences between the external terminals and the pads are replaced with each other.

Abstract: A method for detecting tip positions of probes which is performed prior to the wafer test includes a first step of attaching the transparent film F on the test substrate W having the electrodes P arranged same as those of the wafer; a second step of detecting the electrodes P of the test substrate W by using the first CCD camera 13A; a third step of detecting a surface height of the transparent film F; a fourth step of position-aligning the electrodes P of the test substrate W with the probes 12A. The method further includes a fifth step of forming the probe marks M on the transparent film F by making the probes 12A contact with the transparent film F; and a sixth step of detecting tip positions of the probes 12A based on the electrodes P of the test substrate W and the probe marks M.

Abstract: A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces.

Abstract: A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).

Abstract: A universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.

Abstract: A burn-in system includes a testing stage configured to stress test one an integrated circuit and a power stage having a voltage control mode and a current control mode. The power stage is configured to supply power to the testing stage. One embodiment of the power stage includes a pulse width modulator, a current control circuit and a voltage control circuit. The pulse width modulator is configured to generate a modulated power output that is coupled to the testing stage. The current control circuit is configured to produce a current error output signal that is based on a difference between a measured load current, which is indicative of the current that is supplied to the testing stage by the modulated power output, and target load current.

Abstract: Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.

Abstract: Characteristics of a power MOSFET gate charge test waveform are evaluated to yield a highly reliable and uniform testing methodology that replaces the inconsistent and inefficient dv/dt immunity testing currently performed. The invention utilizes the ratio of QGD over QGS1 to replace traditional dv/dt immunity testing in order to perform binning and sorting the devices. The ratio of QGD over QGS1 has proven to be a very reliable substitute for standard dv/dt immunity tests, and a very accurate predictor of a power MOSFET's suitability for a specified purpose. Because the gate charge parameters are relatively easily measured with high accuracy, and independent of test set-up or tester, reliability is far greater than previous methods and improved efficient results. Additional ratios of charge parameters enhance the performance of the testing methodology of the present invention.

Abstract: A CMOS circuit characteristic automatic adjustment apparatus includes a replica signal generation circuit for generating a replica signal capable of minimizing a drain voltage of an MOS transistor in a target circuit, a replica circuit for receiving the replica signal, voltage buffers for receiving respective drain voltages of MOS transistors in the target circuit and the replica circuit, respectively, MOS transistors for receiving respective output voltages of the voltage buffers, a comparison circuit for comparing respective sizes of currents flowing in the MOS transistors, respectively, and an adjustment circuit for adjusting, based on a comparison result, operation states of the target circuit and the replica circuit.

Abstract: A system and method for testing the electromagnetic (EM) susceptibility of an electronic display unit monitors the light emitted from the electronic display unit as EM noise is applied at a particular testing location of the electronic display unit. An error in the electronic display unit caused by the EM noise is detected using an electrical signal generated in response to the light from the electronic display unit.

Abstract: A power supply voltage detecting circuit includes a voltage regulating circuit, a comparative circuit, a timer circuit, and a display circuit. The voltage regulating circuit provides a stable reference voltage to the comparative circuit. The comparative circuit compares the reference voltage with the voltage from the power supply. The comparative circuit is electrically connected to the display circuit via the timer circuit. The display circuit includes light emitting diodes for revealing a status of the voltage from the power supply. The timer circuit causes the display circuit to keep a light on when there has been an occurrence of abnormal voltage from the power supply until an operator resets it.

Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.

Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series.

Abstract: A system for configuring a plurality of programmable devices may include an external memory, a master programmable device, and at least one slave programmable device. The programmable devices may have a parallel data bus connected in a daisy chain fashion. The programmable devices may further include a chip select signal that is also connected in a daisy chain. Special instructions embedded in the configuration bitstream, which may be stored in the external memory, are used by the programmable devices to control the configuration process.

Abstract: Voltage level translation for open-drain circuitry is described. A logic isolation circuit includes a first buffer circuit configured for being switched between a first voltage transferable state and a first voltage non-transferable state. A first latch circuit is configured for being switched between a first reset state and a first non-reset state, the first reset state for setting the first latch circuit to a first reset condition. A second buffer circuit and second latch circuit are configured like the first buffer circuit and the first latch circuit. First and second input/output nodes are coupled to receive first and second logic level voltages, respectively. The first logic level voltage and the second logic level voltage are both for a same logic state, but the second logic level voltage is significantly greater than the first logic level voltage.

Abstract: In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a SPI interface operable to receive and transmit configuration data for programming the fabric; and circuitry coupled to the JTAG and SPI interfaces. The circuitry is operable, without being configured, to transfer configuration data received at the JTAG interface to the SPI interface for transmission to an external device having a SPI interface, such as a serial flash memory.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices.

Abstract: A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The EXOR logic function of the binary system can be implemented by the control of these metal devices.

Abstract: A P-channel MOS transistor and an N-channel MOS transistor are respectively controlled by a first control signal and a second control signal. The first control signal CTL1 and the second control signal CTL2 are independent from each other. The second control signal CTL2 is generated by a NOR circuit 2 to which a data signal DATA and a third control signal CTL3 are inputted. A load capacitor C1 which samples the first electric potential or the GND electric potential is configured by a gate capacitance of another MOS transistor.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

Abstract: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

Abstract: An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

Abstract: A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.

Abstract: A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal format signal which is received by the multiplexer or demultiplexer. The configurable driver circuit receives the internal format signal from the multiplexer or demultiplexer.

Abstract: A bootstrapping circuit capable of sampling input signals beyond a supply voltage is disclosed. In one embodiment, the bootstrapped circuit is implemented having a reduced area and/or power consumption requirement.

Abstract: A magnetic transistor circuit with the AND, NAND, NOR and OR functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors act as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The AND, NAND, NOR and OR logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A flip-flop circuit capable of inhibiting current consumption as well as the circuit scale from increase is provided. This flip-flop circuit comprises a first latch circuit including first and second inverter circuits. A first power supply line capable of switching a supplied potential between a fixing potential supplied for fixing the potentials of output nodes of the first and second inverter circuits and a floating potential supplied for floating the potentials of the output nodes of the first and second inverter circuits is connected to the first latch circuit.

Abstract: A sample hold circuit includes an op-amp, first capacitors provided on an inverting side of the op-amp and second capacitors provided on a non-inverting side. The sample hold circuit is configured such that a total capacitance of the first and second capacitors to which an input voltage is applied in a sampling phase is equal to that of the first and second capacitors to which the input voltage is applied in a holding phase, a total capacitance of the first capacitors to which the input voltage is applied in the holding phase is equal to that of the second capacitors to which the input voltage is applied in the holding phase, and a total capacitance of the first capacitors to which the input voltage is applied in the sampling phase is different from that of the second capacitors to which the input voltage is applied in the sampling phase.

Abstract: In one embodiment, a fan out buffer has the inputs of a plurality of output followers connected to the output of a plurality of distribution gates.

Abstract: There is provided a skew adjusting apparatus for adjusting a skew between a positive-side differential signal and a negative-side differential signal in differential signals inputted from an outside device via outside transmission lines, having a positive-side transmission line for propagating the positive-side differential signal inputted to an input end, a negative-side transmission line for propagating the negative-side differential signal inputted to an input end, a plurality of differential comparators connected with the positive-side and negative-side transmission paths so that a difference between wiring length from the input end of the positive-side transmission path and wiring length from the input end of the negative-side transmission path is different from each other and that take in the positive-side differential signal and the negative-side differential signal and a selecting section for selecting a signal taken in by the differential comparator by which a skew between the positive-side path from

Abstract: A control voltage for a synchronous rectifying transistor is generated with the desired anticipation time. The anticipation time is continuously controlled with a closed-loop technique by comparing it with the duration of a reference pulse. The resulting error signal is processed and provides the necessary correction to the MOSFET gate signal to equalize the actual anticipation time to the duration of the reference pulse.