Abstract: A storage system comprises a charge storage cell and a controller. The charge storage cell includes first and second charge storage regions, each capable of assuming a plurality of charge levels. The controller programs the first charge storage region to one of the plurality of charge levels and then programs the second charge storage region to one of the plurality of charge levels. The controller reads a charge level stored in the first charge storage region based upon a first measurement of the first charge storage region and a second measurement of the second charge storage region.

Abstract: A flash memory device is disclosed and includes a memory cell array including a plurality of sectors. Each one of the plurality of sectors includes a plurality of strings, and each of the plurality of strings includes a plurality of memory cells series connected between a string select transistor and a ground select transistor. The flash memory device also includes a plurality of string selection lines, wherein each one of the plurality of string selection lines is respectively connected to string select transistors associated the plurality of strings in one of the plurality of sectors.

Abstract: A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.

Abstract: A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.

Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

Abstract: An integrated circuit comprises a resistive memory cell, at least one reference cell, a first device configured to apply a predetermined read voltage to the resistive memory cell and a second device configured to apply the predetermined read voltage to the reference cell. The resistive memory cell can be switched between a highly resistive memory state and at least one lowly resistive memory state. The reference cell comprises a resistance value representing a reference state. The first device generates the read voltage for a first resistance range, the first resistance range comprising the memory states of the resistive memory cell. The second device generates the read voltage for a second resistance range, the second resistance range being smaller in comparison to the first resistance range and comprising the reference state of the reference cell.

Abstract: A semiconductor memory, including a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at intersections between the plurality of word lines and the plurality of bit lines, and a sense amplifier for reading out what is stored in the memory cells, the semiconductor memory including: bit line selection means for selecting a bit line from among the plurality of bit lines; switch means for turning ON/OFF a current of the bit line selected by the bit line selection means; current generation means for generating a threshold current; means for extracting a differential current between the selected bit line current and the threshold current when a value of the selected bit line current is greater than that of the threshold current; voltage conversion means for converting the differential current to a voltage; and determination means for determining a magnitude relationship between the threshold current and the selected bit line current based on an output voltage from the voltage co

Abstract: A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.

Abstract: Systems and methods, including computer software products, can be used to update or modify data stored in a memory. One or more variables are represented with one or more cell values in a memory. Each variable is associated with one or more of the cell values. Multiple states of the one or more variables are defined, and each defined state of the one or more variables includes a current store value for each variable and at least one previous store value for the variable. One or more single cell values influence the current store value and previous store value of at least one variable.

Abstract: A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuit means for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.

Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.

Abstract: A test mode setting method and circuit that reduce the number of signal lines, thereby minimizing the number of wires of a semiconductor memory device. The method includes: sequentially activating a plurality of selection signals; when each selection signal is activated, activating one of a plurality of test mode addresses corresponding to the activated selection signal; when the last one of the selection signals is activated, and one of the test mode addresses corresponding to the last selection signal is activated, activating a test mode corresponding to the activated test mode address.

Abstract: A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is for latching the amplified differential data to generate first latched data having a same phase as the amplified differential data. The second latch is for latching the amplified differential data to generate second latched data having an opposite phase from the amplified differential data. The amplified differential data from outputs of the sense amplifier are applied substantially simultaneously to inputs of the first and second latches.

Abstract: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

Abstract: A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

Abstract: A memory refresh method applicable in a system memory is disclosed. The memory system comprises a plurality of memory ranks. It is to determine whether an access request corresponds to the memory rank, and an idle auto-refresh number of the memory rank is calculated if there is no access request corresponds to the memory rank. The memory rank is switched from an auto-refresh mode to a self-refresh mode when the idle auto-refresh number of the memory rank reaches a predetermined value.

Abstract: A method for sensing an electrical signal includes the steps of: providing an arrangement having a fuse connected in series to an antifuse, the arrangement further having an output tap connected to an intermediate node located between the fuse and the antifuse; programming the fuse and the antifuse; applying a sense signal across the combination of the programmed fuse and the programmed antifuse, and then measuring an output signal at the output tap.

Abstract: An apparatus for reducing leakage currents of an integrated circuit having at least one transistor, wherein the at least one transistor is connected between a supply potential and a first reference potential, the apparatus including a controller for controlling the first reference potential in dependence on the supply potential.

Abstract: In a memory macro which can more largely reduce a leak current of a memory cell in a hold state, a power voltage between a power potential and a reference potential is supplied across power terminals of each CMOS inverter (across source electrodes of loading P channel FETs and source electrodes of driving N channel FETs) forming the memory cell when a word line is on (high level), a hold enable voltage which is lower than the power voltage and equal to or higher than a lower limit voltage for enabling data to be held (voltage between a potential dropped lower than the power potential and the reference potential) is supplied between the power terminals when the word line is turned off (low level), and the power voltage is constantly supplied to a back gate electrode of one FET within each CMOS inverter.

Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Abstract: A semiconductor memory apparatus includes a rising output data generator that generates rising output data from rising data in response to a rising clock and a rising output enable signal. A rising data output buffer buffers the rising output data. A falling output data generator generates falling output data from falling data in response to a falling clock and a falling output enable signal. A falling data output buffer buffers the falling output data.

Abstract: A mixing apparatus for mixing plural kinds of particulate materials by using a falling force, characterized in that the mixing apparatus comprises means for humidifying a space for mixing the particulate materials.

Abstract: An agitation apparatus for agitating a liquid by radiating a sound wave, includes a liquid holder that holds a liquid, and a sound wave generator that is arranged at an outer side of a wall of the liquid holder to make sound waves directed in two mutually plane-symmetrical directions each at an angle with the wall incident on the wall, wherein the sound wave generator generates the sound wave from such a position that a plane of symmetry of the sound wave is displaced from a central axis of the liquid holder.

Abstract: An analyzing apparatus for agitating plural different types of liquids to cause reaction to analyze a reaction liquid, includes a sound wave generator that generates a sound wave to agitate a liquid held in a vessel, a supply unit that supplies, to the vessel holding a first liquid and transported, a second liquid or a solid of an amount smaller than an amount of the first liquid, and a drive controller that controls generation of the sound wave by the sound wave generator so that the first liquid is agitated when the supply unit supplies the second liquid or the solid.

Abstract: A blender jar defines a geometry to impart vertical movement to material being processed in the blender jar, and, alternatively or in combination, improves the horizontal movement to the blended material. By configuring one or more agitators on the floor of a jar, laminar flow or symmetric flow of material around the jar is disrupted. The material is forced in an upward direction in the jar and, therefore, into more frequent contact with the cutter blades rotating in the jar.

Abstract: A system for measuring an acoustic property of material penetrated by a well borehole. The system uses a borehole logging tool comprising preferably one acoustic transmitter and preferably a plurality of acoustic receivers. An independent measurement is used to determine azimuthal orientation of the tool within the borehole. Firings of the transmitter are based upon azimuthal orientation of the tool. Receiver responses resulting from preferably a plurality of transmitter firings per tool revolution are combined to form at least one composite transmitter response. The composite receiver response is compensated for adverse effects of the tool operating eccentered within the borehole.

Abstract: An apparatus for evaluating a tubular in a borehole of includes at least two electromagnetic acoustic transducers. The transducers are configured to generate and receive first and second acoustic waves in the tubular. A difference in velocity of the two acoustic waves is indicative of a stress field in the tubular.

Abstract: This invention relates to a method for processing at least two seismic data sets (10, 20), each data set comprising several seismic traces (i, j) grouped by bins (Bi, Bj) and by offset classes (Oi, Oj), the method including the following steps: calculating at least one attribute (a(i, j)) characteristic of a similarity between a first trace (i) of a first data set (10) and a second trace (j) of a second data set (20), selecting or not the first and second traces (i, j) according to a selection criterion applied to the calculated attribute (a(i, j)).

Abstract: The present invention utilizes signals such as interrogate commands generated from a Master Clock or other High Precision Clocks in a distributed sensor data acquisition system featuring a communications network (such as a land/transition zone seismic data acquisition system) to stabilize the oscillator (timing cycle) frequency of Remote Clocks elsewhere in the network. The disclosed invention is characterized by the utilization of highly stable timing signals from a Master Clock or other High Precision Clocks as a calibration standard to improve the oscillator frequency of distributed Remote Clocks of lesser inherent stability. Implementation of the disclosed invention results in improved synchronization of seismic amplitude data concurrently acquired over a wide area and improved subsurface geologic resolution.

Abstract: This invention provides a method and device to enlarge the scope of ultrasonic measurement. It adopts two-way or more than two-way ultrasonic, and measures the distance in two or more than two directions, especially it can measure the sum distance of two directions directly. Thus the distance value could reach 30 m at one time. Therefore it can enlarge the scope of ultrasonic measuring without changing the performance of ultrasonic transceiver head.

Abstract: A standard non-destructive testing probe (4) may be coupled with a localization system (10) according to the invention so as to determine the position of the apparatus (4) on the surface to be analyzed (1) at any moment. The localization system (10) comprises an ultrasonic emitter (12) and two ultrasonic receivers (14, 16) coupled with means for determining the distance between the emitter (12) and the receivers (14, 16), each of the components being able to be moved freely relative to each other. The coupling between the emitter (12) and the probe (4) allows the position of the latter to be determined by triangulation. A localization and mapping method is also described.

Abstract: A method and system for locating a sound source within a defined area in which the sound data is collected with a plurality of spaced apart microphones. The sound data received by the microphones is processed to form a cross spectral density matrix containing vectors of cross correlations and auto correlations of the sound data. A replica vector matrix containing sound data from at least one test sound at a plurality of predetermined locations within the defined area is then constructed. The sound data vectors in the cross spectral density matrix are then projected on the replica vectors in the replica vector matrix to obtain a probability of the location of the sound source at each predetermined location within the defined area. These probabilities form a distribution within the defined area in which the largest probability distribution correlates with the location of the sound source.

Abstract: A data transmission system connected to a bone implant has an extra-corporeally arranged external transmitting unit an implantable internal first receiving unit adapted to be actuated by the external transmitting unit. An internal transmitting unit is adapted to be coupled and implanted to the implant. A second transmission section is located between the external transmitting unit and the internal first receiving unit, via which the internal transmitting unit is actuated. A second receiving unit and a first transmission section is located between the internal transmitting unit and the second receiving unit. The first transmission section operates with acoustic vibrations or waves.

Abstract: Timepiece component (1) having a grande date display wherein the two discs are actuated independently from one another by stepping motors. The date's tens are displayed differently, for example in another color, in the morning and in the afternoon. It is also possible to combine the date indications with other independent indications.

Abstract: A timing apparatus 10 for monitoring a sports event such as a lacrosse game, comprises a first timer 12 for counting a twenty-second time period and a second timer 14 for counting a one-hundred second time period, an alarm 16 connected to the first and second timers for producing a perceptible warning at the expiration of either of the twenty-second and one-hundred second time periods, and a toggle switch 20 movable between a first position 28 for activating the first timer 12 and a second position 30 for activating the second timer 14.

Abstract: A light emitting device to awaken an animal and stimulate the Suprachiasmatic Nucleus in the brain to suppress melatonin secretion. The device can be programmed for an initiation time, color of light, brightness, frequency of pulsating light, and level of gradual intensity. It has the advantage of being silent and does not to disturb other people sleeping in the same room.

Abstract: A media system for playing content on a media player with an electronic computing device for communication. When song title request information for a song title stored by a storage process is received from a computing device, song titles stored in the storage process are transmitted in a song title transmission process to the computing device, song selection information is received from the computing device, song performance information is read and the performance equipment runs a performance process from that performance information. When the performance equipment and the second communication process are run, the song titles are displayed on the display screen.

Abstract: Congested rewriting in the same area is to be evaded to suppress the tendency towards occurrence of defective areas. When a stream 1 has been recorded, the last written address, representing the last written position, is stored. When recording a stream 2 next, recording is started directly following the position indicated by the last written address for the stream 1. The last written address, corresponding to the last address of the recording position, is stored. If the stream 2 is erased for recording a stream 3, recording is started not at a position directly following the last written address of the stream 1, but from a position directly following the last written address of the stream 2. When the stream 3 has reached the end of a recording area, the next following data is recorded as from a position directly following the stream 1.

Abstract: In an information recording apparatus using a hologram, a signal area of the light flux to be recorded is secured to be as wide as possible and the optical power loss is depressed during reproduction process. For this reason, almost the entire surface of the spatial light modulator is allocated as a signal area and the reference beam is collected on a micro mirror placed on its optical axis.

Abstract: Disclosed is a disc drive apparatus. The disc drive apparatus includes a rotational driving unit rotating a disc-shaped recording medium having a plurality of addresses recorded on an information recording surface of the disc-shaped recording medium; an optical pickup recording and/or reproducing an information signal on the information recording surface of the disc-shaped recording medium rotated by the rotational driving unit; and a control unit controlling rotation of the disc-shaped recording medium via the rotational driving unit. In the disc drive apparatus, the control unit carries out a disc constant velocity rotating processing that sets a predetermined address out of the plurality of addresses as a constant velocity rotation address and continuously reproduces the constant velocity rotation address using the optical pickup.

Abstract: An aberration detection device of the present invention is such that an absolute value of detection sensitivity of an aberration error signal is increased, and variation in detection sensitivity of the aberration error signal is little even when displacement between the center of light beam dividing means and the center of a bundle of light beams occurs due to a shift of a condensing optical system at the time of tracking control. A hologram element (2) divides light beams reflected from an information storage medium into at least two positive first order diffracted light beams. The hologram element (2) has a line (D1) extending in a radial direction and passing through an optical axis (OZ) and a division line (D2) having segments at least both ends thereof and a bulge in a center thereof, wherein the segments are substantially parallel to the line (D1), and the bulge (44) bulges toward the periphery of the hologram element (2) so that a top (D5) of the bulge (44) is substantially parallel to the line (D1).

Abstract: A method for identifying an optical disc's type includes: detecting at least one header's appearance according to a reproduced signal in an optical storage device accessing the optical disc; after the appearance of a first header of the at least one header is detected, detecting whether there is another header's appearance in a window that lags behind the first header's appearance; and determining whether the optical disc is a DVD-RAM disc according to the number of times that there is a header's appearance in a corresponding window.

Abstract: A super resolution optical recording medium for preventing degradation of a reproducing signal, includes a substrate, a super resolution layer formed on the substrate, and having a super resolution aperture formed thereon. The super resolution aperture has a size smaller than a resolution limit of an emitted beam incident on the super resolution layer, and a recording layer disposed on a lower part or an upper part of the super resolution layer. A reaction temperature at which recording of the recording layer is performed, is higher than a super resolution temperature at which the super resolution aperture is formed. Accordingly, the degradation of the reproducing signal can be prevented remarkably improving the number of times information can be reproduced.

Abstract: A reliable optical recording medium is provided which includes an information layer exhibiting small changes in the optical properties even during long-term storage. The optical recording medium includes the information layer including a recording film having an extinction coefficient of 0.4 or less at the wavelength of a laser beam used for recording and reproducing. The information layer further includes a light absorbing film having an extinction coefficient of 1.5 or less at the wavelength of the laser beam, and the extinction coefficient of the light absorbing film is greater than that of the recording film.

Abstract: The optical recording medium includes a first information layer including a first recording film having an extinction coefficient of 0.4 or less at a wavelength of a laser beam used for recording and reproducing, and a second information layer including a second recording film consisting essentially of the same constituent elements as those of the first recording film and having an extinction coefficient of 0.4 or less. Among the first and second information layers, the first information layer is located further away from a laser beam-incident surface than the second information layer located closest to the incident surface. The first information layer further includes a light absorbing film having an extinction coefficient of 1.5 or more at the wavelength of the laser beam, the extinction coefficient of the light absorbing film being greater than that of the first recording film.

Abstract: An optical pickup device is constituted to enable stable recording or reproduction on/from a recording medium.

Abstract: An optical system for use in an optical pickup apparatus comprises a first optical surface having a superposition type diffractive structure including a plurality of ring-shaped zones which are formed concentrically around an optical axis, wherein each ring-shaped zone is composed of a plurality of stepped sections stepwise, and a second optical surface having a diffractive structure including a plurality of ring-shaped zones which are formed concentrically around an optical axis, wherein each of the plurality of ring-shaped zones are divided by a stepped section to generate a diffractive light ray of diffractive order whose absolute value is not small than 1 for the light flux.

Abstract: A method for non-destructive reading of a datum stored in a ferroelectric material in a stable state of polarization, the method including applying a read electrical quantity to the ferroelectric material having a value such as not to cause a variation in the stable state of polarization thereof, generating an output quantity indicative of a polarization charge variation occurring in the ferroelectric material during application of the read electrical quantity, and determining the value of the stored datum based on the output quantity. In particular, the polarization charge variation is given by a difference between a first value assumed by the polarization charge in the stable state of the ferroelectric material and a second value assumed by the polarization charge during application of the read electrical quantity.