Abstract: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT. The TFT includes: a substrate; a polycrystalline silicon (poly-Si) semiconductor layer disposed on the substrate, including source, drain, and channel regions, a crystallization-inducing metal, first gettering sites disposed on opposing edges of the semiconductor layer, and a second gettering site spaced apart from the first gettering sites; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions of the semiconductor layer.

Abstract: A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.

Abstract: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.

Abstract: Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO2 surface of a Si carrier substrate to the Si layer, and removing the Si growth substrate to expose the SiC layer. In yet another aspect, a semiconductor layer may be deposited onto the SiC layer. The semiconductor layer may further be deposited epitaxially.

Abstract: This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C.

Abstract: A method of manufacturing a semiconductor device based on a SiC substrate (12), comprising the steps of forming (201) an oxide layer (14) on a Si-terminated face of the SiC substrate (12) at an oxidation rate sufficiently high to achieve a near interface trap density below 5×1011 cm?2; and annealing (202) the oxidized SiC substrate in a hydrogen-containing environment, in order to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET (10) having improved inversion layer mobility and reduced threshold voltage. It has been found by the present inventors that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. According to the present invention, the deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.

Abstract: A SiC semiconductor device includes: a substrate; a drift layer on a first side of the substrate; a trench in the drift layer; a base region contacting a sidewall of the trench; a source region in an upper portion of the base region; a gate electrode in the trench via a gate insulation film; a source electrode on the source region; and a drain electrode on a second side of the substrate. The source region has multi-layered structure including a first layer and a second layer. The first layer as an upper layer contacts the source electrode with ohmic contact. The second layer as a lower layer has an impurity concentration, which is lower than an impurity concentration of the first layer.

Abstract: The invention provides a substrate for fabricating a light emitting device and the light emitting device fabricated therefrom. The substrate includes at least one platform region having a first facet direction for epitaxial growth; and a plurality of continuous protruded portions surrounding the at least one platform region to isolate the at least one platform region from another platform region, wherein the first facet direction is substantially excluded from facet directions of the plurality of continuous protruded portions. Since facet directions of the plurality of continuous protruded portions substantially do not include the first facet direction, during formation of the light emitting device, epitaxial growth is mainly conducted on the at least one platform region, which may prevent epitaxial defects from generating and enhance external quantum efficiency of the light emitting device.

Abstract: A metal pattern for a high frequency signal is patterned on a flexile substrate, and the flexile substrate is bent in such a way as to form a substantially right angle at a spot corresponding to an end of the metal pattern for the signal. And an end of the metal pattern is fixedly attached to a lead pin for signaling, attached to a stem, for electrical continuity, so as to be in a posture horizontal with each other. Meanwhile, a part of the lead pins attached to the stem, being in such a state as penetrated through respective holes provided in the flexible substrate, is fixedly attached to a part of metal patterns provided on the flexible substrate so as to ensure electrical continuity therebetween.

Abstract: A sapphire growth substrate wafer has epitaxially grown over it N-type layers, an active layer, and P-type layers to form GaN LEDs. Each LED is a flip-chip with its cathode contact and anode contact formed on the same side. The wafer is then diced to separate out the LEDs. A P-type silicon submount wafer has N-type doped interconnect regions for interconnecting all the cathode contacts together after the LEDs are mounted on the submount wafer. The sapphire substrate is then removed by a laser lift-off process. A bias voltage is then applied to the cathode contacts via the interconnect regions to bias the N-type layers for a photo-electrochemical etching process that roughens the exposed layer for increased light extraction. The submount wafer is then diced, cutting through the doped interconnect regions.

Abstract: In order to collect a plurality of semiconductor elements easily from a semiconductor module where a plurality of rod-like semiconductor elements for power generation or light emission are built in and to reuse or repair them, two split modules 61 are arranged in series in a containing case 62 in a semiconductor module 60. In each split module 61, power generating semiconductor elements 1 arranged in a matrix of a plurality of rows and columns, and a conductive connection mechanism for connecting the plurality of semiconductor elements 1 in each row in series and the plurality of semiconductor elements 1 in each column in parallel are molded with transparent synthetic resin, and a connection conductor 67 is allowed to project at the end. A conductive waved spring 70 and an external terminal 76 are provided on the end side of the containing case 62, and series connection of the two split modules 61 is ensured by mechanical pressing force of the conductive waved spring 70.

Abstract: It is a problem to provide a light-emitting device capable of obtaining a constant brightness without being affected by deterioration in an organic light-emitting layer or temperature change, and of making desired color display. The lowering in OLED brightness due to deterioration is reduced by causing the OLED to emit light while keeping constant the current flowing through the OLED instead of causing the OLED to emit light while keeping constant the OLED drive voltage. Namely, OLED brightness is controlled not by voltage but by current thereby preventing against the change in OLED brightness due to deterioration of OLED. Specifically, the drain current Id of a transistor for supplying a current to the OLED is controlled in a signal line drive circuit thereby keeping constant the drain current Id without relying upon the value of a load resistance.

Abstract: There is provided a light emitting diode operating under AC power comprising a substrate; a buffer layer formed on the substrate; and a plurality of light emitting cells formed on the buffer layer to have different sizes and to be electrically isolated from one another, the plurality of light emitting cells being connected in series through metal wires. According to the present invention, light emitting cells formed in an LED have different sizes, and thus have different turn-on voltages when light is emitted under AC power, so that times when the respective light emitting cells start emitting light are different to thereby effectively reduce a flicker phenomenon.

Abstract: An AC LED device and method for fabricating the same are disclosed. An exemplary embodiment of the AC LED device includes at least two separate AC LED unit chips, wherein each of the AC LED unit chip includes a substrate having a first light emitting module and a second light emitting module. Each of the first and second light emitting modules includes a plurality of light emitting micro diodes connected between a first conductive electrode and a second conductive electrode, wherein the amount of light emitting micro diodes emitting light during a positive half cycle of an AC charge is equal to that during a negative half cycle of an AC charge. A plurality of conductive wires is respectively and electrically connected to the separate AC LED unit chips without passive devices.

Abstract: A semiconductor chip can include a semiconductor substrate, an input portion and an output portion. A circuit element can be formed in the semiconductor substrate. The input portion can be formed on the semiconductor substrate. The input portion can include a first input pad to receive an input signal from the outside and a second input pad spaced apart from the first input pad, the second input pad being electrically connected to the first input pad through an external connection line such that the second input pad inputs the input signal to the circuit element. The output portion can be formed on the semiconductor substrate. The output pad can include an output pad to output an output signal from the circuit element.

Abstract: The present invention relates to a light emitting device. According to the present invention, the light emitting device comprises a substrate, a plurality of light emitting cells disposed on the substrate, a first insulation layer disposed on each light emitting cell, an electrically conductive material disposed on the first insulation layer to couple two of the light emitting cells, and a second insulation layer disposed on the electrically conductive material. Each light emitting cell comprises a first semiconductor layer, a second semiconductor layer, and an inclined surface. The second insulation layer corresponds to a contour of each light emitting cell.

Abstract: A light emitting device that has a radiant efficiency that does not decline in use, enables luminous flux to be increased by a high electric current, and produces white light with good color rendering and a method for producing a light emitting device capable of smoothly transmitting heat generated by LED elements to a carrier substrate. The radiation emitting device has first LED elements for emitting UV radiation, second LED elements for emitting visible light, a substrate made of an inorganic material and which carries the first LED elements and the second LED elements, a body made of inorganic material containing the first LED elements, the second LED elements and the substrate, and an SiC fluorescent screen that is doped with at least one of B and Al as well as N and emits visible light when excited by radiation emitted from the first LED elements.

Abstract: Light-emitting elements have a problem that their light-extraction efficiency is low due to scattered light or reflected light inside the light-emitting elements. The light-extraction efficiency of the light-emitting elements needs to be enhanced by a new method. According to the present invention, a light-emitting element includes a first layer generating holes, a second layer including a light-emitting layer for each emission color and a third layer generating electrons between an anode and a cathode, and the thickness of the first layer is different depending on each layer including the light-emitting layer for each emission color. A layer in which an organic compound and a metal oxide are mixed is used as the first layer, and thus, the driving voltage is not increased even when the thickness is increased, which is preferable.

Abstract: A packaged light emitting device. The device has a substrate member comprising a surface region. The device also has two or more light emitting diode devices overlying the surface region. Each of the light emitting diode device is fabricated on a semipolar or nonpolar GaN containing substrate. The two or more light emitting diode devices are fabricated on the semipolar or nonpolar GaN containing substrate emits substantially polarized emission.

Abstract: In the process for production of a gallium nitride-based compound semiconductor light emitting device, when an n-type semiconductor layer, a light emitting layer obtained by alternately stacking an n-type dopant-containing barrier layer and a well layer, and a p-type semiconductor layer, composed of gallium nitride-based compound semiconductors, are grown in that order on a substrate, the ratio of the supply rates of n-type dopant and Group III element during growth of the barrier layer (M/III) is controlled to a range of 4.5×10?7?(M/III)<2.0×10?6 in terms of the number of atoms.

Abstract: The present invention discloses a white light-emitting diode based on In—Ga—N nitride heterojunction is characterized by that the light-emitting diode has primary blue light emission of a specific wavelength and a light conversion layer so as to generate white light. Further, the present invention also discloses a light conversion layer and its fluorine oxygen garnet phosphor powder.

Abstract: A nitride semiconductor light emitting device includes: a substrate for growing nitride semiconductor of a hexagonal crystal structure; a first nitride semiconductor layer of a first conductivity type formed above the substrate; an active layer formed on the first nitride semiconductor layer for emitting light when current flows; a second nitride semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the active layer; texture formed above at least a partial area of the second nitride semiconductor layer and having a plurality of protrusions of a pyramid shape, each of the protrusions including a lower layer made of nitride semiconductor doped with impurities of the second conductivity type and an upper layer made of nitride semiconductor not intentionally doped with impurities; and a transparent electrode covering surfaces of the second nitride semiconductor layer and the texture.

Abstract: An LED package including a carrier, a LED chip, and a lens is provided. The LED chip is disposed on the carrier. The lens is disposed on the carrier and above the LED chip. A gap is formed between the LED chip and the lens. The lens has a first surface, a second surface, a protrusion, and at least one protruding ring. The first surface faces the LED chip. The second surface is opposite to the first surface. The protrusion is located at the first surface. The protruding ring is located at the first surface and surrounds the protrusion.

Abstract: There is provided a semiconductor light emitting device having a patterned substrate and a manufacturing method of the same. The semiconductor light emitting device includes a substrate; a first conductivity type nitride semiconductor layer, an active layer and a second conductivity type nitride semiconductor layer sequentially formed on the substrate, wherein the substrate is provided on a surface thereof with a pattern having a plurality of convex portions, wherein out of the plurality of convex portions of the pattern, a distance between a first convex portion and an adjacent one of the convex portions is different from a distance between a second convex portion and an adjacent one of the convex portions.

Abstract: A radiation emitting device includes a radiation emitting functional layer that emits a primary radiation, and a radiation conversion material that is arranged in the radiation path of the radiation emitting functional layer and converts the primary radiation at least partially into a radiation of greater wavelength.

Abstract: An LED chip package structure using sedimentation includes a package body, at least two conductive substrates, at least one light-emitting element, and a package unit. The package body has a receiving space. The two conductive substrates are received in the receiving space. The light-emitting element is received in the receiving space and electrically connected to the two conductive substrates. The package unit has a package colloid layer and a powder mixed into the package colloid layer, and the package unit is filled into the receiving space. The powder is uniformly deposited in the receiving space by maintaining the package unit at room temperature firstly and the powder is solidified in the receiving space by heating to a predetermined temperature.

Abstract: There is provided a light emitting device, which comprises compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a metal reflection layer formed on a region of the second conductive semiconductor layer; an insulating structure formed at least in a boundary region of the second conductive semiconductor layer; a metal material structure formed to cover the second conductive semiconductor layer having the metal reflection layer and the insulating structure formed; and a substrate bonded to the metal material structure, wherein the boundary region of the second conductive semiconductor layer includes an outer region of the second conductive semiconductor layer along an outer circumference of the second conductive semiconductor layer.

Abstract: An object of the invention is to provide a lighting device which can suppress luminance nonuniformity in a light emitting region when the lighting device has large area. A layer including a light emitting material is formed between a first electrode and a second electrode, and a third electrode is formed to connect to the first electrode through an opening formed in the second electrode and the layer including a light emitting material. An effect of voltage drop due to relatively high resistivity of the first electrode can be reduced by electrically connecting the third electrode to the first electrode through the opening.

Abstract: Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

Abstract: The application relates to a structure of a light emitting device and the manufacturing method thereof. The application discloses a method of forming a bonding pad of the light emitting device by chemical deposition method. The light emitting device includes a substrate, a semiconductor stack deposited on the substrate wherein the semiconductor stack includes at least a p-type semiconductor layer, an n-type semiconductor layer, and an active layer disposed between the p-type semiconductor layer and the n-type semiconductor layer. A bonding pad is formed on at least one of the p-type semiconductor layer and the n-type semiconductor layer wherein the bonding pad includes a seed layer formed by physical deposition method, and a chemically-deposited layer formed by chemical deposition method. The thickness of the seed layer is smaller than that of the chemically-deposited layer.

Abstract: A light emitting diode includes an n-GaN layer on a substrate, an active layer exposing a part of the n-GaN layer, a p-GaN layer on the active layer, a cathode contacting the exposed n-GaN layer and extending from one side of the active layer toward the other side, and an anode formed on the p-GaN layer and including a plurality of sub-electrodes spaced apart from both sides of the cathode and an edge of the active layer at the same distance.

Abstract: A high power LED (light-emitting diode) chip package carrier structure is disclosed and comprises a circuit board, a metal plate and a lid. The circuit board has a perforate groove for positioning a chip, and an electrode contact area formed at two sides or border of the perforate groove. The metal plate is positioned beneath the circuit board. The lid is positioned above the circuit board, and has a through groove with a width larger than the width of the perforate groove of the circuit board such that the electrode contact area can be exposed out in the through groove of the lid. Thus, the manufacturing process can be simplified and helpful to the mass production.

Abstract: A resin composition for sealing a light-emitting device of the present invention includes a silsesquioxane resin including two or more oxetanyl groups, an aliphatic hydrocarbon including one or more epoxy groups and a cationic polymerization initiator. Furthermore, a lamp of the present invention includes a package equipped with a cup-shaped sealing member, an electrode exposed in the bottom portion of the sealing member, and a light-emitting device arranged on the bottom portion and electrically connected with the electrode, wherein the light-emitting device is sealed with the above-described resin composition for sealing a light-emitting device filled in the sealing member.

Abstract: Provided is a method of manufacturing an optical semiconductor device, the method including: providing a resin layer on a light-emitting substrate to cover a principle surface of the light-emitting substrate, the light-emitting substrate including a pair of electrodes in each section of the principle surface, the resin layer including multiple holes each exposing two of the electrodes located adjacent to each other but in the different sections; providing post electrodes respectively on all the paired electrodes formed in all the sections by filling a conductive material in the holes of the resin layer on the principal surface; and forming multiple optical semiconductor devices by cutting the light-emitting substrate into sections, the light-emitting substrate provided with the post electrodes respectively on all the paired electrodes formed in all the sections.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.

Abstract: An ESD protection circuit including an SCR having at least one PNP transistor and at least one NPN transistor such that at least one of the PNP transistor and the NPN transistor having an additional second collector. The circuit further including at least one control circuit coupled to the at least one second collector to control holding voltage of the SCR.

Abstract: A semiconductor thyristor device includes a semiconductor substrate, two transistors each of which is different junction type from the other and which are provided adjacent to each other in the semiconductor substrate to constitute one thyristor element, a first wiring layer that is formed on the semiconductor substrate and provides a ground potential to one of the transistors, and a second wiring layer that is formed on the semiconductor substrate and provides a power source potential to the other of the transistors. The first wiring layer covers a region in the semiconductor substrate in which the two transistors adjoin each other. This avoids a leakage current that might be generated due to any potential of a wiring layer for another circuit in a chip layout.

Abstract: A near-field terahertz wave detector comprises a semiconductor chip (12) whose longitudinal electrical resistance along its surface changes due to a near-field wave of a terahertz wave (1), an insulating film (18) which covers the surface of the semiconductor chip, and a conductive film (20) able to shield the terahertz wave by covering the surface of the insulating film. The conductive film (20) has an aperture (21) whose maximum size is one digit or more smaller than the wavelength of the terahertz wave. Further, a planar conductive probe (14) is provided between the conductive film (20) and the semiconductor chip (12). The conductive probe (14) is insulated from the conductive film (20) by the insulating film (18), and a tip (14a) of the conductive probe (14) is located inside the aperture (21).

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer.

Abstract: A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction.

Abstract: A semiconductor integrated circuit has: a substrate; a basic logic cell placed on the substrate and configured to function as a part of a logic circuit; and a dummy cell placed on the substrate and not configured to function as a part of a logic circuit. The basic logic cell includes a diffusion layer formed in the substrate, and a distance from the diffusion layer to a boundary between the basic logic cell and another cell adjacent to the basic logic cell is equal to a first distance. The dummy cell includes a dummy diffusion layer that is a diffusion layer formed in the substrate, and a distance from the dummy diffusion layer to a boundary between the dummy cell and another cell adjacent to the dummy cell is equal to the first distance.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The plurality of diffusion regions are separated from each other by one or more non-active regions of the substrate portion. The plurality of diffusion regions are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The number of conductive features within the gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction across the gate electrode level region.

Abstract: A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The conductive features within the gate electrode level region are defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction and fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction. Within a five wavelength photolithographic interaction radius within the gate electrode level region, the width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features.

Abstract: A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.