Abstract: An object of this invention is to provide a top-emission type organic EL display in which filling defects of a resin filler material are alleviated during bonding of an organic EL emission panel and a color conversion filter panel with the resin filler material, as well as to provide a method for manufacturing such an organic EL display. An organic EL display of this invention is characterized in having stripe-shaped barrier walls for inkjet application placed on a color conversion filter panel, and a filler material guide wall placed between the length-direction end portions of the barrier walls for inkjet application and a peripheral seal member.

Abstract: An organic light emitting diode display includes a substrate main body, a plurality of organic light emitting diodes formed on the substrate main body, and a differential capping layer covering the plurality of organic light emitting diodes, the differential capping layer having a plurality of thicknesses. The differential capping layer has first regions with a thickness of 90 nm to 120 nm, and second regions with a thickness smaller than the thickness of the first regions.

Abstract: Arrays of light-emitting devices, and related components, processes, systems and methods are disclosed.

Abstract: A ceramic body is disposed in a path of light emitted by a light source. The light source may include a semiconductor structure comprising a light emitting region disposed between an n-type region and a p-type region. The ceramic body includes a plurality of first grains configured to absorb light emitted by the light source and emit light of a different wavelength, and a plurality of second grains. For example, the first grains may be grains of luminescent material and the second grains may be grains of a luminescent material host matrix without activating dopant.

Abstract: An LED chip and method of fabricating the same is disclosed that comprises a plurality of sub-LEDs, said sub-LEDs interconnected such that the voltage necessary to drive said sub-LEDs is dependent on the number of said interconnected sub-LEDs and the junction voltage of said sub-LEDs. Each of said interconnected sub-LEDs comprising an n-type semiconductor layer, a p-type semiconductor layer, and an active or quantum well region interposed between the n-type and p-type layers. The monolithic LED chip further comprising a p-electrode having a lead that is accessible from a point on a surface opposite of a primary emission surface of the monolithic LED chip, the p-electrode electrically connected to the p-type layer, and an n-electrode having a lead that is accessible from a point on the surface opposite of the primary emission surface, the n-electrode electrically connected to the n-type layer.

Abstract: A light emitting device includes a light emitting element, a base, and a transparent layer. The base has an upper side portion including a first portion and a second portion. The first portion includes a mounting region of the light emitting element, and has a first porosity. The second portion surrounds the first portion, includes a plurality of transparent particles, and has a second porosity larger than the first porosity. The light transmitting layer encapsulates the light emitting element, and is attached to the first portion in a state where the transparent layer is apart from the second portion.

Abstract: A light emitting diode manufacturing method introduces a transparent enclosure to improve the uniformity of coating phosphor, so as to achieve the purposes of enhancing the uniform color temperature and the light emitting efficiency. The manufacturing method is used extensively for packaging various types of light emitting diode chips and mass production.

Abstract: A molded resin product or the like that is provided with a phosphor layer made of gel-like or rubber-like resin that can maintain its shape for a long period and that can be implemented easily. The molded resin product (phosphor layer 7) includes a resin member 17 made of a gel-like or rubber-like translucent resin including a phosphor material. The resin member 17 includes a shape maintaining member 19 that is formed in a lattice shape by line-like members 20 that are made of a material having a higher elasticity modulus than the resin member 17. The molded resin product (phosphor layer 7) is in the shape of a dome. The translucent resin is made of for example, silicon resin, and the resin member 17 is gel-like.

Abstract: A light emitting diode comprises a heat conductive layer, a semiconductor layer disposed above the heat conductive substrate and consisting of a p-type semiconductor layer, an active layer and an n-type semiconductor layer, a transparent electrode layer, a current blocking layer and an electrode contact pad. The p-type semiconductor layer has first concaves located on its surface distant from the active layer. The n-type semiconductor layer has second concaves located on its surface distant from the active layer. The transparent electrode layer is located on the surface of the n-type semiconductor layer except the second concaves. The current blocking layer is located in the first concaves of the p-type semiconductor layer. The electrode contact pad is located on the surface of the transparent electrode layer. The density of the second concaves decrease with distance from the electrode contact pad.

Abstract: An LED light source can include protection members to protect bonding wires. The LED can include a substrate including electrode patterns, a sub mount substrate located on the substrate, at least one flip LED chip mounted on the sub mount substrate and a phosphor rein covering the LED chip. The bonding wires can connect each of the electrode patterns to conductor patterns connecting to electrodes of the LED chip. The protection members can be located so as to surround both sides of the bonding wires. In addition, because each height of the protection members is higher than each maximum height of the bonding wires and is lower than a height of the phosphor resin, the protection members can protect the bonding wires from external pressure while the light flux is not reduced. Thus, the disclosed subject matter can provide a reliable LED light source having a favorable light distribution.

Abstract: Provided is a light emitting diode device. The light emitting diode device includes a light emitting diode chip having a first surface on which first and second electrodes are disposed, and a second surface opposing the first surface, a wavelength conversion portion including fluorescent substances and covering the first surface and side surfaces of the light emitting diode chip, wherein the side surfaces denote surfaces placed between the first and second surfaces, and first and second electricity connection portions each including a plating layer, respectively connected to the first and second electrodes, and exposed to the outside of the wavelength conversion portion. Accordingly, the light emitting diode device, capable of enhancing luminous efficiency and realizing uniform product characteristics in terms of the emission of white light, is provided. Further, a process for easily and efficiently manufacturing the above light emitting diode device is provided.

Abstract: LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features.

Abstract: A method for the manufacture of a wavelength converted light emitting device is provided. A light curable coating material is arranged on the outer surface of a wavelength converted light emitting diode. The light curable coating material is cured, in positions where a high intensity of unconverted LED-light encounters the curable coating material. The method can be used to selectively stop unconverted light from exiting the device, leading to a wavelength converted LED essentially only emitting converted light.

Abstract: The present invention relates to the heat-radiation structure of a pin-type power Light Emitting Diode (LED). The heat-radiation structure includes an LED device, first and second lead frames, a mold unit, and a heat sink. The first lead frame is electrically connected to the LED device, and extended forward to the outside in order to supply power to the LED device. The second lead frame is provided to face the first lead frame, and extended forward to the outside. The mold unit includes the LED device, and molds the upper portions of the first and second lead frames out transparent material. The heat sink is provided at a bottom of the mold unit so that the lead frames penetrate therethrough, fixed into any of the two lead frames, and configured to receive heat from the lead frame which comes into contact therewith and to radiate the heat to the outside.

Abstract: An embodiment of present invention discloses a light-emitting device comprising a first multi-layer structure comprising a first lower layer; a first upper layer; and a first active layer able to emit light under a bias voltage and positioned between the first lower layer and the first upper layer; a second thick layer neighboring the first multi-layer structure; a second connection layer associated with the second thick layer; a connective line electrically connected to the second connection layer and the first multi-layer structure; a substrate; and two or more ohmic contact electrodes between the first multi-layer structure and the substrate.

Abstract: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 ?m; and an n-electrode pad formed on the n-type nitride semiconductor layer.

Abstract: A semiconductor light emitting device and corresponding method of manufacture, where the semiconductor light emitting device includes a light emitting structure, a second electrode layer, an insulating layer, and a protrusion. The light emitting structure comprises a second conductive semiconductor layer, an active layer under the second conductive semiconductor layer, and a first conductive semiconductor layer under the active layer. The second electrode layer is formed on the light emitting structure. The insulating layer is formed along the circumference of the top surface of the light emitting structure. The protrusion protrudes from the undersurface of the insulating layer to the upper part of the first conductive semiconductor layer.

Abstract: One object of the present invention is to provide a method for producing a group III nitride semiconductor light-emitting device which has excellent productivity and produce a group III nitride semiconductor light-emitting device and a lamp, a method for producing a group III nitride semiconductor light-emitting device, in which a buffer layer (12) made of a group III nitride is laminated on a substrate (11), an n-type semiconductor layer (14) comprising a base layer (14a), a light-emitting layer (15), and a p-type semiconductor layer (16) are laminated on the buffer layer (12) in this order, comprising: a pretreatment step in which the substrate (11) is treated with plasma; a buffer layer formation step in which the buffer layer (12) having a composition represented by AlxGa1-xN (0?x<1) is formed on the pretreated substrate (11) by activating with plasma and reacting at least a metal gallium raw material and a gas containing a group V element; and a base layer formation step in which the base layer (14a)

Abstract: A method for manufacturing a semiconductor arrangement is disclosed. The method comprises forming at least one trench in a dielectric layer, thereby exposing a portion of a semiconductor substrate, forming a silicon-germanium buffer layer at least on the bottom of the at least one trench, forming a germanium seed layer on the silicon-germanium buffer layer and forming a germanium layer on the germanium seed layer. A semiconductor arrangement is also disclosed. The semiconductor arrangement comprises a semiconductor substrate, a dielectric layer disposed above the semiconductor substrate, at least one trench in the dielectric layer exposing a portion of the semiconductor substrate, a silicon-germanium buffer layer disposed above at least the bottom of the at least one trench, a germanium seed layer disposed above the silicon-germanium buffer layer and a germanium layer disposed above the germanium seed layer.

Abstract: A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels Et in as function of energy from the band edges of the adjacent layer (the semiconductor P-channel layer or optionally the capping layer) toward the center of the bandgap of this layer. The method includes selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels deviates from the energy level at the center of the bandgap of a layer adjacent the gate dielectric layer at the same side of the gate dielectric layer as the P-channel layer, with a value not more than about 49%, such as not more than about 40%, for example not more than about 20%, not more than about 10%, even not more than about 5% of that bandgap in eV. In one aspect, this allows reducing NBTI.

Abstract: A method of manufacture of a optical, photonic or optoelectronic component, including a so-called photonic slab or membrane that is traversed, in at least one internal region and according to a predetermined pattern, by a plurality of through openings having a micrometric or sub-micrometric transverse dimension, the method having the following steps: structuring of the surface of a substrate by an etching that produces holes in the substrate according to the pattern; depositing at least one layer of the photonic material forming the slab or membrane, by anisotropic epitaxial growth on the structured surface of the substrate around the opening of the holes.

Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.

Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Abstract: One inventive aspect relates to a method for forming integrated circuits and circuits obtained therewith. The method of forming a circuit pattern in a device layer of a semiconductor substrate comprises decomposing the circuit pattern in two constituent orthogonal subpatterns. The method further comprises transferring the pattern of a first subpattern to a hard mask layer overlying the device layer. The method further comprises transferring the pattern of the other subpattern to a photosensitive layer overlying the patterned hard mask layer. The method further comprises patterning the device layer using the patterned hard mask layer and the patterned photosensitive layer as a mask. The method further comprises removing the patterned hard mask layer and the patterned photosensitive layer. Furthermore memory or logic circuits obtained using the above technique are described.

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

Abstract: A pickup device according to the present invention includes a photoelectric conversion portion, a charge holding portion configured to include a first semiconductor region, and a transfer portion configured to include a transfer gate electrode that controls a potential between the charge holding portion and a sense node. A second semiconductor region is disposed on a surface of a semiconductor region between the control electrode and the transfer gate electrode. A third semiconductor region is disposed below the second semiconductor region. An impurity concentration of the third semiconductor region is higher than the impurity concentration of the first semiconductor region.

Abstract: A back-illuminated type solid-state imaging device including (a) a semiconductor layer on a front surface side of a semiconductor substrate with an insulation film between them; (b) a photoelectric conversion element that constitutes a pixel in the semiconductor substrate; (c) at least part of transistors that constitute the pixel in the semiconductor film; and (d) a rear surface electrode to which a voltage is applied on the rear surface side of the semiconductor substrate, wherein, (1) a semiconductor layer of an opposite conduction type to a charge accumulation portion of the photoelectric conversion element is formed in the semiconductor substrate under the insulation film, and (2) the same voltage as the voltage applied to the rear surface electrode is applied to the semiconductor layer.

Abstract: A junction field effect transistor semiconductor device and method can include a top gate interposed between a source region and a drain region, and which can extend across an entire surface of the channel region from the source region to the drain region. Top gate doping can be configured such that the top gate can remain depleted throughout operation of the device. An embodiment of a device so configured can be used in precision, high-voltage applications.

Abstract: A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.

Abstract: Disclosed is a CMOS image sensor and a manufacturing method thereof. According to an aspect of the present invention, each pixel of CMOS image sensor includes a photo detector that includes an electon Collection layer doped with a concentration of 5×1015/cm3 to 2×1016/cm3; and a transfer transistor that is connected to the photo detector and is formed of a vertical type trench gate of which the equivalent oxide thickness is 120 ? or more.

Abstract: A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.

Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.

Abstract: An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization.

Abstract: A method of forming a film of lanthanide oxide nanoparticles. In one embodiment of the present invention, the method includes the steps of: (a) providing a first substrate with a conducting surface and a second substrate that is positioned apart from the first substrate, (b) applying a voltage between the first substrate and the second substrate, (c) immersing the first substrate and the second substrate in a solution that comprises a plurality of lanthanide oxide nanoparticles suspended in a non-polar solvent or apolar solvent for a first duration of time effective to form a film of lanthanide oxide nanoparticles on the conducting surface of the first substrate, and (d) after the immersing step, removing the first substrate from the solution and exposing the first substrate to air while maintaining the applied voltage for a second duration of time to dry the film of lanthanide oxide nanoparticles formed on the conducting surface of the first substrate.

Abstract: A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate.

Abstract: A method for making a non-volatile memory device provides a semiconductor substrate including a surface region and a tunnel dielectric layer overlying the surface region. Preferably the tunnel dielectric layer is a high-K dielectric, characterized by a dielectric constant higher than 3.9. The method forms a source region within a first portion and a drain region within a second portion of the semiconductor substrate. The method includes forming a first and second nanocrystalline silicon structures overlying the first and second portions between the source region and the drain region to form a first and second floating gate structures while maintaining a separation between the first and second nanocrystalline silicon structures. The method includes forming a second dielectric layer overlying the first and second floating gate structures. The method also includes forming a control gate structure overlying the first and second floating gate structures.

Abstract: A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The non-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.

Abstract: A trench MOS device includes a base semiconductor substrate, an epitaxial layer grown on the base semiconductor substrate, a first trench in the epitaxial layer, and a stepped trench comprising a second trench and a third trench in the epitaxial layer. There is a mesa between the first trench and the stepped trench. There is a spacer on a the sidewall of the second trench, wherein the third trench having a depth below the spacer. There is a dielectric layer extending along sidewalls and bottom walls of the second trench and the third trench. There is also a metal layer extending over the first trench, over a sidewall of the stepped trench and a portion of the bottom of the stepped trench.

Abstract: Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material.

Abstract: A bilateral conduction semiconductor device and a manufacturing method thereof are provided. The bilateral conduction semiconductor device includes an epitaxial layer having a first conductive type and a first trench, a first gate conductive layer disposed on a sidewall of the first trench, a second gate conductive layer disposed opposite to the first gate conductive layer, and a doped region having the first conductive type. The doped region is disposed in the epitaxial layer between the first gate conductive layer and the second gate conductive layer, and a doped concentration of the doped region is larger than a doped concentration of the epitaxial layer.

Abstract: A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract: As for a semiconductor device which is typified by a display device, it is an object to provide a highly reliable semiconductor device to which a large-sized or high-definition screen is applicable and which has high display quality and operates stably. By using a conductive layer including Cu as a long lead wiring, an increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.

Abstract: A semiconductor device comprises at least one switching element. The at least one switching element comprises a first channel terminal, a second channel terminal and a switching terminal, the switching element being arranged such that an impedance of the switching element between the first and second channel terminals is dependant upon a voltage across the switching terminal and the first channel terminal. The semiconductor device further comprises a resistance element operably coupled between the first channel terminal of the at least one switching element and a reference node, and a clamping structure operably coupled between the switching terminal of the switching element and the reference node.