Patents Issued in December 1, 2011
-
Publication number: 20110291141Abstract: The present invention is directed to the provision of a semiconductor light-emitting element that has an electrode formed with a desired thickness using a plated metal layer. A semiconductor light-emitting element for flip-chip mounting on a circuit substrate includes a semiconductor layer including a light-emitting layer, an N-side bump electrode for connecting the semiconductor layer to the circuit substrate, and a P-type bump electrode for connecting the semiconductor layer to the circuit substrate, wherein the N-side bump electrode and the P-type bump electrode each include an under-bump metal layer and a plated metal layer, the under-bump metal layer includes a high-reflectivity metal layer disposed on a side that faces the semiconductor layer and a metal layer disposed on a side opposite from the semiconductor layer, and the plated metal layer has a thickness not less than 3 ?m but not greater than 30 ?m.Type: ApplicationFiled: May 27, 2011Publication date: December 1, 2011Inventor: Kazuaki SORIMACHI
-
Publication number: 20110291142Abstract: The present invention relates to an oxynitride phosphor, a method for preparing the same, and a light-emitting device. More specifically, the present invention provides the oxynitride phosphor including crystals represented by the following Chemical Formula, a method for preparing the same, and a light-emitting device including the oxynitride phosphor. The invention includes the crystals' represented by the following Chemical Formula to obtain high light-emitting efficiency. [Chemical Formula] (A(1-p-q)BpCq)aDbSicOdNe:xEu2+, yRe3+, Zq) wherein A, B, and C are +2 metals, but different metals from one another; D is metals of Group 3; Re is +3 metals; Q is a flux; p and q are 0<p<1.0 and 0?q<1.0; a, b, c, d, and e are 1.0?a?2.0, 0?b?4.0, 0<c?1.0, 0<d?1.0, and 0<e?2.0; x, y, and z are 0<x?0.25, 0?y?0.25, and 0?z?0.25.Type: ApplicationFiled: September 29, 2009Publication date: December 1, 2011Applicant: KUMHO ELECTRIC, INC.Inventors: Kwang Bok Kim, Jun Gill Kang, Sung II Oh, Young Kwang Jeong
-
Publication number: 20110291143Abstract: A light emitting device package includes: a substrate with a mounting surface; a light emitting device bonded to the mounting surface of the substrate; a light reflecting resin part containing a high reflective material, filled on the substrate around the light emitting device so as to extend in a space between the light emitting device and the substrate; and a packing resin part hermetically sealed to cover the light emitting device and the light reflection resin part.Type: ApplicationFiled: December 30, 2009Publication date: December 1, 2011Applicant: SAMSUNG LED CO., LTD.Inventors: Jin Ha Kim, Masami Nei, Seok Min Hwang, Chung Bae Jeon
-
Publication number: 20110291144Abstract: A semiconductor optical module M is disclosed, where it includes a stem 2 that installing electronic components 1, a lead pin 3, a circular cap 10, and a lens 5 assembled within the cap 10; and has a flange 12 for welding in an end of the cap 10 opposite to the stem 2, the flange radially extending outward. When the cap 10 is welded to the housing A, the cap 10 may be abutted as setting the welding line b nearly equal to the right angle with respect to the flange 12 of the cap, which increases the welding strength. Because the flange does not form any walls of the cap, the loss of the air-tightness due to the welding may be prevented. Moreover, because the flange radially extends outward at the end of the cap, which is apart from the lens 5, the lens may be secured against the damage.Type: ApplicationFiled: February 22, 2010Publication date: December 1, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kyohiro Yoshida, Takeshi Okada
-
Publication number: 20110291145Abstract: An optoelectronic element includes an optoelectronic unit having a first top surface, a first bottom surface opposite to the first top surface, and a lateral surface between the first top surface and the first bottom surface; a first transparent structure covering the lateral surface and exposing the first top surface of the optoelectronic unit; a first insulating layer on the first top surface and the first transparent structure; a second insulating layer on the first insulating layer; a first opening through the first insulating layer and the second insulating layer; and a first conductive layer on the second insulating layer and electrically connecting to the optoelectronic unit via the first opening.Type: ApplicationFiled: August 9, 2011Publication date: December 1, 2011Applicant: Epistar CorporationInventors: Cheng-Nan Han, Tsung-Xian Lee, Min-Hsun Hsieh, Hung-Hsuan Chen, Hsin-Mao Liu, Hsing-Chao Chen, Ching-San Tao, Chih-Peng Ni, Tzer-Perng Chen, Jen-Chau Wu
-
Publication number: 20110291146Abstract: Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Applicant: Micron Technology, Inc.Inventors: Owen Fay, Xiao Li, Josh Woodland, Shijian Luo, Jaspreet Gandhi, Te-Sung Wu
-
Publication number: 20110291147Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
-
Publication number: 20110291148Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar, a resin layer and a conductive material. The conductive material is provided on a surface of the resin layer between the first metal pillar and the second metal pillar, and electrically connects the first metal pillar and the second metal pillar.Type: ApplicationFiled: September 14, 2010Publication date: December 1, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Sugizaki, Susumu Obata
-
Publication number: 20110291149Abstract: According to one embodiment, a light emitting device includes a light emitting chip, an external terminal made of a metal material, and a circuit board. The light emitting chip is mounted on the circuit board via the external terminal. The light emitting chip includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar and a resin layer. The circuit board includes an interconnection bonded to the first metal pillar and the second metal pillar via the external terminal, and a heat radiation material provided on an opposite side of the interconnection and connected to the interconnection.Type: ApplicationFiled: September 20, 2010Publication date: December 1, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Sugizaki, Hideki Shibata, Akihiro Kojima, Masayuki Ishikawa, Hideo Tamura, Tetsuro Komatsu
-
Publication number: 20110291150Abstract: The invention disclose a light emitting diode (LED) illustration device, comprising a platform, a substrate and a light emitting diode die. The said platform comprises an upper surface and a bottom surface. A first concave portion is formed on the upper surface of the platform, and a second concave portion is formed on the bottom surface of the platform. The first concave portion is connected with the second concave portion. The substrate is embedded in the second concave portion, wherein the said substrate comprises an electrostatic discharge protection structure. The said light emitting diode die is disposed on the said substrate.Type: ApplicationFiled: May 24, 2011Publication date: December 1, 2011Applicant: NEOBULB TECHNOLOGIES, INC.Inventors: Chung-Jen Lin, Yun-Lin Peng
-
Publication number: 20110291151Abstract: According to one embodiment, a light emitting device includes a ceramics substrate, a metallic thermally-conductive layer formed on the substrate in which the substrate involves no electric connection, a light emitting element mounted on the metallic thermally-conductive layer, and a metallic bonding layer interposed between the metallic thermally-conductive layer and the light emitting element to bond the light emitting element to the metallic thermally-conductive layer.Type: ApplicationFiled: May 24, 2011Publication date: December 1, 2011Applicant: TOSHIBA LIGHTING & TECHNOLOGY CORPORATIONInventors: Shuhei MATSUDA, Erika TAKENAKA, Tomohiro SANPEI, Kazuto MORIKAWA, Masahiro IZUMI, Kiyoshi NISHIMURA
-
Publication number: 20110291152Abstract: An LED lead frame includes a housing having a cavity for receiving an LED chip, and a pair of conductive leads mounted with the housing. Each lead includes an embedded section retained in the housing. The embedded section is plated with a silver layer thereon and a water-repellent layer disposed on the silver layer.Type: ApplicationFiled: May 30, 2011Publication date: December 1, 2011Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: BEEN-YANG LIAW
-
Publication number: 20110291153Abstract: A light-emitting diode submount includes a base, a through silicon via and a sealing layer. The base has a die side and a back side. The through silicon via penetrates the base to connect the die side and the back side. The through silicon via includes a conoidal-shaped portion converging from the back side toward the die side, and a vertical via portion connects with the conoidal-shaped portion. A sealing layer seals the vertical via portion.Type: ApplicationFiled: May 31, 2011Publication date: December 1, 2011Inventors: Ming-Kun Yang, Tsang-Yu Liu, Long-Sheng Yeou
-
Publication number: 20110291154Abstract: A semiconductor light emitting device, has a package constituted by the lamination of a first insulating layer having a pair of positive and negative conductive wires formed on its upper face, an inner-layer wire below the first insulating layer, and a second insulating layer below the inner-layer wire; a semiconductor light emitting element that has a pair of positive and negative electrodes on the same face side and that is disposed with these electrodes opposite the conductive wires; and a sealing member that covers the semiconductor light emitting element, wherein part of the conductive wires is formed extending in the outer edge direction of the sealing member from directly beneath the semiconductor light emitting element, on the upper face of the first insulating layer, and is connected to the inner-layer wire via a conductive wire disposed in the thickness direction of the package, and the inner-layer wire is disposed so as to be spaced apart from the outer periphery of the semiconductor light emittingType: ApplicationFiled: October 14, 2009Publication date: December 1, 2011Applicant: NICHIA CORPORATIONInventors: Takuya Noichi, Yuichi Okada, Takahito Miki
-
Publication number: 20110291155Abstract: A light-emitting diode chip package body with an excellent heat dissipation performance and a low manufacturing cost, and a packaging method of the same are disclosed. A LED chip package body is provided, the LED chip package body comprising: a LED chip having an electrode-side surface and at least two electrodes mounted on said electrode-side surface; an electrode-side insulating layer formed on said electrode-side surface of said LED chip and formed with a plurality of through-holes registered with corresponding said electrodes; a highly heat-dissipating layer formed in each of said through-holes of said insulating layer on said electrode-side surface; and a highly heat-conducting metal layer formed on said highly heat-dissipating layer in each of said through-holes.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Inventor: Yu-Nung Shen
-
Publication number: 20110291156Abstract: An organic compound layer includes a fluorescent light-emitting sub-layer, a phosphorescent light-emitting sub-layer, and an exciton generation sub-layer which is disposed therebetween and which generates excitons. The interface between the fluorescent light-emitting sub-layer and the exciton generation sub-layer serves as an energy barrier for carriers. Excitons are generated on the exciton generation sub-layer side of the interface therebetween.Type: ApplicationFiled: May 26, 2011Publication date: December 1, 2011Applicant: CANON KABUSHIKI KAISHAInventor: Tsutomu Shiratori
-
Publication number: 20110291157Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.Type: ApplicationFiled: May 24, 2011Publication date: December 1, 2011Applicant: DENSO CORPORATIONInventors: Shigeki TAKAHASHI, Norihito Tokura, Satoshi Shiraki, Youichi Ashida, Akio Nakagawa
-
Publication number: 20110291158Abstract: The present invention provides a HPT having high sensitivity and extensive wavelength band characteristics. The collector and barrier layer (5) is formed on the photo-absorption layer (6), wherein the energy level in the conduction band is higher than that of the photo-absorption layer (6), the energy level in the valence band is almost equal to or higher than that of the photo-absorption layer (6) and is a relatively wider gap semiconductor than the photo-absorption layer. The base layer (4) formed on the collector and barrier layer (5), is a relatively narrow gap as compared with the collector and barrier layer (5), wherein the energy level in the conduction band is equal to or higher than that of the collector and barrier layer (5) in the boundary of the collector and barrier layer (5).Type: ApplicationFiled: February 12, 2010Publication date: December 1, 2011Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCCE AND TECHNOLOGYInventors: Mutsuo Ogura, SungWoo Choi, Nobuyuki Hayama, Katsuhiko Nishida
-
Publication number: 20110291159Abstract: This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation. The present invention provides metal electrode with stress release structures to reduce the strain and stresses in these devices.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Inventors: Ishiang Shih, Cindy Xing Qiu, Chunong Qiu, Yi-Chi Shih
-
Publication number: 20110291160Abstract: A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0?1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0<X?Y?1 and 0<Z?Y?1.Type: ApplicationFiled: February 3, 2010Publication date: December 1, 2011Inventors: Kazuki Ota, Yasuhiro Okamoto, Hironobu Miyamoto
-
Publication number: 20110291161Abstract: A physical quality detecting device including: a detecting unit that detects a physical quantity supplied from the outside with photo-converting pixels which are two-dimensionally arranged, each of which has a selecting transistor for outputting a signal from the detecting unit to a signal line. In the physical quality detecting device, the selecting transistor is a depletion-type transistor. The signal line is selectively coupled to a reference voltage.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Applicant: SONY CORPORATIONInventor: Keiji Mabuchi
-
Publication number: 20110291162Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.Type: ApplicationFiled: August 4, 2011Publication date: December 1, 2011Applicant: PANASONIC CORPORATIONInventors: Mitsuyoshi MORI, Toru Okino, Yusuke Otake, Kazuo Fujiwara, Hitomi Fujiwara
-
Publication number: 20110291163Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.Type: ApplicationFiled: December 10, 2010Publication date: December 1, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Stephan Kronholz, Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger
-
Publication number: 20110291164Abstract: A CMOS-implementable TOF detector promptly collects charge whose creation time can be precisely known, while rejecting collection of potentially late arriving charge whose creation time may not be precisely known. Charges created in upper regions of the detector structure are ensured to be rapidly collected, while charges created in the lower regions of the detector structure, potentially late arriving charges, are inhibiting from being collected.Type: ApplicationFiled: February 16, 2010Publication date: December 1, 2011Applicant: CANESTA, INC.Inventors: Cyrus Bamji, Swati Mehta, Tamer Ahmed Taha Elkhatib
-
Publication number: 20110291165Abstract: A detector module, in particular for super-resolution satellites, contains a multi-chip carrier. At least one TDI-CCD detector and at least one CMOS chip are arranged on the multi-chip carrier, and are electrically connected to one another. The CMOS chip contains at least the digital output electronics for the TDI-CCD detector.Type: ApplicationFiled: May 31, 2011Publication date: December 1, 2011Applicant: DEUTSCHES ZENTRUM FUER LUFT- UND RAUMFAHRT E.V.Inventor: Andreas Eckardt
-
Publication number: 20110291166Abstract: An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roger A. Booth, JR., Kangguo Cheng, Toshiharu Furukawa, Chengwen Pei
-
Publication number: 20110291167Abstract: In one embodiment, a semiconductor device includes a substrate having a through hole, and a MEMS capacitor provided above the substrate. The device further includes an integrated circuit configured to control the MEMS capacitor, the circuit including transistors on the substrate and being provided under the MEMS capacitor and on the substrate. Further, an area on the substrate immediately under the MEMS capacitor overlaps at least partially with the through hole.Type: ApplicationFiled: March 15, 2011Publication date: December 1, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Shimooka, Hiroaki Yamazaki
-
Publication number: 20110291168Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.Type: ApplicationFiled: May 27, 2011Publication date: December 1, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Shinya IWASA
-
Publication number: 20110291169Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
-
Publication number: 20110291170Abstract: In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes.Type: ApplicationFiled: December 10, 2010Publication date: December 1, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Dmytro Chumakov, Tino Hertzsch
-
Publication number: 20110291171Abstract: A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated.Type: ApplicationFiled: March 17, 2011Publication date: December 1, 2011Applicant: International Business Machines CorporationInventors: John J. Pekarik, William F. Clark, JR., Robert J. Gauthier, JR., Yun Shi, Yanli Zhang
-
Publication number: 20110291172Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.Type: ApplicationFiled: May 17, 2011Publication date: December 1, 2011Inventors: Sung-Min Hwang, Kyoung-Hoon Kim, Hansoo Kim, Jae-Joo Shim, Jaehoon Jang, Wonseok Cho, Byoungkeun Son, Hoosung Cho
-
Publication number: 20110291173Abstract: The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tamae Takano, Tetsuya Kakehata, Shunpei Yamazaki
-
Publication number: 20110291174Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region.Type: ApplicationFiled: September 20, 2010Publication date: December 1, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Noboru OOIKE, Tomomi Kusaka
-
Publication number: 20110291175Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.Type: ApplicationFiled: April 22, 2011Publication date: December 1, 2011Inventors: Jung-Geun Jee, Seok-Hoon Kim, Su-Jin Shin, Woo-Sung Lee, Tae-Ouk Kwon
-
Publication number: 20110291176Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.Type: ApplicationFiled: August 5, 2010Publication date: December 1, 2011Inventors: Ki-Hong Lee, Moon-Sig Joo, Kwon Hong
-
Publication number: 20110291177Abstract: A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.Type: ApplicationFiled: September 13, 2010Publication date: December 1, 2011Inventors: Ki-Hong Lee, Kwon Hong, Dae-Gyu Shin
-
Publication number: 20110291178Abstract: According to one embodiment, a semiconductor device includes a substrate, a lower gate layer, a stacked body, a dummy electrode layer, an insulating film, and a channel body. The lower gate layer is provided above the substrate. The stacked body includes a plurality of insulating layers and a plurality of electrode layers alternately stacked above the lower gate layer. The dummy electrode layer is provided between the lower gate layer and the stacked body, made of the same material as the electrode layer, and thicker than each of the electrode layers. The insulating film includes a charge storage film provided on a side wall of a hole formed to penetrate through the stacked body and the dummy electrode layer. The channel body is provided on an inside of the insulating film in the hole.Type: ApplicationFiled: March 7, 2011Publication date: December 1, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Toshiyuki SASAKI, Noriko Sakurai, Tokuhisa Ohiwa, Katsunori Yahashi
-
Publication number: 20110291179Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: IMECInventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
-
Publication number: 20110291180Abstract: Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Inventor: Mark D. Hall
-
Publication number: 20110291181Abstract: According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately.Type: ApplicationFiled: May 31, 2011Publication date: December 1, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki IRIFUNE, Yasuto Sumi, Kiyoshi Kimura, Hiroshi Ohta
-
Publication number: 20110291182Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device.Type: ApplicationFiled: June 30, 2010Publication date: December 1, 2011Applicant: Hynix Semiconductor Inc.Inventor: Seung Hwan LEE
-
Publication number: 20110291183Abstract: A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.Type: ApplicationFiled: July 20, 2010Publication date: December 1, 2011Inventors: Wei-Chieh Lin, Guo-Liang Yang, Jia-Fu Lin, Shian-Hau Liao
-
Publication number: 20110291184Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate.Type: ApplicationFiled: September 26, 2010Publication date: December 1, 2011Applicant: Institute of Microelectronics, Chinese Academy of SciencesInventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
-
Publication number: 20110291185Abstract: A semiconductor device having a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area, and a method for the manufacture thereof. The invention particularly concerns a termination structure for such devices having trenched electrodes in the active area. The termination structure comprises a plurality of lateral trench-gate transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body. The lateral devices are arranged such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices. The termination structure is compact and features of the structure are susceptible for formation in the same process steps as features of the active area.Type: ApplicationFiled: May 21, 2004Publication date: December 1, 2011Inventor: Raymond J. Grover
-
Publication number: 20110291186Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Inventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
-
Publication number: 20110291187Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Inventors: Wing Chor Chan, Chih-Min Hu, Shyi-Yuan Wu, Jeng Gong
-
Publication number: 20110291188Abstract: A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Xuefeng Hua, Ying Zhang
-
Publication number: 20110291189Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.Type: ApplicationFiled: May 28, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
-
Publication number: 20110291190Abstract: A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern.Type: ApplicationFiled: September 28, 2010Publication date: December 1, 2011Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: De Yuan Xiao, Guo Qing Chen, Roger Lee, Chin Fu Yen, Su Xing, Xiao Lu Huang, Yong Sheng Yang