Abstract: The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process.

Abstract: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

Abstract: A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET.

Abstract: A protection circuit for a semiconductor device includes a first gate electrode formed on a substrate of a first conductivity type, and a source and a drain of a second conductivity type having an opposite polarity to the first conductivity type. The source and the drain are commonly coupled to a ground voltage terminal, and the first gate electrode is coupled to a power supply voltage terminal.

Abstract: Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

Abstract: Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.

Abstract: A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device.

Abstract: The memory cell is of SRAM type with four transistors provided with a counter-electrode. It comprises a first area made from semiconductor material with a first transfer transistor and a first driver transistor connected in series, their common terminal defining a first electric node. A second transfer transistor and a second driver transistor are connected in series on a second area made from semiconductor material and their common terminal defines a second electric node. The support substrate comprises first and second counter-electrodes. The first and second counter-electrodes are located respectively facing the first and second semiconductor material areas. The first transfer transistor and second driver transistor are on a first side of a plane passing through the first and second electric nodes whereas the first driver transistor and second transfer transistor are on the other side of the plane.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

Abstract: A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.

Abstract: A semiconductor device according to an embodiment of the present invention includes a active region, a drain electrode, a source electrode, a gate electrode, a passivation layer, a source field plate, and a electrical connection. The active region is formed on a semiconductor substrate. The drain electrode, the source electrode, and the gate electrode are formed on a surface of the active region to be separated from each other. The passivation layer is formed on a surface of the active region between the drain electrode and the source electrode to cover the gate electrode. The source field plate is formed at least at a position including an upper portion of the drain-side end portion of the gate electrode on a surface of the passivation layer. The electrical connection is formed on the passivation layer to connect the source field plate and the source electrode. The electrical connection has a width of the electrical connection smaller than electrode widths of the source field plate and the source electrode.

Abstract: A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer.

Abstract: A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

Abstract: A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a centre of the channel region.

Abstract: A transducer array on a common substrate includes a membrane and first and second transducer devices. The membrane is formed on the common substrate, and includes a lower layer and an upper layer. The first transducer device includes a first resonator stack formed on at least the lower layer in a first portion of the membrane, the upper layer having a first thickness in the first portion of the membrane. The second transducer device includes a second resonator stack formed on at least the lower layer in a second portion of the membrane, the upper layer having a second thickness in the second portion of the membrane, where the second thickness is different from the first thickness, such that a first resonant frequency of the first transducer device is different from a second resonant frequency of the second transducer device.

Abstract: Manufacturing of an element structure including a capacitor is to be facilitated. An element structure includes a first substrate that has a first support layer and a first movable beam having one end supported side the first support layer and the other end having a void part provided therearound and a second substrate that has a second support layer and a first fixing electrode formed side the second support layer wherein the second substrate is disposed to face above the first substrate, the first movable beam is provided with a first movable electrode and the first fixing electrode and the first movable electrode are disposed to face each other, with a gap therebetween.

Abstract: To provide a magnetic memory device having an increased write current and improved reliability in writing. The magnetic memory device of the invention has a substrate, a write line provided over the substrate, a bit line placed with a space from the write line in a thickness direction of the substrate and extending in a direction crossing with an extending direction of the write line, and a magnetic memory element positioned between the write line and the bit line. The magnetic memory element has a pinned layer whose magnetization direction has been fixed and a recording layer whose magnetization direction changes, depending on an external magnetic field. The recording layer contains an alloy film. The alloy film contains cobalt, iron, and boron and its boron content exceeds 21 at %.

Abstract: A power converter comprises a first die and a second die. Each die comprises a semiconductor substrate comprising a junction for converting nuclear radiation particles to electrical energy, the junction of each semiconductor substrate comprising a first side and a second side, a first electrode comprising a nuclear radiation-emitting radioisotope deposited on the semiconductor substrate, the first electrode being electrically connected to the first side of the junction, and a second electrode deposited on the semiconductor substrate, the second electrode being electrically connected to the second side. A bond is formed between one of the first electrode or the second electrode of the first die and one of the first electrode or the second electrode of the second die, wherein the bond forms an electrical contact between the bonded electrodes.

Abstract: A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material.

Abstract: A photosensor comprises a photoelectric conversion device region and a connection pad on the lower surface of a semiconductor substrate, and also comprises a wiring line connected to the connection pad via insulating film under the semiconductor substrate, and a columnar electrode as an external connection electrode connected to the wiring line. As a result, as compared with the case where the photoelectric conversion device region and the connection pad connected to the photoelectric conversion device region are formed on the upper surface of the semiconductor substrate, a piercing electrode for connecting the connection pad and the wiring line does not have to be formed in the semiconductor substrate. Thus, the number of steps can be smaller, and a fabrication process can be less restricted.

Abstract: A semiconductor substrate 2 is dry etched before an insulating layer 4 is exposed, whereby a hole H1 penetrating through the semiconductor substrate 2 and reaching the insulating layer 4 is formed at a position corresponding to a photosensitive region S1. Next, an irregular asperity 22 is formed in a surface 7 of an n+ type embedded layer 6 exposed in the hole H1. The surface of the n+ type embedded layer 6 exposed in the hole H1 through the insulating layer 4 is irradiated with a picosecond to femtosecond pulsed laser beam, whereby the insulating layer 4 is removed and the surface 7 of the n+ type embedded layer 6 exposed in the hole H1 is roughened by the picosecond to femtosecond pulsed laser beam, to form the irregular asperity 22 in the entire area of the surface 7. Then the substrate with the irregular asperity 22 therein is subjected to a thermal treatment.

Abstract: A method for fabricating an image sensor includes forming an insulation layer over a substrate in a logic circuit region and a pixel region, forming a photoresist over the insulation layer, patterning the photoresist to form a photoresist pattern where the insulation layer in the pixel region is exposed and the insulation layer in the logic circuit region is not exposed, wherein a thickness of the photoresist pattern is gradually decreased in an interfacial region between the pixel region and the logic circuit region in a direction of the logic circuit region to the pixel region, and performing an etch back process over the insulation layer and the photoresist pattern in conditions that an etch rate of the photoresist pattern are substantially the same as that of the insulation layer.

Abstract: The present invention discloses a wafer level image sensor packaging structure and a manufacturing method for the same. The manufacturing method includes the following steps: providing a silicon wafer with image sensor chips, providing a plurality of transparent lids, allotting one said transparent lid on top of the corresponding image sensor chip, and carrying out a packaging process. The manufacturing method of the invention has the advantage of having a simpler process, lower cost, and higher production yield rate. The encapsulation compound arranges on the first surface of the image sensor chip and covers the circumference of the transparent lid to avoid the side light leakage as traditional chip scale package (CSP). Thus, the sensing performance of the wafer level image sensor packaging structure can be enhanced.

Abstract: In an image sensor 1 according to an embodiment of the present invention, a plurality of embedded photodiodes PD(m,n) are arrayed. Each of the embedded photodiodes PD(m,n) comprises a first semiconductor region 10 of a first conductivity type; a second semiconductor region 20 formed on the first semiconductor region 10 and having a low concentration of an impurity of a second conductivity type; a third semiconductor region 30 of the first conductivity type formed on the second semiconductor region 20 so as to cover a surface of the second semiconductor region 20; and a fourth semiconductor region 40 of the second conductivity type for extraction of charge from the second semiconductor region 20; the fourth semiconductor region 40 comprises a plurality of fourth semiconductor regions 40 arranged as separated, on the second semiconductor region 20.

Abstract: A photoelectric converter includes a substrate, photoelectric converting elements formed in the substrate and each having a light-receiving surface, an antireflection film arranged above at least a part of the light-receiving surface of each photoelectric converting element, an element isolation region including an insulator, a plurality of transistors including read transistors configured to read electric charges of the photoelectric converting elements, an interlayer insulating film arranged above the photoelectric conversion elements and the read transistors, and contacts electrically connected to active regions of the transistors. The antireflection film is arranged above the element isolation region and the active region connected to each contact. The antireflection film serves as an etch stop film when the interlayer insulating film is etched.

Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CR The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.

Abstract: A backside illumination image sensor, a method of fabricating the same, and an electronic system including the backside illumination image sensor, the backside illumination image sensor including a semiconductor substrate, the semiconductor substrate having an upper surface and a lower surface; photodiodes in the semiconductor substrate; and metal interconnections below the semiconductor substrate, wherein each of the photodiodes includes a N-type region, a lower P-type region below the N-type region, and an upper P-type region on the N-type region.

Abstract: According to one embodiment, a solid-state imaging device includes a first diffusion layer for accumulating carriers generated by a photoelectric effect; a second diffusion layer adjoining the first diffusion layer, the second diffusion layer having a polarity opposite to that of the first diffusion layer; and a reference voltage setting unit that applies a changing voltage that temporally changes to the first diffusion layer through the second diffusion layer and sets a voltage based on an amplitude of the applied changing voltage as a reference voltage of the first diffusion layer.

Abstract: A semiconductor light receiving device includes: a substrate having a rectangular shape with first through fourth corners, a multilayer structure formed on the substrate, a light receiving part having a mesa structure positioned at a first corner side from a center part of the rectangular shape of the substrate, a first electrode pad provided on the semiconductor substrate, and a second electrode pad provided on the semiconductor substrate so as to be close to a second corner diagonally opposite to the first corner, a first minimum distance between the second electrode pad and an edge of the substrate being longer than a second minimum distance between the first electrode pad and the edge of the substrate.

Abstract: An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region.

Abstract: A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow.

Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.

Abstract: A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract: A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process.

Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.

Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Abstract: There is disclosed a package comprising at least an integrated circuit embedded in an electrically non-conductive moulded material. The moulded material includes at least one moulded pattern on at least one surface thereof, and at least one electrically conductive track in the pattern. There is further provided at least one capacitive, inductive or galvanic component electrically connecting between at least two parts of the at least one electrically conductive track. The conductive track can be configured as an antenna, and the capacitive, inductive or galvanic component is used to adjust tuning and other characteristics of the antenna.

Abstract: A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region.

Abstract: The present invention discloses a copper interconnection structure with MIM capacitor and a manufacturing method thereof. The method firstly makes a copper conductive pattern in a copper interconnection structure and a copper through hole bolt connected with the copper conductive pattern; etch away an insulation layer around the copper through hole bolt and deposit a etch stop layer, so as to expose the top and side surface of the copper through hole bolt and part of the top surface of the copper conductive pattern; deposit a dielectric layer on the obtained structure and fill a protection material in the recession area of the obtained structure; etch a trench for receiving other copper conductive patterns; remove the protection material; plate copper in the recession area, and plate copper in the trench, so as to obtain a copper interconnection structure with MIM capacitor.

Abstract: A semiconductor module is provided which is capable of lowering surges caused when switching elements are switched on and off. The module has a plurality of lead frames, switching elements, electronic components, and a sealing member. The switching elements are electrically connected to the lead fames respectively. Part of the lead frames, the switching elements, and the electronic components are sealed by the sealing member. The electronic components are mounted on primary surfaces of the lead frames respectively.

Abstract: Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip.

Abstract: A semiconductor device includes: a first interlayer insulating film; a first conductive member provided lower than the first interlayer insulating film; a contact plug that penetrates through the first interlayer insulating film, and is electrically connected to the first conductive member, the contact plug including a small-diameter part, and a large-diameter part arranged on the small-diameter part, an outer diameter of the large-diameter part being larger than an outer diameter of the small-diameter part, and the outer diameter of the large-diameter part being larger than an outer diameter of a connection face between the second conductive member and the large-diameter part; and a second conductive member that is provided on the first interlayer insulating film, and is electrically connected to the contact plug.

Abstract: To provide a power storage device with improved cycle characteristics and a method for manufacturing the power storage device, a power storage device is provided with a conductive layer in contact with a surface of an active material layer including a silicon layer after an oxide film, such as a natural oxide film, which is formed on the surface of the active material layer is removed. The conductive layer is thus provided in contact with the surface of the active material layer including a silicon layer, whereby the conductivity of the electrode surface of the power storage device is improved; therefore, cycle characteristics of the power storage device can be improved.