Abstract: A semiconductor device that has a reduced size and exhibits a superior blocking voltage capability. A semiconductor device includes an edge termination structure between an active region and an isolation region, the edge termination structure being composed of an edge termination structure for a forward bias section and an edge termination structure for a reverse bias section. A plurality of field limiting rings (FLRs) and a plurality of field plates (FPs) are provided in the edge termination structure for the forward bias section and the edge termination structure for the reverse bias section. A first forward FP that is the nearest of the plurality of FPs to the edge termination structure for the reverse bias section is formed to extend towards the isolation region side. A first reverse FP that is the nearest of the plurality of FPs to the edge termination structure for the forward bias section is formed to extend towards the active region side.

Abstract: In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween.

Abstract: Methods for manufacturing a semiconductor device in a processing chamber are provided.

Abstract: A semiconductor device includes a wiring substrate having an insulating film formed on a surface thereof, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip stacked and mounted on the first semiconductor chip so as to form an overhang portion. The insulating film is removed from an area of the wiring substrate that faces the overhang portion.

Abstract: A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging.

Abstract: A semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material. The filling material fills a gap between the semiconductor chips.

Abstract: The present invention relates to a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.

Abstract: A shielding structure comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias.

Abstract: A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect.

Abstract: A semiconductor chip package is provided. The semiconductor chip package includes a lead frame having a chip carrier. A semiconductor chip is mounted on the chip carrier, having a plurality of bonding pads thereon. A package substrate has a cavity therein to accommodate the chip carrier and the semiconductor chip, wherein at least one of the bonding pads of the semiconductor chip is electrically coupled to the package substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first lead adjacent and staggered to a second lead, the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion; connecting an integrated circuit device with the first internal connection portion and with the second internal connection portion; forming an encapsulation over the integrated circuit device with the first lead and the second lead exposed; and forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.

Abstract: A method and system for forming a thin semiconductor device are disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection.

Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.

Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with at least one die through electrically conducting bumps or balls and electrically conducting ribbons. Embodiments of the present invention may permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.

Abstract: A carrier for holding a plurality of chip packages and a carrier assembly are provided, wherein the chip package has a central area without solder balls and a peripheral area with solder balls formed thereon. The carrier includes a tray component and a plurality of supports disposed on the tray component, wherein each support holds the central area of a respective chip package. The carrier assembly is formed by stacking a plurality of the carriers through a plurality of peripheral projections disposed at a periphery of each tray component, wherein each peripheral projection has a pin formed thereon and a hole formed thereunder.

Abstract: A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed within the insulating layer such that the contact area and the insulating layer include coplanar exposed surfaces and the contact area is electrically connected with the electrically conductive layer and includes an extension which is greater than the extension of the electrically conductive layer along a direction parallel to the main surface of the semiconductor chip.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; pressing an encapsulation onto the package carrier and with the integrated circuit therein; mounting a conductive frame, having a vertical pillar integral with a horizontal cover, through the encapsulation, over the integrated circuit, and the vertical pillar on the package carrier and the horizontal cover on the encapsulation; and forming a contact from the horizontal cover.

Abstract: A heat radiation component configured to be provided through a thermal interface material on a semiconductor device mounted on a board includes a first layer to be positioned on a first side and a second layer stacked on the first layer to be positioned on a second side farther from the semiconductor device than the first side. The coefficient of thermal expansion of the second layer is lower than the coefficient of thermal expansion of the first layer.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.

Abstract: A semiconductor encapsulation adhesive composition comprising (a) an epoxy resin, (b) a curing agent and (c) an antioxidant.

Abstract: An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate.

Abstract: A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.

Abstract: A method of fabricating IC die includes providing a substrate having a topside semiconductor surface including active circuitry and a bottomside surface. The IC die includes at least one protruding feature coupled to the active circuitry that protrudes from the bottomside surface or the topside semiconductor surface. The topside semiconductor surface and/or bottomside surface and the protruding feature are coated with a dielectric polymer. A portion of the dielectric polymer is removed from the protruding feature using a solvent to expose a tip portion of the protruding feature for electrical connection thereto. With a solvent that does not corrode or oxidize the exposed protruding feature tips, the need for a conventional subsequent chemical exposure to remove corrosion or oxidation is avoided.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a number of stacked semiconductor chips. Each of the semiconductor chips includes a first through electrode formed through the semiconductor chip, a first bump pad formed over the semiconductor chip at a region where the first bump pad is separated from the first through electrode, a first internal circuit formed inside the semiconductor chip, coupled to the first through electrode through a first metal path, and coupled to the first bump pad through a second metal path; and a redistribution layer (RDL) formed over a backside of the semiconductor chip.

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.

Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.

Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.

Abstract: In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device.

Abstract: A semiconductor device with improved quality and reliability is provided. In a UBM formed over an electrode pad located over a semiconductor substrate, the edge (end) of an Au film as an upper layer is located inside or in the same position as the edge (end) of a TiW film as a lower layer, which can suppress the formation of a suspended part in the Au film. This arrangement can prevent the occurrence of electrical short circuit between the adjacent pads due to the suspended part and the adhesion of the suspended part as foreign matter to the semiconductor substrate, thus improving the quality and reliability of the semiconductor device (semiconductor chip).

Abstract: A semiconductor chip such as an MMIC is provided. The semiconductor chip has: a Si semiconductor as a substrate; and a low-loss transmission line, and can be easily connected to a circuit board on which the semiconductor chip is to be mounted and can ensure a stable GND potential. The semiconductor chip is a flip-chip semiconductor chip, and includes: a Si substrate; an integrated circuit manufactured on a main surface of the substrate; a dielectric film formed above the integrated circuit; and a conductor film for grounding formed on an upper surface of the dielectric film. The integrated circuit includes a wiring layer including a signal line which transmits signals for the integrated circuit. The signal line, the dielectric film, and the conductor film constitute a microstrip line.

Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.

Abstract: A chip bump structure is formed on a substrate. The substrate includes at least one contact pad and a dielectric layer. The dielectric layer has at least one opening. The at least one opening exposes the at least one contact pad. The chip bump structure includes at least one elastic bump, at least one first metal layer, at least one second metal layer, and at least one solder ball. The at least one elastic bump covers a central portion of the at least one contact pad. The at least one first metal layer covers the at least one elastic bump. The at least one first metal layer has a portion of the at least one contact pad. The portion of the at least one contact pad is not overlaid by the at least one elastic bump. The at least one second metal layer is formed on a portion of the at least one first metal layer. The portion of the at least one first metal layer is located on the top of the at least one elastic bump. The at least one solder ball is formed on the at least one second metal layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips.

Abstract: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic components of the microelectronic packages may have sintered conductive vias comprising sintered metal and magnetic particles.

Abstract: A semiconductor device includes a wiring, a stack of first, second, and third films, and a contact plug. The stack of first, second, and third films is located over the wiring. The first, second, and third films are stacked in this order. The stack has an opening. The first film is made of the same material as the third film. The contact plug is in the opening. The contact plug is in contact with the wiring.

Abstract: Electronic elements with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes, preferably dielectric lined, in front sides of substrates, filling the trenches or pipes with a conductor having a coefficient of expansion not too different from that of the substrate but of higher conductivity, forming an epitaxial SC layer over the front side of the substrate in Ohmic contact with the conductor the trenches or pipes, forming various semiconductor (SC) devices in the epi-layer, back grinding the substrate to expose bottoms of the conductor filled trenches or pipes, and providing a back-side conductor contacting the conductor in the trenches or pipes. For silicon SCs, tungsten is a suitable conductor for filling the trenches or pipes to minimize substrate stress. Series ON-resistance of the elements due to the substrate resistance is substantially reduced.

Abstract: Disclosed is a semiconductor article which includes a semiconductor base portion, a back end of the line (BEOL) wiring portion on the semiconductor base portion, a through silicon via and a guard ring. The semiconductor base portion is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having metallic wiring and insulating material. The BEOL wiring portion does not include a semiconductor material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor base portion. The guard ring surrounds the through silicon via in the BEOL wiring portion.

Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.

Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.

Abstract: A junction body has a first member and a second member each of which is provided with a joining surface whose main component is copper. A solder member containing, in a tin-base solder material, a three-dimensional web structure whose main component is copper is provided between the first member and the second member. A copper-tin alloy whose average thickness is 2 ?m or more but 20 ?m or less is provided between the joining surfaces and the three-dimensional web structure.

Abstract: A method of manufacture of an integrated circuit package system includes: providing a through-silicon-via die having conductive vias therethrough; forming a first redistribution layer on a bottom of the through-silicon-via die coupled to the conductive vias; forming a second redistribution layer on the top of the through-silicon-via die coupled to the conductive vias; fabricating an embedded die superstructure on the second redistribution layer including: mounting an integrated circuit die to the second redistribution layer, forming a core material layer on the second redistribution layer to be coplanar with the integrated circuit die, forming a first build-up layer, having contact links coupled to the integrated circuit die, on the core material layer, and coupling component interconnect pads to the contact links; and forming system interconnects on the first redistribution layer for coupling the through-silicon-via die, the integrated circuit die, the component interconnect pads, or a combination thereof.

Abstract: An interconnect structure is provided that includes at least one patterned and cured photo-patternable low k material located on a surface of a patterned and cured oxygen-doped SiC antireflective coating (ARC). A conductively filled region is located within the at least one patterned and cured photo-patternable low k material and the patterned and cured oxygen-doped SiC ARC. The oxygen-doped SiC ARC, which is a thin layer (i.e., less than 400 angstroms), does not produce standing waves that may degrade the diffusion barrier and the electrically conductive feature that are embedded within the patterned and cured photo-patternable low k dielectric material and, as such, structural integrity is maintained. Furthermore, since a thin oxygen-doped SiC ARC is employed, the plasma etch process time used to open the material stack of the ARC/dielectric cap can be reduced, thus reducing potential plasma damage to the patterned and cured photo-patternable low k material.

Abstract: A die seal of a semiconductor device may be provided with a varying pattern density such that a gradient between the die region and the die seal may be reduced. Consequently, for a given width of the die seal, a required mechanical stability may be achieved, while at the same time differences in topography between the die region and the die seal may be reduced, thereby contributing to superior process conditions for sophisticated lithography processes.

Abstract: An electronic device including a die-pad area, a die fixed to the die-pad area, a connection terminal, and a ribbon of conductive material. The ribbon is electrically connected to the die and to the connection terminal, and has a prevalent dimension along a first axis, a width, measured along a second axis, which is transverse to the first axis, and a thickness, which is negligible with respect to the width; the ribbon moreover has a cross section that defines a concave geometrical shape.

Abstract: A device has a silicon substrate with a via extending from a first surface of the silicon substrate having a conductor portion. A first dielectric portion surrounds the conductor portion. A second dielectric portion is disposed between a first silicon portion and the silicon substrate.

Abstract: A package system includes an integrated circuit disposed over an interposer. The interposer includes a first interconnect structure. A first substrate is disposed over the first interconnect structure. The first substrate includes at least one first through silicon via (TSV) structure therein. A molding compound material is disposed over the first interconnect structure and around the first substrate. The integrated circuit is electrically coupled with the at least one first TSV structure.

Abstract: A semiconductor integrated circuit includes first power supply through-chip vias formed through the semiconductor chip to be in a line in a first direction of the semiconductor chip, second power supply through-chip vias formed through the semiconductor chip to be in, first power lines arranged in a second direction, wherein each of the plurality of first power lines is coupled to each of the first power supply through-chip vias, and second power lines arranged in the second direction, wherein each of the plurality of second power lines is coupled to each of the second power supply through-chip vias.

Abstract: A semiconductor device includes a through-silicon-via arranged to couple a plurality of stacked semiconductor chips, an interconnection line coupled to the through-silicon-via at one side and arranged to couple the through-silicon-via to the semiconductor chip, an internal interconnection line disposed at the other side of the interconnection line and intersected with the interconnection line, and at least one first contact disposed to couple the internal interconnection line to the interconnection line. A region of the interconnection line in which the internal interconnection line is disposed is equally divided, and an area between the divided regions is removed.