Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

Abstract: An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.

Abstract: A method for fabricating a semiconductor device with improved bonding ability is disclosed. The method comprises providing a substrate having a front surface and a back surface; forming one or more sensor elements on the front surface of the substrate; forming one or more metallization layers over the front surface of the substrate, wherein forming a first metallization layer comprises forming a first conductive layer over the front surface of the substrate; removing the first conductive layer from a first region of the substrate; forming a second conductive layer over the front surface of the substrate; and removing portions of the second conductive layer from the first region and a second region of the substrate, wherein the first metallization layer in the first region comprises the second conductive layer and the first metallization layer in the second region comprises the first conductive layer and the second conductive layer.

Abstract: A graphite substrate is processed to have surface unevenness in a range of 1 ?m to 8 ?m. Thereby, a semiconductor film to be laminated on the graphite substrate has a stable film quality, and thus adhesion of the graphite substrate and the semiconductor layer can be enhanced. When an electron blocking layer is interposed between the graphite substrate and the semiconductor layer, the electron blocking layer is thin and thus the surface unevenness of the graphite substrate is transferred onto the electron blocking layer. Consequently, the electron blocking layer also has surface unevenness approximately in such range. Thus, almost the same effect as a configuration in which the semiconductor layer is directly connected to the graphite substrate can be produced.

Abstract: Silicon nitride coated crucibles for holding melted semiconductor material and for use in preparing multicrystalline silicon ingots by a directional solidification process; methods for coating crucibles; methods for preparing silicon ingots and wafers; compositions for coating crucibles and silicon ingots and wafers with a low oxygen content.

Abstract: Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer.

Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices.

Abstract: A pixel structure including a substrate, a gate, an insulation layer, a metal oxide semiconductor (MOS) layer, a source and a drain, at least one film layer, and a first electrode layer is provided. The gate is disposed on the substrate. The insulation layer covers the gate. The MOS layer is disposed on the insulation layer above the gate. The source and the drain are disposed on the MOS layer. The film layer covers the MOS layer and includes a transparent photocatalytic material, wherein the transparent photocatalytic material blocks ultraviolet light from reaching the MOS layer. The first electrode layer is electrically connected to the source or the drain.

Abstract: A pixel structure includes a first patterned metal layer, a gate insulating layer, a semiconductor channel layer, a second patterned metal layer, a passivation layer, and a conducting layer. A gate line of the second patterned metal layer is electrically connected by the conducting layer to a gate extension electrode of the first patterned metal layer. A source electrode of the second patterned metal layer is electrically connected by the conducting layer to a second data line segment of the first patterned metal layer. A method for fabricating a pixel structure is also disclosed herein.

Abstract: A storage capacitor architecture for pixel structure and manufacturing method thereof are described. The storage capacitor architecture includes a substrate, a first electrode, an insulating layer and a second electrode. The first electrode has a first concave and convex structure. The insulating layer is disposed on the first concave and convex structure of the first electrode. The second electrode is disposed on the insulating layer and has a second concave and convex structure. The first concave and convex structure and the second concave and convex structure form an interdigitated space and the insulating layer is disposed in the interdigitated space to solve the problem of decreased aperture ratio of the LCD panel.

Abstract: An organic light-emitting display device includes a capacitor lower electrode that includes a semiconductor material doped with ion impurities. A first insulating layer covers an active layer and the capacitor lower electrode. A gate electrode includes a gate lower electrode formed of a transparent conductive material and a gate upper electrode formed of metal. A pixel electrode is electrically connected to the thin film transistor. A capacitor upper electrode is at the same level as the pixel electrode. An etch block layer is formed between the first insulating layer and the capacitor upper electrode. Source and drain electrodes are electrically connected to the active layer. A second insulating layer has an opening completely exposing the capacitor upper electrode. A third insulating layer exposes the pixel electrode. An intermediate layer includes an emissive layer. An opposite electrode faces the pixel electrode.

Abstract: An organic light emitting display apparatus includes a substrate on which a display area and a non-display area are defined, a first electrode on the substrate, an intermediate layer on the first electrode, the intermediate layer includes an organic emission layer, a second electrode on the intermediate layer, a plurality of pad units on the non-display area, and an insulating layer on the pad units. The insulating layer includes contact holes overlapping upper surfaces of the pad units and grooves adjacent to the contact holes.

Abstract: A flat panel display device includes a substrate having an emission area in which an image is displayed and a pad area that is outside of the emission area, a semiconductor layer on the substrate, and the semiconductor layer has crystallization areas and amorphous areas. An electrostatic protecting circuit is on a portion of at least one of the amorphous areas corresponding to the pad area, and a panel circuit unit is on a portion of at least one of the crystallization areas corresponding to the pad area.

Abstract: A display unit includes, on a substrate: a plurality of light emitting devices in which a first electrode, an organic layer including a light emitting layer, and a second electrode are respectively and sequentially layered; and a black insulating layer separating the organic layer for the every light emitting device.

Abstract: A semiconductor thin-film manufacturing method includes: forming, above a substrate, an amorphous silicon film (precursor film) having a photoluminescence (PL) intensity greater than or equal to 0.65 when photon energy is 1.1 eV in a PL spectrum normalized to have a maximum PL intensity of 1; and annealing the amorphous silicon film to form a crystalline silicon film.

Abstract: A silicon wafer used in manufacturing crystalline GaN for light emitting diodes (LEDs) includes a silicon substrate, a buffer layer of aluminum nitride (AlN) and an upper layer of GaN. The silicon wafer has a diameter of at least 200 millimeters and an Si(111)1×1 surface. The AlN buffer layer overlies the Si(111) surface. The GaN upper layer is disposed above the buffer layer. Across the entire wafer substantially no aluminum atoms of the AlN are present in a bottom most plane of atoms of the AlN, and across the entire wafer substantially only nitrogen atoms of the AlN are present in the bottom most plane of atoms of the AlN. A method of making the AlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and then a subsequent amount of ammonia through the chamber.

Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

Abstract: A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (BxAl1-xN) and an upper layer of GaN, for which 0.35?x?0.45. The BAlN forms a wurtzite-type crystal with a cell unit length about two-thirds of a silicon cell unit length on a Si(111) surface. The C-plane of the BAlN crystal has approximately one atom of boron for each two atoms of aluminum. Across the entire wafer substantially only nitrogen atoms of BAlN form bonds to the Si(111) surface, and substantially no aluminum or boron atoms of the BAlN are present in a bottom-most plane of atoms of the BAlN. A method of making the BAlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and triethylboron and then a subsequent amount of ammonia through the chamber.

Abstract: A gallium and nitrogen containing optical device has a base region and no more than three major planar side regions configured in a triangular arrangement provided from the base region.

Abstract: A light emitting device includes a substrate, multiple n-type layers, and multiple p-type layers. The n-type layers and the p-type layers each include a group III nitride alloy. At least one of the n-type layers is a compositionally graded n-type group III nitride, and at least one of the p-type layers is a compositionally graded p-type group III nitride. A first ohmic contact for injecting current is formed on the substrate, and a second ohmic contact is formed on a surface of at least one of the p-type layers. Utilizing the disclosed structure and methods, a device capable of emitting light over a wide spectrum may be made without the use of phosphor materials.

Abstract: A power semiconductor device is provided. The power semiconductor device includes a source electrode disposed on a device activation region and widened in a direction toward a first side, a drain electrode arranged alternately with the source electrode on the device activation region and widened in a direction toward a second side facing the first side, an insulating layer disposed on the source electrode and the drain electrode and configured to include a plurality of via contacts contacting the source electrode and the drain electrode, a source electrode pad disposed in a first region on the insulating layer to be brought into contact with the source electrode, and a drain electrode pad disposed in a second region separated from the first region on the insulating layer and brought into contact with the plurality of via contacts contacting the drain electrode.

Abstract: Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a composition modulation layer that is formed of a first composition layer made of AlN and a second composition layer made of AlxGa1-xN (0?x<1) being alternately laminated. The relationship of x(1)?x(2)? . . . ?x(n?1)?x(n) and x(1)>x(n) is satisfied, where n represents the number of laminations of each of the first and the second composition layer (n is a natural number equal to or greater than two), and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side, to thereby cause a compressive strain to exist such that the compressive strain increases in a portion more distant from the base substrate.

Abstract: An object of the present invention is to provide a nitride semiconductor light emitting element having a novel transparent electrode. The nitride semiconductor light emitting element has the transparent electrode on a p-type nitride semiconductor layer, wherein the p-type nitride semiconductor layer and the transparent electrode can be in good ohmic contact to each other and wherein the variability of the forward voltage (Vf) within the wafer can be reduced. The present invention is a nitride semiconductor light emitting element including: an n-side nitride semiconductor layer; a p-side nitride semiconductor layer; and a transparent electrode formed on the p-side nitride semiconductor layer, wherein the transparent electrode is made of indium oxide containing Ge and Si.

Abstract: Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a plurality of composition modulation layers each formed of a first composition layer made of AlN and a second composition layer made of AlxGa1-xN (0?x<1) being alternately laminated. The relationship of x(1)?x(2)? . . . ?x(n?1)?x(n) and x(1)>x(n) is satisfied, where n represents the number of laminations of each of the first and the second composition layer, and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side. Each of the second composition layers is formed so as to be in a coherent state relative to the first composition layer.

Abstract: An N-face GaN HEMT device including a semiconductor substrate, a buffer layer including AlN or AlGaN deposited on the substrate, a barrier layer including AlGaN or AlN deposited on the buffer layer and a GaN channel layer deposited on the barrier layer. The channel layer, the barrier layer and the buffer layer create a two-dimensional electron gas (2-DEG) layer at a transition between the channel layer and the barrier layer.

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract: The present invention discloses a LED structure and a method for manufacturing the LED structure. The LED structure includes a substrate, a reflection layer, a first conducting layer, a light emitting layer, and a second conducting layer. The substrate has a plurality of grooves, and the reflection layer is disposed inside the plurality of grooves. The reflection layer is formed as a reflection block inside each of the grooves. The first conducting layer is disposed on the substrate, that is, the reflection layer is disposed between the first conducting layer and the substrate. The light emitting layer and the second conducting layer are sequentially disposed on the first conducting layer. The light emitting layer generates light when a current pass through the light emitting layer. Accordingly, the light generated by the light emitting layer can be emitted to the same side of the LED structure.

Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.

Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.

Abstract: An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: A method for manufacturing a semiconductor device, comprising forming a tunneling dielectric layer, a storage dielectric layer, a gate dielectric layer and a gate layer sequentially on a semiconductor substrate of a first semiconductor material; patterning the tunneling dielectric layer, the storage dielectric layer, the gate dielectric layer and the gate layer to form a gate stack; forming a groove in the semiconductor substrate on the sides of the gate stack; filling the groove with a second semiconductor material different from the first semiconductor material, meanwhile, the entire device is covered by the dielectric layer. The surface energy level in the channel is made to change by the stress generated by the second semiconductor material and the covering dielectric layer, thereby increasing tunneling current and improving the storage efficiency of the device.

Abstract: Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm.

Abstract: A substrate assembly on which a first conduction-type semiconductor layer, an active layer and a second conduction-type semiconductor layer are formed is disclosed, the substrate assembly comprising a first substrate, a second substrate and a bonding layer interposed there between. In the substrate assembly, the thermal expansion coefficient of the bonding layer is smaller than or equal to that of at least one of the first and second substrates.

Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.

Abstract: A light emitting device package of the embodiment includes a body including cavities; first and second lead electrodes disposed in the cavity of the body; a light emitting device disposed in the cavities, electrically connected to at least one of the first and second lead electrodes and emitting a first main peak wavelength in the range of 410˜460 nm; and a first resin layer having first phosphor on the light emitting device, wherein the first phosphor of the first resin layer emits light of a second main peak wavelength in the range of 461 nm˜480 nm by exciting some light having the first main peak wavelength, and the first and second main peak wavelengths have the wavelength different from each other and contain the light having the same color.

Abstract: The present invention discloses a touch display device and a manufacturing method thereof, the display device comprising: an OLED display layer disposed on a lower substrate; an upper substrate; an air layer formed between the upper substrate and the lower substrate; and a touch module, disposed above the OLED display layer, wherein the touch module comprises: a first sensing circuit layer and a second sensing circuit layer, further wherein the first sensing circuit layer and the second sensing circuit layer are spaced and the distance between them is more than 2 um. The display device can reduce interference in detection circuit caused by coupling capacitance formed between the sensing circuit layers thereby improving accuracy of touch detection.

Abstract: A light emitting device package according to the embodiment includes a body having a cavity; at least one light emitting device in the cavity; a resin member filled in the cavity while covering the light emitting device; and a fluorescence sheet coupled with a top surface of the body such that the fluorescence sheet is physically separable from the top surface of the body, and including a fluorescence material for converting light emitted from the light emitting device into another light.

Abstract: An organic light emitting diode (OLED) display includes a substrate, an OLED on the substrate, and an encapsulation layer on the substrate with the OLED therebetween. The encapsulation layer includes a plurality of metal layers. Two of the plurality of metal layers are directly attached to each other.

Abstract: A light source includes a substrate arranged into at least two facing surfaces which form a seam therebetween; and a lighting device with light emitting diode (LED) chips embedded therein in a linear arrangement. The LED chips generate light photons. The lighting device has a first edge and a second edge opposite to the first edge, the light photons within the lighting device that are emitted by the LED chips from a top surface of the LED chips being output from the lighting device at the second edge of the device. The lighting device is sandwiched in the seam between the two facing surfaces, the second edge of the lighting device being exposed when the seam is in an opened position.

Abstract: The invention relates to a large area organic light emitting diode display having a uniformed luminescence throughout the display area. The invention suggests an organic light emitting diode display comprising a thin film transistor substrate including a thin film transistor, a driving current line to supply an electric signal to the thin film transistor, a driving line contact hole to expose some portions of the driving current line, and an organic light emitting diode connected to the thin film transistor; a cap including a cap substrate and an auxiliary electrode disposed on a surface of the cap substrate with an area that is at least ? of an area of the cap substrate; a conductive sealing material to electrically connect the auxiliary electrode and the driving current line through the driving line contact hole; and an organic adhesive joining the thin film transistor substrate and the cap.

Abstract: Optical conversion layers based on semiconductor nanoparticles for use in lighting devices, and lighting devices including same. In various embodiments, spherical core/shell seeded nanoparticles (SNPs) or nanorod seeded nanoparticles (RSNPs) are used to form conversion layers with superior combinations of high optical density (OD), low re-absorbance and small FRET. In some embodiments, the SNPs or RSNPs form conversion layers without a host matrix. In some embodiments, the SNPs or RSNPs are embedded in a host matrix such as polymers or silicone. The conversion layers can be made extremely thin, while exhibiting the superior combinations of optical properties.

Abstract: A method of manufacturing a multichip package structure includes: providing a substrate body; placing a plurality of light-emitting chips on the substrate body, where the light-emitting chips are electrically connected to the substrate body; surroundingly forming surrounding liquid colloid on the substrate body to surround the light-emitting chips; naturally drying an outer layer of the surrounding liquid colloid at a predetermined room temperature to form a semidrying surrounding light-reflecting frame, where the semidrying surrounding light-reflecting frame has a non-drying surrounding colloid body disposed on the substrate body and a dried surrounding colloid body totally covering the non-drying surrounding colloid body; and then forming a package colloid body on the substrate body to cover the light-emitting chips, where the semidrying surrounding light-reflecting frame contacts and surrounds the package colloid body.

Abstract: An LED module (1) includes a plurality of LEDs (76 to 89) which are arranged on a printed circuit board (75) and which each have a “bedding element” with a lens (100 to 113) with which the respective LED (76 to 89) protrudes from the printed circuit board plane. The LEDs (76 to 89) are each coupled to a light input element of an optical waveguide body and the respective associated light input element radiates the respective luminous flux from the associated LED (76 to 89) outwards from the LED module (1). To achieve a homogeneous external appearance, the printed circuit board (75) for the LEDs (76 to 89) has at least one passive LED (95, 96, 97) provided thereon.

Abstract: The invention includes one or more LED elements, a silicon substrate on which the LED elements are mounted via micro bumps and internally formed wiring is connected to the micro bumps, a heat insulation organic substrate which is stuck to the opposite side of the LED elements-mounting side of the silicon substrate and has through-holes in which the wiring goes through, a chip-mounting substrate which is stuck to the opposite side of the silicon substrate side of the heat insulation organic substrate and internally formed wiring is connected to wiring in the through-holes of the heat insulation organic substrate, and an LED control circuit chip which is connected to the wiring of the chip-mounting substrate via micro bumps, and mounted via the micro bumps on the opposite side of the heat insulation organic substrate side of the chip-mounting substrate.

Abstract: A light emitting diode (LED) device includes a substrate, first and second LED chips arranged on the substrate, and a phosphor layer over the first and second LED chips. The phosphor layer includes a plurality of phosphor units, each including a phosphor particle and a silver halide layer encapsulating the phosphor particle. Light emitted from the second LED chip strikes the phosphor particles to generate a first light, which. combines with the light to generate a resultant light. The silver halide layer is reduced by the light from the first LED chip to produce silver particles around the phosphor particles. The silver particles can block the light emitted from the second LED chip from sticking the phosphor particles. By adjusting the current supplied to the first LED chip, the color temperature of the resultant light generated by the LED device can be changed.

Abstract: A transfer-bonding method for light emitting devices including following steps is provided. A plurality of light emitting devices is formed over a first substrate and is arranged in array, wherein each of the light emitting devices includes a device layer and a sacrificial pattern sandwiched between the device layer and the first substrate. A protective layer is formed over the first substrate to selectively cover parts of the light emitting devices, and other parts of the light emitting devices are uncovered by the protective layer. The device layers uncovered by the protective layer are bonded with a second substrate. The sacrificial patterns uncovered by the protective layer are removed, so that parts of the device layers uncovered by the protective layer are separated from the first substrate and are transfer-bonded to the second substrate.

Abstract: A LED mirror light assembly comprises a body having a through hole configured subject to a predetermined shape and located on a middle part thereof, a film-coated glass configured subject to shape of the through hole and supported on a first step, a LED holder holding a plurality of light-emitting diodes, and a reflector comprising a reflective surface located on a front side thereof and facing toward the light-emitting diodes and a light-shading coating coated on a rear side thereof The reflector being kept in a non-parallel manner relative to the film-coated glass and defining with the film-coated glass a predetermined contained angle so that the light spots of the light-emitting diodes are repeatedly reflected by the reflective back face of the film-coated glass and the reflective surface of the reflector, forming a curved tunnel of light spots.

Abstract: An OLED assembly comprises a base and a planar OLED device mounted on the base. A planar light diffuser sheet is removably attached relative to the base and OLED device. A releasable attachment mechanism is operably configured between the light diffuser sheet and the base. The light diffuser sheet is oriented relative to the OLED device so as to provide a selected diffusive property to light emitted from the OLED device. The light diffuser sheet is removable from the base upon release of the attachment mechanism and can be substituted with a different light diffuser sheet. A luminaire may incorporate the OLED assembly, wherein the luminaire has fixture in which the OLED assembly is received.

Abstract: The invention provides a light emitting device. A light emitting device includes a light emitting component capable of radiating a light. A first fluorescent layer is capable of radiating a first light of a first wavelength range while being excited by the light. A second fluorescent layer is capable of radiating a second light of a second wavelength range while being excited by the light. A first fluorescent layer is between the light emitting component and the second fluorescent layer, and the first wavelength range is longer than the second wavelength range.