Patents Issued in January 31, 2013
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Publication number: 20130026615Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Inventors: Yuping Gong, Yan Xun Xue
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Publication number: 20130026616Abstract: The present invention relates to a power device package module and a manufacturing method thereof. In one aspect of the present invention, a power device package module includes: a control unit a first lead frame, a control chip and a first coupling portion that are mounted on a first substrate, wherein the first lead frame and the first coupling portion are electrically connected to the control chip, and individually molded; and a power unit including a second lead frame, a power chip and a second coupling portion that are mounted on a second substrate, wherein the second lead frame and the second coupling portion are electrically connected to the power chip, and individually molded, wherein the individually molded control unit and power unit are coupled by the first coupling portion and the second coupling portion.Type: ApplicationFiled: July 25, 2012Publication date: January 31, 2013Inventors: Suk Ho LEE, Jae Cheon DOH, Young Hoon KWAK, Tae Hoon KIM, Tao Jyun KIM, Young Ki LEE
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Publication number: 20130026617Abstract: Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.Type: ApplicationFiled: July 12, 2012Publication date: January 31, 2013Applicant: APPLIED MATERIALS, INC.Inventors: MICHAEL G. WARD, IGOR V. PEIDOUS
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Publication number: 20130026618Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate that contains a plurality of electronic components. The semiconductor device includes an interconnect structure disposed over the substrate, the interconnect structure containing a plurality of interconnect layers. The semiconductor device includes a passivation layer disposed over the interconnect structure. The semiconductor device includes an Under-Bump Metallization (UBM) layer disposed over the passivation layer, the UBM layer containing a UBM pad and a plurality of UBM devices, the UBM devices including at least one of: a UBM trace that is electrically coupled to one of the electronic components through the interconnect structure, and a dummy UBM device. The semiconductor device includes a solder bump disposed on, and electrically coupled to, the UBM pad.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Hsien-Wei Chen
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Publication number: 20130026619Abstract: The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Horng CHANG, Tin-Hao KUO, Chen-Shien CHEN, Yen-Liang LIN
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Publication number: 20130026620Abstract: The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Lin HUANG, I-Ting CHEN, Ying Ching SHIH, Po-Hao TSAI, Szu Wei LU, Jing-Cheng LIN, Shin-Puu JENG, Chen-Hua YU
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Publication number: 20130026621Abstract: A semiconductor device comprises a substrate comprising a major surface and a plurality of metal bumps on the major surface. Each of the plurality of metal bumps comprises a metal via on the major surface and a metal pillar on the metal via having an overlay offset between the metal pillar and metal via. A first metal bump of the metal bumps has a first overlay offset and a second metal bump of the metal bumps farther than the first metal bump to a centroid of the substrate has a second overlay offset greater than the first overlay offset.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Fu TSAI, Min-Feng KU, Yian-Liang KUO
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Publication number: 20130026622Abstract: A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chita CHUANG, Yao-Chun CHUANG, Tsung-Shu LIN, Chen-Cheng KUO, Chen-Shien CHEN
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Publication number: 20130026623Abstract: Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ren Chen, Ming Hung Tseng, Yi-Jen Lai
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Publication number: 20130026624Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Michael Erwin, Ian D. Melville, Ekta Misra, George John Scott
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Publication number: 20130026625Abstract: Disclosed is a flip-chip semiconductor device having isotropic electrical interconnection, primarily comprising a chip and a substrate. The chip has at least a first bump and a plurality of second bumps. The substrate has a plurality of bump pads disposed on the top surface and an isotropic connecting mechanism disposed inside the substrate consisting of a plurality of terminals electrically isolated from each other and a flexible vertical pad protruded from the top surface, wherein the disposition locations of the terminals circle around the flexible vertical pad as a disposition center. When the second bumps of the chip are bonded onto the corresponding bump pads, the first bump presses and bends the flexible vertical pad in a specific horizontal direction so that the flexible vertical pad selectively and electrically connect to a selected one of the terminals.Type: ApplicationFiled: April 18, 2012Publication date: January 31, 2013Inventor: Hian-Hang MAH
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Publication number: 20130026626Abstract: Disclosed herein are a method for forming bumps and a substrate including the bumps. The method includes: coating a solder resist on a substrate and electrodes formed on the substrate: performing laser etching treatment on the solder resist to form openings for forming bumps; printing a composition for forming bumps in the openings for forming bumps; and performing a reflowing process. The present invention can decrease the number of processes and realize a fine bump pitch of 90 ?m or less at the time of forming bumps. Further, the present invention can also decrease the number of times that alignment is performed, due to the decrease in the number of processes.Type: ApplicationFiled: June 4, 2012Publication date: January 31, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Cheol Ho CHOI, Chang Bo LEE, Chang Sup RYU
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Publication number: 20130026627Abstract: An electronic chip including a semiconductor substrate (1) covered with an insulating layer (4) including metal interconnection levels (3) and interconnection pillars (10) connected to said metal interconnection levels (3), said pillars (110) forming regions (111) protruding from the upper surface of said insulating layer (4) and capable of forming an electric contact, wherein said pillars (110) have a built-in portion (115) in a housing formed across the thickness of at least said insulating layer (4).Type: ApplicationFiled: July 20, 2012Publication date: January 31, 2013Applicant: STMicroelectronics (Crolles 2) SASInventor: Laurent-Luc Chapelon
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Publication number: 20130026628Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.Type: ApplicationFiled: October 4, 2012Publication date: January 31, 2013Applicant: STATS CHIPPAC, LTD.Inventor: STATS CHIPPAC, LTD.
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Publication number: 20130026629Abstract: An example of a semiconductor device according to the present invention includes: a protective film (1) which has an opening to expose a part of the surface of an electrode pad (4) and covers the surface of the electrode pad (4) excluding the opening; and a bump (6) which is electrically connected with the electrode pad (4) through the opening of the protective film (1) and has a part exposed outside within the area of the electrode pad (4), wherein probe marks (7) are formed by a probe brought into contact with the electrode pad (4) for electrical characteristic inspection, and the probe marks (7) are positioned within a region where the protective film (1) is formed and are covered by the protective film (1).Type: ApplicationFiled: October 5, 2012Publication date: January 31, 2013Applicant: Panasonic CorporationInventor: Panasonic Corporation
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Publication number: 20130026630Abstract: In certain embodiments, a flip chip includes a first and second solder bump. The first solder bump has a solder bump height that is greater than the second solder bump. In certain embodiments, a method includes depositing solder on an integrated circuit, reflowing the solder to create at least two solder bumps between bond pads and the integrated circuit, wherein the at least two solder bumps have different solder bump heights. A bottom layer is sized to accommodate the different solder bump heights.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Inventor: ChauChin Low
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Publication number: 20130026631Abstract: Disclosed are a semiconductor apparatus and a manufacturing method thereof. The manufacturing method of the semiconductor apparatus includes: forming a semiconductor chip on a semiconductor substrate; adhering a carrier wafer with a plurality of through holes onto the semiconductor chip; polishing the semiconductor substrate; forming a first via hole at the rear side of the polished semiconductor substrate; forming a first metal layer below the polished semiconductor substrate and at the first via hole; and removing the carrier wafer from the polished semiconductor substrate.Type: ApplicationFiled: July 16, 2012Publication date: January 31, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Byoung-Gue MIN
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Publication number: 20130026632Abstract: A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer.Type: ApplicationFiled: February 22, 2011Publication date: January 31, 2013Applicant: NEC CORPORATIONInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Kentaro Mori, Yoshiki Nakashima
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Publication number: 20130026633Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Manfred Schneegans, Jürgen Förster
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Publication number: 20130026634Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.Type: ApplicationFiled: July 26, 2011Publication date: January 31, 2013Applicant: FUJITSU LIMITEDInventors: Michael G. Lee, Chihiro Uchibori
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Publication number: 20130026635Abstract: A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: International Business Machines CorporationInventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, III, Shom Ponoth
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Publication number: 20130026636Abstract: A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.Type: ApplicationFiled: September 20, 2011Publication date: January 31, 2013Applicant: NGK Insulators, Ltd.Inventors: Makoto TANI, Takami HIRAI, Shinsuke YANO, Tsutomu NANATAKI
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Publication number: 20130026637Abstract: An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao HOU, Peng-Soon LIM, Da-Yuan LEE, Xiong-Fei YU, Chun-Yuan CHOU, Fan-Yi HSU, Jian-Hao CHEN, Kuang-Yuan HSU
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Publication number: 20130026638Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.Type: ApplicationFiled: January 30, 2012Publication date: January 31, 2013Inventors: Efren M. Lacap, Subhash Rewachand Nariani, Charles Nickel
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Publication number: 20130026639Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: ApplicationFiled: September 14, 2012Publication date: January 31, 2013Applicant: International Business Machines CorporationInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrar, Steven J. Holmes, Pushkara Varanasi
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Publication number: 20130026640Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.Type: ApplicationFiled: September 21, 2012Publication date: January 31, 2013Applicant: SEIKO EPSON CORPORATIONInventor: SEIKO EPSON CORPORATION
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Publication number: 20130026641Abstract: A conductor contact structure includes a conductor line, a dielectric layer and a contact hole. The conductor line includes a first zone and a second zone. The first zone extends along a symmetry axis and is symmetrical with respect to the symmetry axis. The second zone extends along the symmetry axis but is not symmetrical with respect to the symmetry axis. A distance between a first edge of the second zone and the symmetry axis is greater than a distance between a second edge of the second zone and the symmetry axis. A contact hole is formed in the dielectric layer and in communication with the second zone. A diameter of the contact hole is smaller than a distance between the first edge and the second edge of the second zone.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventor: Chin-Sheng YANG
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Publication number: 20130026642Abstract: An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Inventors: Kenneth Robert Rhyner, Peter R. Harper
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Publication number: 20130026643Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Luke G. England, Paul A. Silvestri, Michel Koopmans
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Publication number: 20130026644Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo
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Publication number: 20130026645Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: TESSERA, INC.Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Uzoh
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Publication number: 20130026646Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Alvin J. Joseph
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Publication number: 20130026647Abstract: A via structure includes at least a first via set and a second via set electrically connected to the first via set. There is at least one via in the first via set and at least one via in the second via set. The via in the first via set has a cross-sectional area which is larger than that of the via in the second via set.Type: ApplicationFiled: July 31, 2011Publication date: January 31, 2013Inventor: Philip J. Ireland
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Publication number: 20130026648Abstract: Disclosed is a film for forming a semiconductor protection film, which protects a surface of a semiconductor element that is mounted on a structure such as a substrate and is located on the outermost side, the surface being on the reverse side of the surface at which the semiconductor element is mounted on the structure, and the resin composition constituting the film for forming a semiconductor protection film contains (A) a thermosetting component and (B) an inorganic filler.Type: ApplicationFiled: August 5, 2010Publication date: January 31, 2013Inventors: Takashi Hirano, Masato Yoshida
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Publication number: 20130026649Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.Type: ApplicationFiled: June 18, 2012Publication date: January 31, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masashi Takenaka, Katsuyoshi Yamamoto
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Publication number: 20130026650Abstract: A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.Type: ApplicationFiled: July 24, 2012Publication date: January 31, 2013Inventors: Osamu Yamagata, Akio Katsumata, Hiroshi Inoue, Shigenori Sawachi, Satoru Itakura, Yasuhiro Yamaji
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Publication number: 20130026651Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.Type: ApplicationFiled: September 28, 2012Publication date: January 31, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventor: HYNIX SEMICONDUCTOR INC.
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Publication number: 20130026652Abstract: A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2, semiconductor chip 3a stacked on substrate 4 together with semiconductor chip 2, and having a foot print larger than semiconductor chip 2, through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2, through electrode 32 extending through semiconductor chip 3a at a position facing to through electrode 22, and conduction bump 7b arranged between through electrode 22 and through electrode 32, and conductively connecting through electrode 22 with through electrode 32.Type: ApplicationFiled: October 1, 2012Publication date: January 31, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130026653Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.Type: ApplicationFiled: March 22, 2011Publication date: January 31, 2013Applicant: NEC CORPORATIONInventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori
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Publication number: 20130026654Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.Type: ApplicationFiled: October 4, 2012Publication date: January 31, 2013Applicant: STATS CHIPPAC, LTD.Inventor: Stats ChipPac, Ltd.
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Publication number: 20130026655Abstract: A chip package structure includes a substrate in which a plurality of grooves are formed, an adhesive layer disposed on the substrate, and a plurality of chips attached to the adhesive layer. In addition, a method of fabricating the chip package structure includes forming a plurality of grooves in the substrate, dispensing a die attach material on a plurality of chip attaching regions between the plurality of grooves, and attaching a plurality of chips respectively on the plurality of chip attaching regions.Type: ApplicationFiled: April 3, 2012Publication date: January 31, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Baik-woo LEE, Hyung-jae Shin
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Publication number: 20130026656Abstract: A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.Type: ApplicationFiled: September 28, 2012Publication date: January 31, 2013Inventors: Hye-jin KIM, Byung-seo KIM, Sun-il YOUN
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Publication number: 20130026657Abstract: A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area.Type: ApplicationFiled: September 23, 2011Publication date: January 31, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wei-Chung Hsiao, Chun- Hsien Lin, Yu-Cheng Pai, Liang-Yi Hung, Ming-Chen Sun
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Publication number: 20130026658Abstract: Primarily disclosed is a wafer-level chip-scale-package (WLCSP) for wire-bonding connection. A first encapsulating layer is formed over a passivation layer of a chip. An RDL (redistribution wiring layer) is formed on the first encapsulating layer. A plurality of wire-bonding pads are stacked on the wiring terminals of the RDL on the first encapsulating layer. Each wire-bonding pad has a top surface and a sidewall. A surface plated layer completely covers the top surfaces of the wire-bonding pads. A second encapsulating layer is formed over the first encapsulating layer to encapsulate the RDL and the sidewalls of the wire-bonding pads. The openings of the second encapsulating layer are smaller than the top surfaces of the corresponding wire-bonding pads to partially encapsulate the surface plated layer. Accordingly, it can resolve the issue of die crack when wire-bonding on thinned chips.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Inventor: Yen-Ju CHEN
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Publication number: 20130026659Abstract: A method for producing a MEMS component including the steps of simultaneously embedding structure elements during producing the multi-level conductive path layer stack which structure elements are to be subsequently exposed, subsequently producing a recess that extends from a substrate backside to the multi-level conductive path layer stack, exposing the micromechanical structure elements in the multi-level conductive path layer stack through the recess. In order to increase process precision a reference mask for defining a lateral position or a lateral extension of the micromechanical structure elements to be exposed is produced, wherein the reference mask is either arranged on the substrate front side between the substrate and the multi-level conductive path layer stack or in a layer of the multi-level conductive path layer stack which layer is more proximal to the substrate than the structure element to be exposed.Type: ApplicationFiled: March 22, 2011Publication date: January 31, 2013Applicant: IHP GmbH - Innovations for High Performance MicroelectronicsInventors: Mehmet Kaynak, Bernd Tillack, Rene Scholz
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Publication number: 20130026660Abstract: A liquid epoxy resin composition for semiconductor encapsulation comprising: (A) an epoxy resin, (B) an imidazole compound, and (C) a maleimide compound, a semiconductor device encapsulated by the liquid epoxy resin composition, and an assembly in which a cured material of the liquid epoxy resin is positioned between a printed circuit substrate and a semiconductor die. The liquid epoxy resin composition provides a cured material that has an excellent adhesiveness to a semiconductor chip surface and has an excellent moisture resistance.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: NAMICS CORPORATIONInventors: Pawel CZUBAROW, Osamu Suzuki, Toshiyuki Sato, Kazuyoshi Yamada, Kaori Matsumura
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Publication number: 20130026661Abstract: A liquid epoxy resin composition for semiconductor encapsulation comprising: (A) at least one epoxy resin, (B) at least one curing accelerator and (C) at least one acid anhydride terminated polyamic acid, and an assembly in which a cured material of the liquid epoxy resin is positioned between a printed circuit substrate and semiconductor die. The liquid epoxy resin composition provides a cured material that has an excellent adhesiveness to a semiconductor chip surface and has an excellent moisture resistance.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: NAMICS CORPORATIONInventors: Pawel Czubarow, Osamu Suzuki, Toshiyuki Sato, Kazuyoshi Yamada, Kaori Matsumura
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Publication number: 20130026662Abstract: The present invention relates to an epoxy resin composition for semiconductor encapsulation, including the following components (A) to (D): (A) an epoxy resin; (B) a phenol resin; (C) an inorganic filler, and (D) a silicone compound containing an alkoxy group directly bonded to silicon atom in an amount of 10 to 45 wt % based on the entire silicone compound and having a specific gravity of 1.10 to 1.30.Type: ApplicationFiled: July 24, 2012Publication date: January 31, 2013Applicant: NITTO DENKO CORPORATIONInventors: Tomohito IWASHIGE, Tomoaki ICHIKAWA, Mitsuaki FUSUMADA, Naoya SUGIMOTO
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Publication number: 20130026663Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.Type: ApplicationFiled: July 27, 2012Publication date: January 31, 2013Applicant: SOITECInventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
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Publication number: 20130026664Abstract: A fan assembly includes a nozzle and a body on which the nozzle is mounted. The nozzle has a first air inlet, a first air outlet, and a first interior passage for conveying air from the first air inlet to the first air outlet. The nozzle also includes a second air inlet, a plurality of second air outlets, and a second interior passage for conveying air from the second air inlet to the second air outlets. The body generates a first air flow through the first interior passage and a second air flow through the second interior passage. A first air passageway conveys the first air flow to the first air inlet and a second air passageway conveys the second air flow to the second air inlet. One of the temperature, humidity, composition and electrical charge of the second air flow is changed before it is emitted from the nozzle.Type: ApplicationFiled: July 26, 2012Publication date: January 31, 2013Applicant: Dyson Technology LimitedInventors: Mark Joseph STANIFORTH, Jude Paul PULLEN