Abstract: A LED package with a Fresnel lens includes a base, a LED chip, a surrounding body and a lens. The lens is a Fresnel lens which refracts the beam of light from the LED chip to one definite direction for spotlighting the emitting light in a certain orientation.

Abstract: A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.

Abstract: An organic luminance device includes a base substrate, a organic luminance multi-layered structure and a cover substrate. Furthermore, a protective film is used to wrap the light emitting surface and at least one lateral surface of the base substrate to prevent the substrate from crack. The protective film may be doped with one or more dopants having a refractive index different from original material of the protective film.

Abstract: Disclosed are a wafer level LED package and a method of fabricating the same. The method of fabricating a wafer level LED package includes: forming a plurality of semiconductor stacks on a first substrate, each of the semiconductor stacks comprising a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active region disposed between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer; preparing a second substrate comprising first lead electrodes and second lead electrodes arranged corresponding to the plurality of semiconductor stacks; bonding the plurality of semiconductor stacks to the second substrate; and cutting the first substrate and the second substrate into a plurality of packages after the bonding is completed. Accordingly, the wafer level LED package is provided.

Abstract: A structure of a light-emitting device includes the following components: a substrate; an epitaxial structure on the substrate, the epitaxial structure including at least a first conductivity type semiconductor layer, a light-emitting active layer, and a second conductivity type semiconductor layer; a first electrode on the first conductivity type semiconductor layer; a transparent conductive layer between the first electrode and the first conductivity type semiconductor layer; and a three-dimensional distributed Bragg reflector (DBR) layer between the transparent conductive layer and the first conductivity type semiconductor layer.

Abstract: An LED package includes a substrate, an LED chip arranged on the substrate, and a light transmission layer arranged on a light output path of the LED chip. The substrate includes a first electrode and a second electrode separated and electrically insulated from the first electrode. The LED chip is electrically connected to the first electrode and the second electrode of the substrate. The light transmission layer comprises two parallel transparent plates and a fluorescent layer sandwiched between the two transparent plates. The LED package further includes a transparent encapsulation layer sealing the LED chip therein, and in one embodiment, the light transmission layer is located on the encapsulation layer and in another embodiment, the encapsulation layer also seals the light transmission layer therein. A method for manufacturing the LED package is also provided.

Abstract: The inventive concept provides light emitting devices and methods of manufacturing a light emitting device. The light emitting device may include a transparent substrate including a first region and a second region, a first transparent electrode disposed on a first surface of the transparent substrate, a second transparent electrode facing and spaced apart from the first transparent electrode, an organic light emitting layer disposed between the first and second transparent electrodes, an assistant electrode disposed between the first and second transparent electrodes and selectively masking the second region, and a light path changing structure disposed on a second surface of the transparent substrate and selectively masking the second region.

Abstract: A surface-mount light emitting device is provided comprising a light emitting element (2), a reflector (1) which is molded integral with a leadframe (11, 12) having the light emitting element mounted thereon, and an encapsulating resin composition (4). The reflector is molded from a heat curable resin composition to define a recess with bottom and side walls. The resin side wall has a thickness of 50-500 ?m. The encapsulating resin composition is a heat curable resin composition having a hardness of 30-70 Shore D units in the cured state.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer.

Abstract: A light emitting diode (LED) is provided. The LED comprises a semiconductor composite layer stacked laterally and a phosphor substrate. The phosphor substrate covers a lateral surface of the semiconductor composite layer.

Abstract: A light emitting device includes: a substrate; an n layer; an active light emitting region, a p layer; and a support portion configured to provide both mechanical support and improve light transmission disposed over a light emitting side of the device.

Abstract: A light-emitting diode housing comprising fluoropolymer is disclosed. The light-emitting diode housing supports a light-emitting diode chip and reflects at least a portion of the light emitted from the light-emitting diode chip.

Abstract: Provided is a light emitting device having strong bonding strength between the light emitting element and the wavelength converting member is provided. In the light emitting device, a light emitting element and a wavelength converting member are bonded. Particularly, the light emitting element has, from the wavelength converting member side, a first region and a second region, the wavelength converting member has, from the light emitting element side, a third region and a fourth region. The first region has an irregular atomic arrangement compared with the second region, the third region has an irregular atomic arrangement compared with the fourth region, and the first region and the third region are directly bonded.

Abstract: A waterproof transparent LED shield structure has a singular LED component with a circuit board and an LED lighting component, with the circuit board connected with protruding electric pins. A hard transparent shield has a base board and a shield. The base board covers the front side of the circuit board, and is configured with a rim to rest against the edge of the circuit board. The shield has a circular side wall and a top end and encloses the LED lighting component. A soft waterproof covering body covers and is attached to the outside of the LED component and hard transparent shield. The soft waterproof covering has a seat part and a projecting part. The seat covers the circuit board, the connecting end of the electric pins and the base board and rim, and the protruding end of the electric pins extends out of the seat part.

Abstract: A light emitting chip package includes a substrate, an insulation layer, a patterned electric conductive layer, a light emitting chip, an encapsulation, a plurality of thermal conductors and electrical conductors. The insulation layer is formed on a top surface of the substrate. The patterned electric conductive layer partially covers the insulation layer. The light emitting chip is arranged on the electric conductive layer. The encapsulation covers the light emitting chip and the electric conductive layer. The plurality of thermal conductors is formed at a bottom surface side of the substrate. The plurality of electrical conductors penetrates the insulation layer and connects the conductive layer with the thermal conductor. The plurality of electrical conductors is isolated from each other.

Abstract: Disclosed is a light emitting device module including a package body, a first lead frame and a second lead frame provided on the package body, a light emitting device electrically connected to the first lead frame and the second lead frame, a first pad and a second pad respectively formed on the lower surfaces of the first lead frame and the second lead frame, and a third pad formed on the lower surface of the package body, wherein at least one of the first pad, the second pad and the third pad includes a plurality of sub-pads.

Abstract: A non-polar light emitting diode (LED) having a photonic crystal structure and a method of fabricating the same. A non-polar LED includes a support substrate, a lower semiconductor layer positioned on the support substrate, an upper semiconductor layer positioned over the lower semiconductor layer, a non-polar active region positioned between the lower and upper semiconductor layers, and a photonic crystal structure embedded in the lower semiconductor layer. The photonic crystal structure embedded in the lower semiconductor layer may improve the light emitting efficiency by preventing the loss of light in the semiconductor layer, and the photonic crystal structure is used to improve the polarization ratio of the non-polar LED.

Abstract: A light emitting device of the present invention has a package constituted by a molded article having a light emitting face, a bottom face that is contiguous with the light emitting face, and a rear face that is on the opposite side from the light emitting face, and a pair of leads that are partially embedded in the molded article, protrude from the bottom face, and have ends that bend toward either the light emitting face or the rear face, and a light emitting element that is disposed on one of the pair of leads, the molded article has a front protruding part that protrudes on the light emitting face side, and a rear protruding part that protrudes on the rear face side, between the leads on the bottom face.

Abstract: An organic light emitting diode display includes a substrate, an organic light emitting diode on the substrate, an organic film configured to cover the organic light emitting diode on the substrate in an organic film deposition area having a first diameter, and an inorganic film configured to cover the organic film on the substrate in an inorganic film deposition area having a second diameter, wherein L1 is the first diameter of the organic film deposition area in ?m, wherein L2 is the second diameter of the inorganic film deposition area in ?m, wherein D is a thickness of the organic film in ?m, and wherein L2?L1?2 (171D+150 ?m).

Abstract: A light emitting device (10) comprises a body (11) comprising a substrate (12) of a p-type semiconductor material. The substrate has an upper surface (14) and having formed therein on one side of the upper surface and according to a bulk semi-conductor fabrication process utilizing lateral active area isolation techniques: a first n+-type island (16) to form a first junction (24) between the first island and the substrate; and a second n+-type island (18) spaced laterally from the first island (16). The substrate provides a laterally extending link (20) between the islands having an upper surface. The upper surface of the link, an upper surface of the island (16) and an upper surface of the island (18) collectively form a planar interface (21) between the body (11) and an isolation layer (19) of the device. The device comprises a terminal arrangement to apply a reverse bias to the first junction, to cause the device to emit light. The device is configured to facilitate the transmission of the emitted light.

Abstract: Methods of forming photoactive devices include infiltrating pores of a solid porous ceramic material with a fluid, which may be a supercritical fluid, carrying at least one single source precursor therein. The single source precursor may be decomposed to form a plurality of particles within the pores of the solid porous ceramic material. Photoactive devices include a solid porous ceramic material exhibiting electrical conductivity, and a plurality of photoactive semiconductor particles within pores of the solid porous ceramic material.

Abstract: An insulated gate semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to one another; a drift region, which extends in the semiconductor body and has a first type of conductivity and a first doping value; a body region having a second type of conductivity, which extends in the drift region facing the front side of the semiconductor body; a source region, which extends in the body region and has the first type of conductivity; and a buried region having the second type of conductivity, which extends in the drift region at a distance from the body region and at least partially aligned to the body region in a direction orthogonal to the front side and to the back side.

Abstract: A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer.

Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract: Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer.

Abstract: In a high-frequency circuit, it is necessary to block galvanically between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. Among these MIM capacitors, one coupled to the external terminal is easily affected by static electricity from outside, which easily causes a problem of electro-static breakdown or the like. The present invention is a semiconductor integrated circuit device formed over a semi-insulating compound semiconductor substrate in which a first electrode of an MIM capacitor electrically coupled to an external pad is electrically coupled to the semi-insulating compound semiconductor substrate, and on the other side, a second electrode of the MIM capacitor is electrically coupled to the semi-insulating compound semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film.

Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.

Abstract: A method for forming a neutron detector comprises thinning a backside silicon substrate of a radiation detector; and forming a neutron converter layer on the thinned backside silicon substrate of the radiation detector to form the neutron detector. The neutron converter layer comprises one of boron-10 (10B), lithium-6 (6Li), helium-3 (3He), and gadolinium-157 (157Gd).

Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.

Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench including an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer including nitrogen or carbon.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line and a processor based system with such an imaging device. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.

Abstract: An image sensor includes front-side and backside photodetectors of a first conductivity type disposed in a substrate layer of the first conductivity type. A front-side pinning layer of a second conductivity type is connected to a first contact. The first contact receives a predetermined potential. A backside pinning layer of the second conductivity type is connected to a second contact. The second contact receives an adjustable and programmable potential.

Abstract: A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is formed in the peripheral circuit area and connected to the dummy capacitor group in parallel. Capacitance of the dummy capacitor group may be greater than that of the MOS capacitor.

Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.

Abstract: A semiconductor integrated circuit including a large capacity reservoir capacitor to provide suitable power is provided. The semiconductor integrated circuit includes a semiconductor substrate in which a cell area and a peripheral circuit area are defined, a MOS capacitor formed on the semiconductor substrate corresponding to the peripheral circuit area, and a dummy capacitor group formed on the peripheral circuit area to overlap the MOS capacitor. One electrode of the MOS capacitor and one electrode of the dummy capacitor group are connected to each other and the other electrode of the MOS capacitor and the other electrode of the dummy capacitor group are connected to difference voltage sources from each other.

Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

Abstract: Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell.

Abstract: A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are adjacent to each other and formed on the first dielectric layer. Each data storage unit includes at least two floating gates formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and between the two floating gates, an inter-gate dielectric layer formed on the two floating gates and the second dielectric layer, at least one control gate formed on the inter-gate dielectric layer, and a third dielectric layer formed on the first dielectric layer and surrounding and tightly connecting with the two floating gates, the inter-gate dielectric layer, and the control gate.

Abstract: A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of floating gate electrodes is formed to have a width of an upper portion thereof in a channel width direction which is smaller than a width of a lower portion thereof in the channel width direction and one of contact surfaces thereof on at least opposed sides which contact the second insulating film is formed to have one surface, and the second insulating film has a maximum film thickness in a vertical direction, the maximum film thickness being set smaller than a distance from a lowest surface to a highest surface of the second insulating film in the vertical direction.

Abstract: A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.

Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.

Abstract: The semiconductor device includes an insulating substrate, a channel layer over the insulating substrate, a gate at least partially extending from an upper surface of the channel layer into the channel layer, a source and a drain respectively at opposing sides of the gate on the channel layer, a gate insulating layer surrounding, the gate and electrically insulating the gate from the channel layer, the source, and the drain, and a variable resistance material layer between the insulating substrate and the gate.

Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and bodies (252). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Abstract: A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

Abstract: A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface.

Abstract: Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.

Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.

Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.