Abstract: The present invention provides a technique capable of realizing a silicon carbide semiconductor device having high performance and high reliability. By constituting a channel region by an n?-type, intrinsic, or p?-type channel region and a p+-type channel region, a high channel mobility and a high threshold voltage are realized. Further, by constituting a source region by an n+-type source region and an n++-type source region, and forming the n+-type source region between the p+-type channel region and the n++-type source region, an electric field in the p+-type channel region is relaxed to suppress deterioration of a gate insulating film, and also by electrically connecting a source wiring electrode to the n++-type source region, a contact resistance is decreased.

Abstract: An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected, second connecting wirings (642, 644, 646) connected to gate terminals (51) to which extraction wirings (612, 614, 616) are connected, bundled wirings (651 to 654) each composed of a mutually adjacent first connecting wiring and second connecting wiring bundled together, a first inspection wiring (66) capable of inputting an inspection signal to bundled wirings (652, 654) that are not adjacent to each other among the bundled wirings, and a second inspection wiring (67) capable of inputting an inspection signal to bundled wirings (651, 653) that are not adjacent to each other and not connected to the first inspection wiring (66) among the bundled wirings.

Abstract: A lighting device includes first and second light emission units. The first light emission unit emits light having a relatively low color temperature and a high feeling of contrast index. The second light emission unit emits light having a relatively high S/P ratio, which is the ratio of scotopic luminance to photopic luminance. The first light emission unit illuminates a region located at a vertical upper side of a region illuminated by the second light emission unit.

Abstract: The present invention provides a substrate for an optical semiconductor apparatus for mounting optical semiconductor devices, the substrate comprising first leads to be electrically connected to first electrodes of the optical semiconductor devices and second leads to be electrically connected to second electrodes of the optical semiconductor devices, wherein the first leads and the second leads are arranged each in parallel, a molded body of a thermosetting resin composition is molded by injection molding in a penetrating gap between the first leads and the second leads such that the substrate is formed in a plate shape, and an exposed front surface and an exposed back surface of the first leads, the second leads and the resin molded body each tie in a same plane. The substrate exhibits excellent heat dissipation properties and enables manufacture of a thin optical semiconductor apparatus with a low cost.

Abstract: A method for fabricating a high voltage light emitting diode (HV LED) includes: calculating a total area of the HV LED according to a predetermined light emission luminance; calculating the number of sub-LEDs according to a predetermined operating voltage; subtracting, from the total area, areas of isolation trenches between the sub-LEDs, electrode areas and areas of series-connected conductive leads between the sub-LEDs, and then dividing the difference obtained through the subtraction by the number of the sub-LEDs, so as to calculate an effective light emission area of each of the sub-LEDs; and according to the effective light emission area, adjusting the area of a sub-LED having an electrode and the area of a sub-LED having no electrode, so as to enable the area of the sub-LED having an electrode to be greater than the area of the sub-LED having no electrode. An HV LED manufactured by the above method.

Abstract: A light emitting device according to an embodiment includes a body including first and second side walls which correspond to each other, third and fourth side walls which have lengths longer than lengths of the first and second side walls, and a concave portion; a first lead frame under the concave portion and the third side wall; a second lead frame under the concave portion and the fourth side wall; a light emitting chip on at least one of the first and second lead frames; a molding member on the concave portion; a first recess portion recessed from the first side wall toward the second side wall and connected to a bottom of the body; and a second recess portion recessed from the second side wall toward the first side wall and connected to the bottom of the body.

Abstract: An optical emitter is fabricated by bonding a Light-Emitting Diode (LED) die to a package wafer, electrically connecting the LED die and the package wafer, forming a phosphor coating over the LED die on the package wafer, molding a lens over the LED die on the package wafer, molding a reflector on the package wafer, and dicing the wafer into at least one optical emitter.

Abstract: A luminous glazing unit including at least one substrate formed by a transparent glazing element; at least one light source; and at least one light extraction device for extracting the light, the extraction device being arranged to create a luminous region, the extraction device being formed by at least one fibrous layer.

Abstract: A light-emitting device includes at least one first light-emitting semiconductor component, which radiates red light during operation, at least one second light-emitting semiconductor component having a wavelength conversion element, and at least one third light-emitting semiconductor component having a wavelength conversion element. The second and third light-emitting semiconductor components each radiate blue primary light and converted secondary light and the respective superposition of the primary light and the secondary light of the second and third light-emitting semiconductor components has different chromaticity coordinates.

Abstract: A light emitting device includes an active layer configured to provide light emission due to carrier recombination therein, a surface on the active layer, and an electrically conductive contact structure on the surface. The contact structure includes at least one plated contact layer. The contact structure may include a sublayer that conforms to the surface roughness of the underlying surface, and the plated contact layer may be substantially free of the surface roughness of the underlying surface. The surface of the plated contact layer may be substantially planar and/or otherwise configured to reflect the light emission from the active layer. Related fabrication methods are also discussed.

Abstract: The present invention provides a substrate for an optical semiconductor apparatus for mounting optical semiconductor devices, the substrate includes first leads to be electrically connected to first electrodes of the optical semiconductor devices and second leads to be electrically connected to second electrodes of the optical semiconductor devices, wherein the first leads and the second leads are arranged each in parallel, a molded body of a thermosetting resin composition is molded in a penetrating gap between the first leads and the second leads, a reflector of the thermosetting resin composition is molded at a periphery of respective regions on which the optical semiconductor devices are to be mounted, and the resin molded body and the reflector are integrally molded with the first leads and the second leads by injection molding.

Abstract: A semiconductor light-emitting device includes a substrate, an LED chip mounted on the substrate, and a resin package covering the LED chip. The substrate includes a base and a wiring pattern formed on the base. The resin package includes a lens. The base includes an upper surface, a lower surface and a side surface extending between the upper surface and the lower surface. The LED chip is mounted on the upper surface of the base. The side surface of the base is oriented in a lateral direction. The wiring pattern includes a pair of first mount portions and a pair of second mount portions. The paired first mount portions are formed on the lower surface of the base. The paired second mount portions are oriented in the lateral direction and offset from the side surface of the base in the lateral direction.

Abstract: A light emitting diode (LED) structure, a LED device and methods for forming the same are provided. The LED structure comprises a LED wafer; and a phosphor layer having a flat surface and formed above a light emitting surface of the LED wafer, in which the phosphor layer is formed by centrifugal spin coating.

Abstract: A method for manufacturing a ceramic luminescence conversion element includes providing a shaped body having a first main surface, a second main surface and a first lateral surface. The shaped body includes a ceramic material and a luminescence conversion substance. The first main surface and/or the second main surface of the shaped body is/are machined using a patterning method, so that at least one first machined area and at least one unmachined area are formed. The first machined area extends essentially parallel to the first lateral surface. Singularization is performed to produce a plurality of luminescence conversion elements by means of cuts that are made in the machined main surface of the machined shaped body essentially at right angles to the first lateral surface.

Abstract: An LED structure include a substrate, a light-emitting structure disposed on the substrate, at least one surface plasmon (SP) structure, and a first and a second electrodes. The light-emitting structure has a first electrical type semiconductor layer, an active layer, a second electrical type semiconductor layer, and a first conductive layer sequentially stacked. The active layer is located at a first portion of the first electrical type semiconductor layer and exposed from a second portion of the first electrical type semiconductor layer. The first and the second electrical type semiconductor layer have different electrical types. The SP structure is concavely disposed in the first conductive layer and the second electrical type semiconductor layer. The first and the second electrodes are disposed on the second portion of the first electrical type semiconductor layer and the first conductive layer, respectively. A method for manufacturing the above LED structure.

Abstract: According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer and a second insulating layer. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided on the second surface in a region including the light emitting layer. The n-side electrode is provided on the second surface in a region not including the light emitting layer. The p-side interconnect layer includes a p-side external terminal exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface. The n-side interconnect layer includes an n-side external terminal exposed from the second insulating layer at the third surface.

Abstract: The invention relates to a LED assembly comprising a light scattering layer provided between the phosphor layer of the LED and a filter layer.

Abstract: An exemplary light-emitting diode (LED) includes a substrate, a first electrode and a second electrode sandwiching the substrate therebetween, an LED chip electrically connected to the first electrode and the second electrode, a reflector located on the first electrode and the second electrode and surrounding the LED chip, and a first retaining wall mounted on an edge of the first electrode and a second retaining wall mounted on an edge of the second electrode. The first retaining wall and the second retaining wall are made of conductive material. The first retaining wall and the second retaining wall are at a same side of the LED. Outer surfaces of the first retaining wall and the second retaining wall are exposed out of the reflector.

Abstract: A light-emitting diode chip includes at least two semiconductor bodies, each semiconductor body including at least one active area that generates radiation, a carrier having a top side and an underside facing away from the top side, and an electrically insulating connector arranged at the top side of the carrier, wherein the electrically insulating connector is arranged between the semiconductor bodies and the top side of the carrier, the electrically insulating connector imparts a mechanical contact between the semiconductor bodies and the carrier, and at least some of the semiconductor bodies electrically connect in series with one another.

Abstract: Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.

Abstract: A light-emitting module includes a light-emitting diode package structure and an insulating support structure. The light-emitting diode package structure includes a package base and at least two leads. The package base has a first surface, and each lead has a bonding surface. The insulating support structure has a second surface and a third surface opposite to each other, and the insulating support structure is disposed under the package base, so that the first surface is in contact with the second surface. The bonding surfaces and the third surface are located in different planes.

Abstract: A light emitting device is provided. A light emitting device that includes a substrate, a first electrode, a passivation layer, a second electrode, and a light emitting layer is provided. The first electrode is disposed on the substrate and includes a first patterned conductive layer. The first patterned conductive layer includes an alloy containing a first metal and a second metal. The passivation layer is at least disposed on a side surface of the first electrode and includes a compound of the second metal. Here, a work function of the compound of the second metal ranges from about 4.8 to about 5.5. The second electrode is disposed on the first electrode. The light emitting layer is disposed between the first electrode and the second electrode.

Abstract: Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

Abstract: CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region.

Abstract: A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

Abstract: According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.

Abstract: Spin transistors and related memory, memory systems, and methods are disclosed. A spin transistor is provided by at least two magnetic tunnel junctions (MTJs) with a shared multiferroic layer. The multiferroic layer is formed from a piezoelectric (PE) thin film over a ferromagnetic thin film (FM channel) with a metal electrode (metal). The ferromagnetic layer functions as the spin channel and the piezoelectric layer is used for transferring piezoelectric stress to control the spin state of the channel. The MTJ on one side of the shared layer forms a source and the MTJ on the other side is a drain for the spin transistor.

Abstract: A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

Abstract: A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area having source and drain regions. The first and second trench isolations extend parallel to each other. The line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area and is formed in the substrate adjacent to the first trench isolation defining a first segment of the active area with the first trench isolation. The second word line extends across the active area and is formed in the substrate adjacent to the second trench isolation defining a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.

Abstract: A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.

Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

Abstract: A solid-state imaging device that includes a pixel including a photoelectric conversion section, and a conversion section that converts an electric charge generated by photoelectric conversion into a pixel signal. In the solid-state imaging device, substantially only a gate insulation film is formed on a substrate corresponding to an area under a gate electrode of at least one transistor in the pixel.

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Abstract: A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material.

Abstract: A semiconductor device includes: a second transistor having a second conductive type formed on a first well region having a first conductive type; a first transistor having a first conductive type formed on a second well region having a second conductive type; a first well guard ring having the first conductive type, the first well guard ring including at least a first portion formed between the first transistor and the second transistor; a second well guard ring having the first conductive type, the second well guard ring including at least a first portion formed between the first transistor and the second transistor; and a first capacitor formed on at least one of the first well region and the second well region, and located between the first portion of the first well guard ring and the first portion of the second well guard ring.

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.

Abstract: Some embodiments include memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric material and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. Some embodiments include methods of storing information. A memory cell to is provided which has a channel-supporting material, a dielectric material over the channel-supporting material, a carrier-trapping material over the dielectric material, and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. It is determined if carriers are trapped in the carrier-trapping material to thereby ascertain a memory state of the memory cell.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.

Abstract: A superjunction device in which corner portions of each annular-shaped second trench are composed of a plurality of alternately arranged first sides and second sides. The first sides are parallel to a plurality of parallel arranged first trenches in a current-flowing area, while the second sides are perpendicular to the first sides and the first trenches. Such design ensures that Miller indices of sidewalls and bottom face of any portion of each second trench belong to the same family of crystal planes. Moreover, with this design, the corner portions of the second trenches can be filled with a silicon epitaxial material at the same rate with the rest portions thereof, which ensures for the second trenches to be uniformly and completely filled without any defects in the corner portions and hence improve the performance of the superjunction device.

Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer.

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.