Abstract: The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this.

Abstract: Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.

Abstract: A trench MOSFET comprising a plurality of trenched gates surrounded by source regions encompassed in body regions in active area. A plurality of trenched source-body contact structure penetrating through the source regions and extending into the body regions, are filled with tungsten plugs padded with a Ti layer, a first and a second TiN layer, wherein the second TiN layer is deposited after Ti silicide formation to avoid W spiking occurrence.

Abstract: A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

Abstract: The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends along a length (i.e., the larger dimension of the butted contact) from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.

Abstract: A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer.

Abstract: A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.

Abstract: A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure positioned on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure positioned on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure.

Abstract: The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in which a plasma, preferably a microplasma, cooperates with conventional solid state semiconductor device regions to influence or perform a semiconducting function, such as that provided by a transistor. The invention provides a family of hybrid plasma electronic/photonic devices having properties previously unavailable. In transistor devices of the invention, a low temperature, glow discharge is integral to the hybrid transistor. Example preferred devices include hybrid BJT and MOSFET devices.

Abstract: A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.

Abstract: An isolation structure prevents inter-device and intra-device leakage in first and second adjacent semiconductor devices in a substrate. The first and second semiconductor devices each include a gate region and at least one active region. A first channel stop region is configured to surround the first semiconductor device. A second channel stop region is configured to surround the second semiconductor device. A first field plate is located above at least part of the first channel stop region, and overlaps the gate region of the first semiconductor device in a first overlap region. A second field plate is located above at least part of the second channel stop region, and overlaps the gate region of the second semiconductor device in a second overlap region.

Abstract: A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO2, ZrO2, Ta2O5, TiO2, SrTiO3 and (Ba,Sr)TiO3, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer.

Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

Abstract: An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

Abstract: The present invention discloses a semiconductor device, comprising a substrate, a gate stack structure on the substrate, a gate spacer structure at both sides of the gate stack structure, source/drain regions in the substrate and at opposite sides of the gate stack structure and the gate spacer structure, characterized in that the gate spacer structure comprises at least one gate spacer void filled with air. In accordance with the semiconductor device and the method for manufacturing the same of the present invention, carbon-based materials are used to form a sacrificial spacer, and at least one air void is formed after removing the sacrificial spacer, the overall dielectric constant of the spacer is effectively reduced. Thus, the gate parasitic capacitance is reduced and the device performance is enhanced.

Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.

Abstract: Integrated circuits and methods of fabricating integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit includes depositing a layer of a high-k dielectric material; depositing a layer of a work function shifter material over a portion of the high-k dielectric material to form an overlapping region; heat treating the layer of the high-k dielectric material and the layer of the work function shifter material to as to form a transformed dielectric material via thermal diffusion that is a combination of the high-k dielectric and work function shifter materials in the overlapping region; and depositing a layer of a first replacement gate fill material to obtain multiple threshold voltages.

Abstract: A micromechanical acceleration sensor includes a seismic mass and a substrate that has a reference electrode. The seismic mass is deflectable in a direction perpendicular to the reference electrode, and the seismic mass has a flexible stop in the deflection direction. The flexible stop of the seismic mass includes an elastic layer.

Abstract: A component system includes at least one MEMS element, a cap for a micromechanical structure of the MEMS element, and at least one ASIC substrate. The micromechanical structure of the MEMS element is implemented in the functional layer of an SOI wafer. The MEMS element is mounted face down, with the structured functional layer on the ASIC substrate, and the cap is implemented in the substrate of the SOI wafer. The ASIC substrate includes a starting substrate provided with a layered structure on both sides. At least one circuit level is implemented in each case both in the MEMS-side layered structure and in the rear-side layered structure of the ASIC substrate. In the ASIC substrate, at least one ASIC through contact is implemented which electrically contacts at least one circuit level of the rear-side layered structure and/or at least one circuit level of the MEMS-side layered structure.

Abstract: A micromechanical inertial sensor includes an ASIC element having a processed front side, an MEMS element having a micromechanical sensor structure, and a cap wafer mounted above the micromechanical sensor structure, which sensor structure includes a seismic mass and extends over the entire thickness of the MEMS substrate. The MEMS element is mounted on the processed front side of the ASIC element above a standoff structure and is electrically connected to the ASIC element via through-contacts in the MEMS substrate and in adjacent supports of the standoff structure. A blind hole is formed in the MEMS substrate in the area of the seismic mass, which blind hole is filled with the same electrically conductive material as the through-contacts, the conductive material having a greater density than the MEMS substrate.

Abstract: The present invention generally relates to methods for producing MEMS or NEMS devices and the devices themselves. A thin layer of a material having a lower recombination coefficient as compared to the cantilever structure may be deposited over the cantilever structure, the RF electrode and the pull-off electrode. The thin layer permits the etching gas introduced to the cavity to decrease the overall etchant recombination rate within the cavity and thus, increase the etching rate of the sacrificial material within the cavity. The etchant itself may be introduced through an opening in the encapsulating layer that is linearly aligned with the anchor portion of the cantilever structure so that the topmost layer of sacrificial material is etched first. Thereafter, sealing material may seal the cavity and extend into the cavity all the way to the anchor portion to provide additional strength to the anchor portion.

Abstract: Measures are proposed by which the design freedom is significantly increased in the case of the implementation of the micromechanical structure of the MEMS element of a component, which includes a carrier for the MEMS element and a cap for the micromechanical structure of the MEMS element, the MEMS element being mounted on the carrier via a standoff structure. The MEMS element is implemented in a layered structure, and the micromechanical structure of the MEMS element extends over at least two functional layers of this layered structure, which are separated from one another by at least one intermediate layer.

Abstract: A hybridly integrated component includes an ASIC element having a processed front side, a first MEMS element having a micromechanical structure extending over the entire thickness of the first MEMS substrate, and a first cap wafer mounted over the micromechanical structure of the first MEMS element. At least one structural element of the micromechanical structure of the first MEMS element is deflectable, and the first MEMS element is mounted on the processed front side of the ASIC element such that a gap exists between the micromechanical structure and the ASIC element. A second MEMS element is mounted on the rear side of the ASIC element. The micromechanical structure of the second MEMS element extends over the entire thickness of the second MEMS substrate and includes at least one deflectable structural element.

Abstract: A magnetoresistive element includes a first magnetic layer having an axis of magnetization perpendicular to the film surface and a fixed magnetization orientation; a second magnetic layer having an axis of magnetization perpendicular to the film surface and a changeable magnetization orientation; a first nonmagnetic layer arranged between the first and second magnetic layers; and a third magnetic layer having an axis of magnetization perpendicular to the film surface and a fixed magnetization orientation opposite that of the first magnetic layer. The first magnetic layer has a first magnetic material film in contact with the first nonmagnetic layer, a nonmagnetic material film in contact with the first magnetic material film, and a second magnetic material film containing Co100-xWx (0<x<40 at %) and in contact with the nonmagnetic material film. As current flows via the nonmagnetic layer, the magnetization orientation of the second magnetic layer changes.

Abstract: An integrated magnetoresistive device, where a substrate of semiconductor material is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends in the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material including at least one arm, extending in a transversal direction to the sensitivity plane and vertically offset to the magnetoresistor. In this way, magnetic flux lines directed perpendicularly to the sensitivity plane are concentrated and deflected so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract: An embodiment method for forming an image sensor includes forming an anti-reflective coating over a surface of a semiconductor supporting a photodiode, forming an etching stop layer over the anti-reflective coating, forming a buffer oxide over the etching stop layer, and selectively removing a portion of the buffer oxide through etching, the etching stop layer protecting the anti-reflective coating during the etching. An embodiment image sensor includes a semiconductor disposed in an array region and in a periphery region, the semiconductor supporting a photodiode in the array region, an anti-reflective coating disposed over a surface of the semiconductor, an etching stop layer disposed over the anti-reflective coating, a thickness of the etching stop layer over the photodiode in the array region less than a thickness of the etching stop layer in the periphery region, and a buffer oxide disposed over the etching stop layer in the periphery region.

Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

Abstract: In general, the invention relates to a unit that includes a semiconductor and a plasmonic material disposed on the semiconductor, where a potential barrier is formed between the plasmonic material and the semiconductor. The unit further includes an insulator disposed on the semiconductor and adjacent to the plasmonic material and a transparent conductor disposed on the plasmonic material, where, upon illumination, the plasmonic material is excited resulting the excitation of an electron with sufficient energy to overcome the potential barrier.

Abstract: A pixel and pixel array for use in an image sensor are provided. The image sensor includes floating sensing nodes symmetrically arranged with respect to a photodiode in each pixel.

Abstract: A method for manufacturing an image sensor may include at least one of the following steps. Forming at least one device isolation layer that passes through an epitaxial layer in a semiconductor substrate to isolate pixel regions. Forming a light-receiving element in each pixel region. The method may include forming a transistor in the active region of the semiconductor substrate partitioned by the device isolation layer.

Abstract: An avalanche photodiode includes a substrate; an avalanche multiplying layer, a p-type electric field controlling layer, a light-absorbing layer, and a window layer sequentially laminated on the substrate. A p-type region is present in parts of the window layer and the light-absorbing layer. Carbon is the dopant of the electric field controlling layer. Zn is the dopant of the p-type region. A bottom face of the p-type region is closer to the substrate than is an interface between the light-absorbing layer and the window layer.

Abstract: A method and apparatus for reducing external series resistance (Rext) has been becoming a more dominant component of the total series resistance between the MOSFET source and drain. A significant part of Rext (25-35%) comes from the interface resistance (RC) between the metal (silicide) and source/drain (S/D) silicon diffusion regions. RC is determined by the specific contact resistivity (?c) at the silicide/silicon interface, the S/D silicon sheet resistivity at the silicide/silicon interface (RS/D), and the contact length (LC). The LC has been and will be decreasing by about 30% from one CMOS technology node to the next, resulting in increased RC and Rext. To maintain or reduce RC with respect to state-of-the-art value, one must reduce ?c. This may be accomplished using a metal-dopant alloy having a dopant material that can diffuse into the semiconductor layer during annealing to provide contact and ultralow resistance at the interface.

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract: Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.

Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

Abstract: An inductor is provided. The inductor includes first and second bonding pads on a semiconductor substrate, a lead pin on a board trace, a first bonding wire being configured to connect the first bonding pad and the lead pin, and a second bonding wire configured to connect the second bonding pad and the lead pin, the second bonding wire being connected to the first bonding wire in parallel.

Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.

Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.

Abstract: Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.

Abstract: A technique is provided for a structure. A substrate has a nanopillar vertically positioned on the substrate. A bottom layer is formed beneath the substrate. A top layer is formed on top of the substrate and on top of the nanopillar, and a cover layer covers the top layer and the nanopillar. A window is formed through the bottom layer and formed through the substrate, and the window ends at the top layer. A nanopore is formed through the top layer by removing the cover layer and the nanopillar.

Abstract: A method that includes, in the sequence set forth, (1) temporarily fixing a substrate onto a support via a temporary fixing material including a central section (A) having two or more layers and a peripheral section (B) with solvent resistance, section (B) being in contact with a peripheral portion of the support on the substrate side and with a peripheral portion of the substrate on the support side, section (A) being in contact with a central portion of the support on the substrate side and with a central portion of the substrate on the support side, the temporary fixing thus resulting in a stack in which section (A) is covered with the support, section (B) and the substrate; (2) processing the substrate and/or transporting the stack; (3) dissolving section (B) with a solvent; and (4) heating the residue of the temporary fixing material and separating the substrate from the support.

Abstract: A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test structure is probed, and then a passivation layer overlying the surface of the wafer is formed, the passivation layer overlying the plurality of bond pads and overlying the test structure. Openings in the regions of the passivation layer overlying the plurality of bond pads are then formed to expose the plurality of bond pads while retaining the regions of the passivation layer overlying the test structure until singulation of the wafer. Pad metallizations are formed at the plurality of bond pads via the openings in the regions of the passivation layer and the wafer is singulated. The resulting dies may be packaged and the resulting IC packages may be implemented in electronic devices.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.