Abstract: An aromatic amine derivative having a specific structure. An organic electroluminescence device which is composed of one or more organic thin film layers sandwiched between a cathode and an anode, wherein at least one of the organic thin film layers, especially a hole transporting layer, contains the aromatic amine derivative. The aromatic amine derivative has at least one substituted or unsubstituted dibenzofuran skeleton and at least one substituted or unsubstituted terphenylene skeleton. Because the molecules in the aromatic amine derivate hardly crystallize, organic electroluminescence devices improving their production yield and having prolonged lifetime are provided.

Abstract: A thin film transistor and a manufacturing method thereof. The thin film transistor includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a first semiconductor disposed on the gate insulating layer; a second semiconductor disposed on the first semiconductor and having a different plane shape from the first semiconductor; and a source electrode and a drain electrode that are disposed on the second semiconductor and face each other.

Abstract: A thin film transistor substrate including a base substrate; an active pattern disposed on the base substrate and including a source electrode, a drain electrode, and a channel including an oxide semiconductor disposed between the source electrode and the drain electrode; a gate insulation pattern disposed on the active pattern; a gate electrode disposed on the gate insulation pattern and overlapping with the channel; and a light-blocking pattern disposed between the base substrate and the active pattern.

Abstract: Embodiments of the invention provide an oxide TFT and a manufacturing method thereof. The oxide thin film transistor comprises: a substrate; a gate electrode formed on the substrate; a gate insulation layer covering the gate electrode; an oxide active layer formed on the gate insulation layer and comprising a source region, a drain region, and a channel between the source region and the drain region; an etching barrier layer entirely covering the active layer and the gate insulation layer; and a source electrode and a drain electrode formed on the etching barrier layer and respectively provided on both sides of the channel. The etching barrier layer is a metal layer. The oxide thin film transistor further comprises a channel protective layer, which is a non-conductive oxidation layer converted from the metal layer by performing an oxidation treatment on the metal layer.

Abstract: According to embodiments of the invention, a thin film transistor (TFT), a manufacturing method of the TFT, an array substrate and a display device are provided. The manufacturing method of the TFT comprises: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate formed with the gate electrode; forming an oxide semiconductor active layer, an etch stop layer and a source/drain electrode on the gate insulating layer, wherein the etch stop layer is obtained by an oxidation treatment.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. In the manufacturing method, the needed patterns can be formed by just three photolithography processes, wherein the semiconductor layer and the etch stop layer are formed by just one photolithography process. The method reduces one photolithography process compared to the method of the state of the art, which forms the pattern of the semiconductor layer and the etch stop layer by two photolithography processes respectively, thereby greatly reducing the manufacturing cost and improving the production efficiency.

Abstract: A semiconductor device having a high aperture ratio, including a capacitor with increased capacitance, and consuming low power is provided. The semiconductor device includes pixels defined by x (x is an integer of 2 or more) scan lines and y (y is an integer of 1 or more) signal lines, and each of the pixels includes a transistor, and a capacitor. The transistor includes a semiconductor film having a light-transmitting property. The capacitor includes a dielectric film between a pair of electrodes. In the capacitor between an (m?1)-th (m is an integer of 2 or more and x or less) scan line and an m-th scan line, a semiconductor film on the same surface as the semiconductor film having a light-transmitting property of the transistor serves as one of the pair of electrodes and is electrically connected to the (m?1)-th scan line.

Abstract: An electronic device of the type wherein a semiconductor stack is functionally supported by interconnects, electrical contacts and dielectric materials. The interconnects and electrical contacts are composed of iridium, ruthenium, zirconium, niobium, tantalum, rhodium, chromium, nickel, palladium, osmium, platinum, titanium, silver and their alloys. The dielectric materials are formed of mixtures of titanium oxide, zirconium oxide, iridium oxide, silver oxide, ruthenium oxide, and niobium oxide.

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract: One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal.

Abstract: Test dies having metrology test structures and methods of manufacture are disclosed. The method includes forming one or more metrology test structures in a test die that are identical to one or more structures formed in an adjacent product chip.

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Abstract: A semiconductor device includes an AC coupling element, and a temperature monitoring unit that outputs a temperature monitor signal, the temperature monitoring unit has a first temperature monitoring element that outputs the temperature monitor signal, and the first temperature monitoring element is arranged in a region immediately below or a region adjacent to the AC coupling element.

Abstract: An SJ-MOSFET can include an active region serving as a main current path and a temperature detection region including a temperature detecting diode. Main SJ cells in which n drift regions and p partition regions are alternately adjacent to each other are arranged in a drift layer in the active region. The temperature detection region is provided in the active region. Fine SJ cells in which n drift regions and p partition regions are alternately bonded to each other at a pitch less than that of the n drift region and the p partition region of the main SJ cell are arranged in the drift layer in the temperature detection region. The temperature detecting diode is formed above the fine SJ cells with an insulating film) interposed therebetween. The temperature detecting diode includes a p+ anode region and an n+ cathode region.

Abstract: A thin film transistor (TFT) array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method comprises: forming a first passivation layer (8) on a substrate (1), and forming a board wiring PAD-region via hole (11) in the first passivation layer (8) above the board wiring PAD region (11) through a first patterning process; forming a second passivation layer (16) on the substrate (1) formed with the board wiring PAD-region via hole (11), and forming a pixel-region via hole (15) in the first passivation layer (8) and the second passivation layer (16) above the display electrode (7) through a second patterning process in such a way that the pixel-region via hole (15) has a top-size smaller than its bottom-size; and applying a transparent conductive layer on the substrate (1) formed with the pixel-region via hole (15) to form a second display electrode.

Abstract: Embodiments of the invention provide an array substrate and a display device. The array substrate comprises a common electrode and a pixel electrode that are formed on a base substrate. The common electrode comprises a first common electrode and a second common electrode, the first common electrode is provided below the pixel electrode and separated from the pixel electrode by an insulating layer, the second common electrode is provided in the same layer as the pixel electrode. The pixel electrode comprises a plurality of strip electrodes, the second common electrode also comprises a plurality of strip electrodes, and the strip electrodes of the pixel electrode and the strip electrodes of the second common electrode are alternately arranged.

Abstract: According to an embodiment of a field-effect semiconductor device, the field-effect semiconductor device includes a semiconductor body and a source electrode. The semiconductor body includes a drift region, a gate region and a source region of a first semiconductor material having a first band-gap and an anode region of a second semiconductor material having a second band-gap lower than the first band-gap. The drift region is of a first conductivity type. The gate region forms a pn-junction with the drift region. The source region is of the first conductivity type and in resistive electric connection with the drift region and has a higher maximum doping concentration than the drift region. The anode region is of the second conductivity type, forms a heterojunction with the drift region and is spaced apart from the source region. The source metallization is in resistive electric connection with the source region and the anode region.

Abstract: A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A semiconductor layer has a third pattern. A source/drain includes a second electrically conductive layer stack.

Abstract: A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A third inorganic thin film dielectric layer has a third pattern. A semiconductor layer is in contact with and has the same pattern as the third inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack.

Abstract: An electronic device is presented, such as a thin film transistor. The device comprises a patterned electrically-conductive layer associated with an active element of the electronic device. The electrically-conductive layer has a pattern defining an array of spaced-apart electrically conductive regions. This technique allows for increasing an electric current through the device.

Abstract: An electrophoretic display device includes a photosensitive transistor in a thin-film-transistor layer that may be used to receive an optical signal as input control signal. The thin-film-transistor layer also includes an electrical switch element for driving an electrophoretic layer to display content. A switching transistor may also be included in the thin-film-transistor layer for selectively turning on the photosensitive transistor. By incorporating the photosensitive transistor and the switching transistor into the existing thin-film-transistor layer of an active matrix electrophoretic display device, optical sensing touch control is made applicable in the electrophoretic display device without compromising its advantageous light, flexible, thin features.

Abstract: Embodiments of the present disclosure related to electronic displays and electronic devices incorporating such displays which employ a device, method, or combination thereof for reducing the width of gate lines and/or data lines in the display. The result of which allows for increased pixel aperture size. The present disclosure provides techniques for reducing the width of gate lines and/or data lines while maintaining an acceptable resistance level in the gate lines and/or data lines.

Abstract: There are provided a substrate including an oxide TFT having improved initial threshold voltage degradation characteristics included in a driving circuit of a liquid crystal display (LCD) device, a method for fabricating the same, and a driving circuit for an LCD device using the same. The substrate including an oxide thin film transistor (TFT) includes: a base substrate divided into a pixel region and a driving circuit region; and a plurality of TFTs formed on the base substrate, wherein an initial threshold voltage of at least one of the plurality of TFTs formed in the driving circuit region is positive-shifted to have a predetermined level.

Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.

Abstract: A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose.

Abstract: An array substrate for an organic electroluminescent display device includes a substrate including a display area and a non-display area; a gate line and a data line; a thin film transistor including a semiconductor layer of polycrystalline silicon, a gate insulating layer, a gate electrode, an inter insulating layer, a source electrode, and a drain electrode; auxiliary lines formed of a same material and on a same layer as the data line; a passivation layer of organic insulating material and including a drain contact hole exposing the drain electrode, and an auxiliary line contact hole exposing one of the auxiliary lines; and a first electrode and a line connection pattern on the passivation layer, wherein the first electrode contacts the drain electrode and the line connection pattern contacts the one of the first auxiliary pattern.

Abstract: The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate.

Abstract: A low leakage current transistor (2) is provided which includes a GaN-containing substrate (11-14) covered by a passivation surface layer (17) in which a T-gate electrode with sidewall extensions (20) is formed and coated with a multi-level passivation layer (30-32) which includes an intermediate etch stop layer (31) which is used to define a continuous multi-region field plate (33) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.

Abstract: A semiconductor light emitting device includes a supporting substrate, a light emitting layer including a nitride semiconductor, and a nitride multilayer film. The nitride multilayer film includes a first layer including a first nitride semiconductor containing aluminum nitride, a second layer including a second nitride semiconductor containing gallium nitride, and a third layer including the first nitride semiconductor containing aluminum nitride.

Abstract: [Technical Problem] A sapphire substrate and a method for manufacturing the same are provided, which enables growth of a nitride semiconductor having excellent crystallinity and can achieve a nitride semiconductor light emitting element having excellent light extraction efficiency. [Solution to Problem] A sapphire substrate provided with a plurality of projections on a principal surface on which a nitride semiconductor is grown to form a nitride semiconductor light emitting element, wherein the projection is substantially pyramidal-shaped having a pointed top and constituted by a plurality of side surfaces, wherein the side surface has an inclined angle of between 53° and 59° from a bottom surface of the projection, and wherein the side surface is crystal-growth-suppressed surface on which growth of nitride semiconductor is suppressed relative to the substrate surface located between the adjacent projections.

Abstract: The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers.

Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.

Abstract: A light emitting device is constituted by flip-chip mounting a GaN-based LED chip. The GaN-based LED chip includes a light-transmissive substrate and a GaN-based semiconductor layer formed on the light-transmissive substrate, wherein the GaN-based semiconductor layer has a laminate structure containing an n-type layer, a light emitting layer and a p-type layer in this order from the light-transmissive substrate side, wherein a positive electrode is formed on the p-type layer, the electrode containing a light-transmissive electrode of an oxide semiconductor and a positive contact electrode electrically connected to the light-transmissive electrode, and the area of the positive contact electrode is half or less of the area of the upper surface of the p-type layer.

Abstract: A nitride semiconductor wafer includes a substrate, and a buffer layer formed on the substrate and including an alternating layer of AlxGa1-xN (0?x?0.05) and AlyGa1-yN (0<y?1 and x<y) layers. Only the AlyGa1-yN layer in the alternating layer is doped with an acceptor.

Abstract: Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm?2 or less and high-quality AlN substrates having surfaces of any desired crystallographic orientation fabricated from these bulk crystals.

Abstract: An optoelectronic semiconductor chip including a semiconductor body of semiconductor material, an outcoupling face arranged downstream of the semiconductor body in an emission direction and a mirror layer, wherein the semiconductor body includes an active layer that generates radiation, the mirror layer is arranged on the side of the semiconductor body remote from the outcoupling face, and a gap between the active layer and the mirror layer is set such that radiation emitted by the active layer towards the outcoupling face interferes with radiation reflected at the mirror layer such that the semiconductor chip features an emitted radiation pattern with a selected direction in the forward direction.

Abstract: A GaN single crystal substrate has a main surface with an area of not less than 10 cm2, the main surface has a plane orientation inclined by not less than 65° and not more than 85° with respect to one of a (0001) plane and a (000-1) plane, and the substrate has at least one of a substantially uniform distribution of a carrier concentration in the main surface, a substantially uniform distribution of a dislocation density in the main surface, and a photoelasticity distortion value of not more than 5×10?5, the photoelasticity distortion value being measured by photoelasticity at an arbitrary point in the main surface when light is applied perpendicularly to the main surface at an ambient temperature of 25° C. Thus, the GaN single crystal substrate suitable for manufacture of a GaN-based semiconductor device having a small variation of characteristics can be obtained.

Abstract: A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.

Abstract: A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided.

Abstract: A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate.

Abstract: A semiconductor device includes an active region in which current flows when the semiconductor device is in an on state and a breakdown voltage structure portion which surrounds the active region. In the active region, a MOS gate structure includes, a p well region, an n+ source region, a gate electrode, and a source electrode is provided on the front surface of a semiconductor substrate. A drain electrode which comes into contact with an n? drift region is provided from the rear surface to the side surface of the semiconductor substrate. The drain electrode forms a Schottky contact with the n? drift region which is the semiconductor substrate. In the breakdown voltage structure portion, a leakage current reducing layer reduces leakage current from the outer circumferential edge of the semiconductor substrate and is provided at least at the outer circumferential edge of the semiconductor substrate.

Abstract: In some aspects of the invention, semiconductor unit can produce chips performing uniform parallel operation and a low-thermal-resistance. Aspects of the invention can include a plurality of small semiconductor chips of one and the same kind formed by use of an SiC substrate, which is a wide gap substrate are sandwiched between two conductive plates. In this manner, there can be provided a high-reliability semiconductor unit in which parallel operation of the semiconductor chips is uniformized so that breakdown caused by current concentration can be prevented.

Abstract: In some aspects of the invention, a layer containing titanium and nickel is formed on an SiC substrate. A nickel silicide layer containing titanium carbide can be formed by heating. A carbon layer precipitated is removed by reverse sputtering. Thus, separation of an electrode of a metal layer formed on nickel silicide in a subsequent step is suppressed. The effect of preventing the separation can be further improved when the relation between the amount of precipitated carbon and the amount of carbon in titanium carbide in the surface of nickel silicide from which the carbon layer has not yet been removed satisfies a predetermined condition.

Abstract: A silicon carbide semiconductor device that is able to increase the gate reliability, and to provide a method for manufacturing the silicon carbide semiconductor device, and that includes: a source electrode selectively formed on a source region; a gate insulating film formed so as to extend over the source region; and a gate electrode formed on the gate insulating film. The source region includes a first source region located below the source electrode, and a second source region surrounding the first source region. The doping concentration in a superficial layer of the second source region is lower than the doping concentration in a superficial layer of the first source region. The doping concentration in the second source region is higher in a deep portion than in a superficial portion thereof.

Abstract: A method of producing an optoelectronic component includes providing a semiconductor chip having an active layer that generates radiation and is arranged on a carrier, applying a dispersed material including a matrix material and particles embedded therein to the semiconductor chip and/or the carrier at least in regions, wherein before the dispersed material is applied, at least one chip edge of the semiconductor chip facing away from the carrier is modified such that the dispersed material at least partly separates into its constituents during application at the chip edge.

Abstract: Some embodiments of the present disclosure relate to an infrared (IR) opto-electronic sensor having a silicon waveguide implemented on a single silicon integrated chip. The IR sensor has a semiconductor substrate having a silicon waveguide extends along a length between a radiation input conduit and a radiation output conduit. The radiation input conduit couples radiation into the silicon waveguide, while the radiation output conduit couples radiation out from the silicon waveguide. The silicon waveguide conveys the IR radiation from the radiation input conduit to the radiation output conduit at a single mode. As the radiation is conveyed by the silicon waveguide, an evanescent field is formed that extends outward from the silicon waveguide to interact with a sample positioned between the radiation input conduit and the radiation output conduit.

Abstract: According to an embodiment, a semiconductor device includes a primary side lead, a light-emitting element electrically connected to the primary side lead, and a thyristor-type light-receiving element. The light-receiving element includes a first face for detecting light emitted from the light-emitting element, and a second face provided on an opposite side of the first face. The light-receiving element includes an anode electrode, a cathode electrode, and a gate electrode that are provided on the first face. The device further includes a secondary side first lead electrically connected to the anode electrode, a secondary side second lead electrically connected to the cathode electrode, and a secondary side third lead electrically connected to the gate electrode. The secondary side third lead is connected to the second face of the light-receiving element.

Abstract: A semiconductor electricity converter is provided. The semiconductor electricity converter includes: an AC input module, for converting an input AC electric energy into a light energy, the AC input module including a plurality of semiconductor electricity-to-light conversion structures, each semiconductor electricity-to-light conversion structure including an electricity-to-light conversion layer; and an AC output module, for converting the light energy into an output AC electric energy, the AC output module including a plurality of semiconductor light-to-electricity conversion structures, each semiconductor light-to-electricity conversion structure including a light-to-electricity conversion layer; in which an emitting spectrum of each semiconductor electricity-to-light conversion structure and an absorption spectrum of each semiconductor light-to-electricity conversion structure are matched with each other.