Abstract: A conductive paste composition contains a source of an electrically conductive metal, an alkaline-earth-metal boron tellurium oxide, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the paste composition on a semiconductor device substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and establish electrical contact between it and the device.

Abstract: A conductive paste composition contains a source of an electrically conductive metal, a Ti—Te—Li oxide, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the paste composition on a semiconductor substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and establish electrical contact between it and the device.

Abstract: The electro-optical device includes a semiconductor layer, a first metal layer and an electrical insulator layer disposed between the semiconductor layer and the first metal layer. The electrical insulator layer includes a silicon nitride layer so as to provide an interface between the first metal layer and the silicon nitride layer. The electro-optical device is configured to carry a plasmonic wave.

Abstract: Photo-conducting infrared sensors are provided including a substrate (e.g., silicon) with one or more trenches formed on a first surface. An infrared-reflective film can be deposited directly or indirectly onto and conforming in shape with the first surface of the substrate. A lead chalcogenide film can be deposited directly or indirectly over the top of the infrared-reflective film and conforming in shape with the first surface of the substrate. Accordingly, the infrared-reflective film is directly or indirectly sandwiched between the substrate and the lead chalcogenide film.

Abstract: A solid-state imaging device including pixel photododes on a light-receiving surface of a substrate; a first insulating film on the substrate covering a multilayer wiring on and in contact with the substrate. The first insulating film comprises material of a first refractive index lower than a refractive index of the substrate for at least bottom and top surface portions of the first insulating film. A second insulating film with a second refractive index higher than the first refractive index is on the first insulating film. A third insulating film with a third refractive index higher than the second refractive index is on the second insulating film. For each pixel, a color filter is on the third insulating film.

Abstract: Prepared is an n? type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n? type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n? type semiconductor substrate 1 is formed on the second principal surface 1b side of the n? type semiconductor substrate 1. After formation of the accumulation layer 11, the n? type semiconductor substrate 1 is subjected to a thermal treatment.

Abstract: A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter comprising a first material layer and a second material layer formed in association with the first shaping material layer.

Abstract: A device includes an image sensing element. The device also includes a Silicon Dioxide (SiO2) layer, located over the image sensing element, exhibiting a first index of refraction. The device further includes a first lens, located over the SiO2 layer, exhibiting a second index of refraction greater than the first index of refraction. The device still further includes a color filter located over the first lens and a second lens located over the color filter.

Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.

Abstract: A device includes a semiconductor substrate, a black reference circuit in the semiconductor substrate, a metal pad on a front side of, and underlying, the semiconductor substrate, and a first and a second conductive layer. The first conductive layer includes a first portion penetrating through the semiconductor substrate to connect to the metal pad, and a second portion forming a metal shield on a backside of the semiconductor substrate. The metal shield is aligned to the black reference circuit, and the first portion and the second portion are interconnected to form a continuous region. The second conductive layer includes a portion over and contacting the first portion of the first conductive layer, wherein the first portion of the first conductive layer and the portion of the second conductive layer form a first metal pad. A dielectric layer is overlying and contacting the second portion of the first conductive layer.

Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions

Abstract: A semiconductor package including a substrate including an epoxy-based material, an image sensor chip mounted on the substrate, and an attaching part provided between the substrate and the image sensor chip may be provided. The attaching part may include a first attaching part, and a second attaching part provided around the first attaching part. The first attaching part may achieve high reliability of the semiconductor package in association with the second attaching part. The second attaching part may include a material having a low rigidity. Thus, it is possible to reduce or prevent warpage of the image sensor chip from occurring. Due to the presence of the second attaching part, a plane coverage ratio of the first attaching part relative to the image sensor chip can be reduced. Thus, the warpage of the image sensor chip can be reduced or prevented more effectively.

Abstract: A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.

Abstract: The present specification discloses front-side contact back-side illuminated (FSC-BSL) photodiode array having improved characteristics such as high speed of each photodiode, uniformity of the bias voltage applied to different photodiode, low bias voltage, reduced resistance of each photodiode, and an associated reduction in noise. The photodiode array is made of photodiodes with front metallic cathode pads, front metallic anode pad, back metallic cathode pads, n+ doped regions and a p+ doped region. The front metallic cathode pads physically contact the n+ doped regions and the front metallic anode pad physically contacts the p+ doped region. The back metallic cathode pads physically contact the n+ doped region.

Abstract: An optical device includes a first region and an isolating layer which are each provided in a semiconductor substrate. The first region configures a photoelectric converter and includes at least an impurity of a first conductivity type. The isolating layer is configured to inhibit passage of electrons. The isolating layer includes a second region which is below the first region and which includes an impurity of a second conductivity type, a third region which surrounds the first region in plan-view thereof and which includes an impurity of the second conductivity type, and a fourth region which surrounds the second region in plan-view thereof and which is connected to the third region. The fourth region is greater in width than a connecting part of the third region which connects the third region to the fourth region.

Abstract: In one embodiment, a MEMS sensor includes a mirror and an absorber spaced apart from the mirror, the absorber including a plurality of spaced apart conductive legs defining a tortuous path across an area directly above the mirror.

Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.

Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

Abstract: An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

Abstract: A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.

Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus.

Abstract: Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.

Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.

Abstract: A capacitor structure includes a first conductive structure, a dielectric structure, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode. The first conductive structure is disposed over a substrate. The dielectric structure is disposed over the substrate and partially enclosing the first conductive structure. The dielectric structure has a trench. A first surface of the first conductive structure is exposed through the trench of the dielectric structure. The first capacitor electrode is disposed on a bottom and a sidewall of the trench. The first capacitor electrode is electrically contacted with the first surface of the first conductive structure. The capacitor dielectric layer is disposed on a surface of the first capacitor electrode. The second capacitor electrode is disposed on a surface of the capacitor dielectric layer and filled in the trench.

Abstract: A semiconductor device has a silicon substrate, a shield which is disposed on the silicon substrate and comprises a conductive material, a capacitor electrode disposed on the shield, and at least one pillar member which is provided between the shield and the silicon substrate and comprises a conductive material. The pillar member may be disposed at a location other than a location of the through-hole.

Abstract: A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction.

Abstract: A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region.

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract: A compound semiconductor device and method of fabricating the same according to the present invention is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region, and a semiconductor layer disposed on the substrate, wherein doping conditions of said first doped region and said second doped region may be different from each other.

Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.

Abstract: A method for producing a semiconductor layer is disclosed. One embodiment provides for a semiconductor layer on a semiconductor substrate containing oxygen. Crystal defects are produced at least in a near-surface region of the semiconductor substrate. A thermal process is carried out wherein the oxygen is taken up at the crystal defects. The semiconductor layer is deposited epitaxially over the near-surface region of the semiconductor substrate.

Abstract: Disclosed herein is a semiconductor substrate having a crack preventing structure, the semiconductor substrate including: a plurality of wiring layers and a plurality of insulating layers sequentially stacked on a device divided into integrated circuit device areas and a cutting area separating the device areas from each other; opening parts formed to spatially separate the insulating layers in the device areas and the insulating layers in the cutting area from each other; and chamfering parts formed at outer sides of the insulating layers in the device areas contacting the opening parts, wherein the plurality of wiring layers are formed between the insulating layers in the cutting area and the device.

Abstract: There is provided a semiconductor device including a semiconductor layer, a protective layer including a transparent material, and a transparent resin layer that seals a gap between the semiconductor layer and the protective layer. A chip prevention member with a higher Young's modulus than the transparent resin layer is formed to come into contact with the semiconductor layer in a dicing portion of a layer structure before fragmentation, and dicing is performed in the dicing portion for the fragmentation.

Abstract: A semiconductor chip includes a semiconductor substrate having one surface, the other surface which faces away from the one surface, and an integrated circuit which is formed on the one surface; and a shielding layershielding layer formed in the semiconductor substrate to correspond to the other surface.

Abstract: A method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapour deposition in a reactor, includes adjusting a deposition temperature between 605° C.-800° C. in a process chamber of the reactor, and depositing the one or more polycrystalline silicon layers on the substrate by using a silicon source gas including SiH4 or SiH2Cl2, and a dopant gas including BCl3.

Abstract: A method of manufacturing a semiconductor device with an SON structure having a thick cavity inside a semiconductor substrate is disclosed. The method forms a plurality of trenches with a predetermined distance between adjacent trenches. Each trench has, at a middle portion between the trench top and bottom, an outwardly expanding sectional shape. High temperature annealing is conducted driving surface migration of silicon atoms in the surface region of the silicon substrate to close the top of the trench, resulting in formation of a plurality of small cavities composed of the trenches in the silicon substrate. Further high temperature annealing joins the plurality of small cavities to form a single cavity. Second opening width x2 at the middle portion ranges from 1.1 times to 1.5 times of first opening width x1 at the top of the trench. Aspect ratio of the trench is at least 8.

Abstract: An electronic element includes a substrate; a patterned first electrically conductive layer on the substrate; a patterned second electrically conductive layer on the substrate; and a dielectric stack on the substrate. A portion of the first electrically conductive layer and a portion of the second electrically conductive layer overlap each other such that an overlap region is present. At least a portion of the dielectric stack is positioned in the overlap region between the patterned first electrically conductive layer and the patterned second electrically conductive layer. The dielectric stack includes a first inorganic thin film dielectric material layer and a second inorganic thin film dielectric material layer. The first inorganic thin film dielectric material layer and the second inorganic thin film dielectric material layer have the same material composition.

Abstract: Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor substrate can then be placed in an atomic layer deposition (ALD) chamber to repeatedly perform a selective ALD process. The selective ALD process can include an etching process and/or a purging process in the ALD chamber. By repeatedly performing the selective ALD process, a first high-K dielectric layer can be selectively formed on the first silicon oxide layer in the first region, exposing the semiconductor substrate in the second region.

Abstract: A semiconductor device includes a semiconductor substrate, an insulator film that is arranged above the semiconductor substrate, a first passivation film that is arranged above the insulator film, a second passivation film that is arranged above the first passivation film, a stress relaxation layer that is arranged above the second passivation film, an organic coated film that is arranged above the stress relaxation layer, and a resin layer that is arranged above the organic coated film, wherein a Young's modulus of the stress relaxation layer is smaller than a Young's modulus of the organic coated film, and is smaller than a Young's modulus of the second passivation film.

Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconductor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.

Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.

Abstract: An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side, and a bump connected with the through silicon via.

Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.

Abstract: Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.

Abstract: In a preferred embodiment, a wiring board with embedded device, built-in stopper and electromagnetic shielding includes a stopper, a semiconductor device, a stiffener with shielding sidewalls, a first build-up circuitry and a second build-up circuitry with a shielding lid. The first and second build-up circuitries cover the semiconductor device, the stopper and the stiffener in the opposite vertical directions. The shielding sidewalls and the shielding lid are electrically connected to at least one ground contact pad of the semiconductor device by the first build-up circuitry and can respectively serve as effective horizontal and vertical electromagnetic shields for the semiconductor device within the aperture of the stiffener.

Abstract: An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material.

Abstract: One embodiment is a packaged device having multiple layers. Another embodiment is a method of forming a packaged device having multiple layers. Conductive layers and insulating layers can be formed with openings exposing semiconductor devices. The semiconductor devices can be wire-bonded to the conductive layers. In some embodiments, parasitic effects and a relative footprint of the packaged device can be reduced.