Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.

Abstract: In a display substrate, a method for manufacturing the display substrate and an electro-wetting display apparatus including the display substrate, the display substrate includes a base substrate, a sidewall defining a unit pixel area, a pixel electrode, a hydrophobic insulating layer and a light blocking layer. The sidewall is on the base substrate and defines the unit pixel area. The pixel electrode is in the unit pixel area. The hydrophobic insulating layer is on the sidewall and the pixel electrode. The light blocking layer is on the hydrophobic insulating layer and overlaps the sidewall.

Abstract: According to one embodiment, a semiconductor device includes a conductive member, a semiconductor element, a sealing section. The semiconductor element is provided on an upper surface of the conductive member. The sealing section seals part of the conductive member and the semiconductor element. The upper end of the semiconductor element is located above the uppermost portion of the conductive member. The conductive member includes an inclined surface and a lower surface. The inclined surface is provided on an outside of the sealing section and makes an acute angle with the upper surface. The lower surface is provided outside the sealing section and makes an obtuse angle with the inclined surface.

Abstract: An LED package includes a substrate, an LED chip mounted on the substrate, and a lens formed on the substrate and encapsulating the LED chip therein. The lens includes a top surface and a bottom surface connecting a bottom end of the top surface. The bottom surface is directly formed on the substrate. A tangent of the top surface extends through a joint of the top surface and the bottom surface to define a contacting angle between the tangent and a plumb line, and the contacting angle is not larger than 60 degrees.

Abstract: A light-emitting device may comprise a substrate, an electric wire fixed to the substrate, and a plurality of light-emitting diodes mounted to the electric wire. According to one embodiment, each of the plurality of light-emitting diodes is an LED chip, and the light-emitting diodes on the substrate are sealed individually or collectively by one or more sealing members. According to another embodiment, the substrate has a plurality of through holes, wherein a plurality of portions of the electric wire provided on a rear surface side of the substrate communicates with a front surface side of the substrate at the plurality of through holes of the substrate, and wherein the plurality of light-emitting diodes is respectively mounted to the respective portions of the electric wire that communicate with the front surface side of the substrate. Other embodiments relate to methods of manufacturing a light-emitting device.

Abstract: A light emitting device includes a conductive support member, and first and second light emitting structures. A channel layer is provided around lower portions of the first and second light emitting structures. A first electrode is coupled to a first conductive first semiconductor layer of the first light emitting structure, and a second electrode is coupled to a second semiconductor layer of the first light emitting structure. A third electrode is coupled to a third semiconductor layer of the second light emitting structure, and a fourth electrode is coupled to a fourth semiconductor layer of the second light emitting structure. A first connection part is coupled to the first electrode and the conductive support member, and a second connection part is coupled to the second and third electrodes. A third connection part is coupled to the fourth electrode and has one end provided on the channel layer.

Abstract: A capacitance setting line is disposed at the top end of a pixel, a light emission setting line is disposed at the bottom end of the pixel, and a gate line is disposed at the center between both the lines. A selection transistor, a potential control transistor and a capacitor are disposed between the gate line and a capacitance setting line. A short-circuit transistor, a drive transistor and a drive control transistor are disposed between the gate line and the light emission setting line. With such an arrangement, the efficient arrangement of wiring contacts can be performed, and an aperture ratio can be increased.

Abstract: A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate.

Abstract: A light emitting diode (LED) structure comprises a first dopant region, a dielectric layer on top of the first dopant region, a bond pad layer on top of a first portion the dielectric layer, and an LED layer having a first LED region and a second LED region. The bond pad layer is electrically connected to the first dopant region. The first LED region is electrically connected to the bond pad layer.

Abstract: An LED device comprises an LED chip or LED chip array for emitting light of a color spectrum, the LED chip or array being mounted on a component having a component surface. At least one color is applied to the component surface where the color is selected to reflect light to color tune the light emitted from the LED device to obtain a desired CRI.

Abstract: Exemplary embodiments of the present invention relate to a light emitting device including a light emitting diode and a surface-modified luminophore. The surface-modified luminophore includes a quantum dot luminophore and a fluorinated coating arranged on the quantum dot luminophore.

Abstract: The invention provides an array substrate, a manufacturing method and a display device thereof. The array substrate comprises a substrate, a gate line and a pixel electrode disposed on the substrate, a common electrode disposed above and overlaying the gate line, wherein a strip-shaped through hole is disposed on the common electrode and at least a portion of the strip-shaped through hole is positioned right above the gate line.

Abstract: A multilayered LED printed circuit board with electrically insulating layers includes at least one electrically insulating material and electrically conductive layers consisting of an electrically conductive material, wherein at least one of the electrically conductive layers is structured with a conductor track structure, wherein the at least one structured electrically conductive layer is arranged on an upper side of the LED printed circuit board, and wherein a plurality of LEDs is arranged on the at least one structured electrically conductive layer on the upper side. The LED printed circuit board further includes: a thermally conducting element, and thermal paths comprising an electrically conductive material, which are arranged, in each case in contact-making fashion, between the LEDs and the thermally conducting element.

Abstract: According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)?Wi)/Wi?0.008.

Abstract: A method for producing a thin-film semiconductor body is provided. A growth substrate is provided. A semiconductor layer with funnel-shaped and/or inverted pyramid-shaped recesses is epitaxially grown onto the growth substrate. The recesses are filled with a semiconductor material in such a way that pyramid-shaped outcoupling structures arise. A semiconductor layer sequence with an active layer is applied on the outcoupled structures. The active layer is suitable for generating electromagnetic radiation. A carrier is applied onto the semiconductor layer sequence. At least the semiconductor layer with the funnel-shaped and/or inverted pyramid-shaped recesses is detached, such that the pyramid-shaped outcoupling structures are configured as projections on a radiation exit face of the thin-film semiconductor body.

Abstract: A light-emitting diode (LED) with a mirror protection layer includes sequentially stacked an N-type electrode, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a metal mirror layer, a protection layer, a buffer layer, a binding layer, a permanent substrate, and a P-type electrode. The protection layer is made of metal oxide, and has a hollow frame for covering or supporting edges of the metal mirror layer. Accordingly, the metal mirror layer can be protected by the protection layer to prevent from oxidation in subsequent processes and to prevent metal deterioration during high-current operations. Thus the metal mirror layer can maintain high reflectivity, thereby increasing light extraction efficiency and electrical stability of the LED.

Abstract: A semiconductor light emitting device is provided that includes a support substrate, a first metal layer formed on the support substrate, a transparent conductive layer formed on the first metal layer, a second metal layer embedded in the transparent conductive layer, and a semiconductor light emitting layer formed on the transparent conductive layer. A reflectance of the second metal layer to light emitted by the semiconductor light emitting layer is higher than a reflectance of the first metal layer to light emitted by the semiconductor light emitting layer.

Abstract: An LED package includes adjacent first and second electrodes, first and second extension electrodes protruding sideward from the first and second electrodes, a molded body surrounding the first and second electrodes and an LED die. The molded body forms a reflecting cup located over the first and second electrodes, with each reflecting cup defining a receiving cavity in a top face thereof to receive the LED die. The first and second extension electrodes are exposed from an outer periphery of the molded body. The first electrode has a first bottom face. The second electrode has a second bottom face. The first and second bottom faces of the first and second electrodes are exposed out from a bottom face of the molded body. A method for manufacturing the LED package is also provided.

Abstract: An LED package includes a first electrode, a second electrode adjacent to the first electrode, a molded body surrounding and encapsulating the first and second electrodes, and an LED die mounted on the second electrode. The molded body includes a reflecting cup located over the first and second electrodes and the reflecting cup defines a receiving cavity in a top face to receive the LED die. A first extension electrode protrudes sideward from the first electrode and a second extension electrode protrudes sideward from the second electrode. The first and second extension electrodes are exposed from an outer periphery of the molded body. A method for manufacturing the LED package is also provided.

Abstract: The light emitting device includes a light emitting chip, and an optical lens provided over the light emitting chip. The optical lens includes an incident surface into which a light emitted from the light emitting chip is incident, a recess portion opposite to the incident surface and recessed in a direction of the incident surface, an exit surface provided at a peripheral portion of the recess portion to output a light incident through the incident surface, and a convex portion protruding between the recess portion and the exit surface and connected with at least one of the recess portion and the exit surface through an inflection point. The convex portion is located inward of a line segment ranging from the light emitting chip to a first inflection point provided at an outermost portion of the recess portion.

Abstract: A flip-chip light-emitting diode structure comprises a carrier substrate, a light-emitting die structure, a reflective layer, an aperture, a dielectric layer, a first contact layer and a second contact layer. The light-emitting die structure, located on the carrier substrate, comprises a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The light emitting layer is formed between the first type and the second type semiconductor layer. The reflective layer is located on the first type semiconductor layer. The aperture penetrates the light-emitting die structure. The dielectric layer covers an inner sidewall of the aperture and extends to a portion of a surface of the reflective layer. The first contact layer is disposed on the part of the reflective layer not covered by the dielectric layer. The second contact layer fills up the aperture and is electrically connected to the second type semiconductor layer.

Abstract: There is provided an electrode foil, which can show superior light scattering, while preventing short circuit between electrodes. The electrode foil of the present invention comprises a metal foil having a thickness of from 1 ?m to 250 ?m, wherein the electrode foil comprises, on at least one outermost surface thereof, a light-scattering surface having a Pv/Pp ratio of 2.0 or higher, wherein the Pv/Pp ratio is a ratio of a maximum profile valley depth Pv of a profile curve to a maximum profile peak height Pp of the profile curve as measured in a rectangular area of 181 ?m×136 ?m in accordance with JIS B 0601-2001.

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence and a carrier substrate. A first and a second electrical contact layer are arranged at least regionally between the carrier substrate and the semiconductor layer sequence and are electrically insulated from each other by an electrically insulating layer. A minor layer is arranged between the semiconductor layer sequence and the carrier substrate. The semiconductor chip comprises a transparent encapsulation layer covering side surfaces of the semiconductor layer sequence, side surfaces of the minor layer and side surfaces of the electrically insulating layer facing towards the side surfaces of the semiconductor chip.

Abstract: An optoelectronic semiconductor chip includes a carrier including a carrier element having a mounting side; one electrically conductive n-type wiring layer arranged at the mounting side; a structured, electrically conductive contact layer having a p-side and n-side contact region and arranged at a side of the n-type wiring layer facing away from the carrier element; at least one insulation region electrically insulating the p-side contact region from the n-side contact region; at least one electrically insulating spacer layer arranged at a side of the n-type wiring layer facing away from the carrier element in a vertical direction between the p-side contact region and the n-type wiring layer, wherein the n-side contact region and the n-type wiring layer electrically conductively connect to one another, and the p-side contact region and the spacer layer border the n-side contact region in a lateral direction; an optoelectronic structure connected to the carrier.

Abstract: A method for manufacturing a light emitting device comprises (a) preparing a structure including a substrate, a semiconductor layer formed on the substrate, and a p-side electrode and an n-side electrode formed on the semiconductor layer; (b) preparing a support member including a p-side wiring and an n-side wiring on the same surface thereof; (c) electrically connecting the p-side electrode and the n-side electrode of the structure to the p-side wiring and the n-side wiring of the support member, respectively, using an anisotropic conductive material containing conductive particles and a first resin; and after step (c), (d) removing the substrate from the structure.

Abstract: In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., freestanding white light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder.

Abstract: An ultraviolet light emitting diode package for emitting ultraviolet light is disclosed. The ultraviolet light emitting diode package comprises an LED chip emitting light with a peak wavelength of 350 nm or less, and a protective member provided so that surroundings of the LED chip is covered to protect the LED chip, the protective member having a non-yellowing property to energy from the LED chip.

Abstract: Solid state light sources based on LEDs mounted on or within thermally conductive luminescent elements provide both convective and radiative cooling. Low cost self-cooling solid state light sources can integrate the electrical interconnect of the LEDs and other semiconductor devices. The thermally conductive luminescent element can completely or partially eliminate the need for any additional heatsinking means by efficiently transferring and spreading out the heat generated in LED and luminescent element itself over an area sufficiently large enough such that convective and radiative means can be used to cool the device.

Abstract: A light-emitting device includes a first electrode; a light-emitting stacked layer on the first electrode; a first contact layer on the light-emitting stacked layer, wherein the first contact layer includes a first contact link and a plurality of first contact lines connected to the first contact link; a first conductive post in the light-emitting stacked layer and electrically connecting the first electrode and the first contact layer; and a passivation layer between the first conductive post and the light-emitting stacked layer.

Abstract: Disclosed are a light emitting diode (LED) package and a method of fabricating the same. The LED package includes a first substrate, a semiconductor stack disposed on a front surface of the first substrate, a second substrate including a first lead electrode and a second lead electrode, a plurality of connectors electrically connecting the semiconductor stack to the first and second lead electrodes, and a wavelength converter covering a rear surface of the first substrate. The semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

Abstract: Provided are a method of fabricating a light-emitting apparatus with improved light extraction efficiency and a light-emitting apparatus fabricated using the method. The method includes: preparing a monocrystalline substrate; forming an intermediate structure on the substrate, the intermediate structure comprising a light-emitting structure which comprises a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type stacked sequentially, a first electrode which is electrically connected to the first conductive pattern, and a second electrode which is electrically connected to the second conductive pattern; forming a polycrystalline region, which extends in a horizontal direction, by irradiating a laser beam to the substrate in the horizontal direction such that the laser beam is focused on a beam-focusing point within the substrate; and cutting the substrate in the horizontal direction along the polycrystalline region.

Abstract: A semiconductor light emitting element suppressing non-uniformity in light emission on a light emitting surface is provided. An n-type semiconductor layer, a light emitting layer and a p-type semiconductor layer are laminated in order, and a translucent electrode film is laminated on the p-type semiconductor layer and a p-electrode is provided on the translucent electrode film. On the other hand, an n-electrode is provided on a semiconductor layer exposure surface that exposes the n-type semiconductor layer. The p-electrode includes a connecting portion having a circular planar shape and an extending portion that extends like a long and slender strip from the connecting portion to encircle and face the n-electrode. Holes in the translucent electrode film are provided such that the density thereof is decreased along with a move from the n-electrode side toward the p-electrode side.

Abstract: A side view light emitting diode (LED) package includes an electrode structure, an LED die disposed on the electrode structure and an encapsulation layer covering the LED die. The encapsulation layer includes a light outputting surface. The electrode structure includes a first electrode and a second electrode spaced from each other to define a tortuous gap therebetween. Resin material for forming a substrate of the LED package fills in the gap to interconnect the first and second electrode together. The LED die is electrically connected to the first electrode and the second electrode. The present disclosure also provides a method for manufacturing the side view LED package.

Abstract: A semiconductor light emitting device includes: a first conductive semiconductor layer including first and second areas; an active layer disposed on the second area; a second conductive semiconductor layer disposed on the active layer; first and second electrode branches disposed on the first and second conductive semiconductor layers, respectively; a first electrode pad electrically connected to the first electrode branch and disposed on the first electrode branch; and a second electrode pad electrically connected to the second electrode branch and disposed on the second electrode branch.

Abstract: A light emitting diode (LED) structure (10) has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semi-conductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer (34) is formed in the gap followed by filling the gap with a metal (42). The metal is patterned to form stud bumps (40, 42, 44) that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

Abstract: A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

Abstract: An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate.

Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract: There is provided an insulated gate bipolar transistor, including: an active region including a gate electrode, a first emitter metal layer, a first well region, and one portion of a third well region; a termination region including a second well region supporting diffusion of a depletion layer; and a connection region located between the active region and the termination region and including a second emitter metal layer, a gate metal layer, and the other portion of the third well region, wherein the third well region is formed over the active region and the connection region, and the first emitter metal layer and the second emitter metal layer are formed on the third well region.

Abstract: A MOS type semiconductor device wherein on voltage is low, the rate of rise of current at turn-on time is low, and it is possible to hold down the rate of rise of collector current at turn-on time, and reduce radiation noise. The device includes a stripe-shaped plan-view pattern of protruding semiconductor region on an n-type substrate and having a p-type region sandwiched between an upper side n-type first region and a lower side n-type second region, a top flat portion including a depression region with a depth reaching the p-type region, and an inclined portion between the top flat portion and a bottom flat portion around the protruding semiconductor region; and a gate electrode with one end portion of the gate electrode on a surface within the inclined portion, and another end portion on a surface of the lower side n-type second region in the p-type region side vicinity.

Abstract: According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. Bottoms of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer.

Abstract: An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention.

Abstract: Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V material of the sacrificial gate material to form a gate of the transistor comprising a Me-III-V compound material.

Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

Abstract: According to example embodiments, a higher electron mobility transistor (HEMT) may include a first channel layer, a second channel layer on the first channel layer, a channel supply on the second channel layer, a drain electrode spaced apart from the first channel layer, a source electrode contacting the first channel layer and contacting at least one of the second channel layer and the channel supply layer, and a gate electrode unit between the source electrode and the drain electrode. The gate electrode unit may have a normally-off structure. The first and second channel layer form a PN junction with each other. The drain electrode contacts at least one of the second channel layer and the channel supply layer.

Abstract: A semiconductor device includes: an electron transit layer formed with a semiconductor material, the electron transit layer being formed on a semiconductor substrate; an n-type semiconductor layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the n-type semiconductor layer being formed on the electron transit layer; a ? doping area having an n-type impurity doped in a sheet-shaped region, the ? doping area being formed on the n-type semiconductor layer; and a barrier layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the barrier layer being formed on the ? doping area.

Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.

Abstract: A FET sensor with a gate biasing electrode is disclosed in one embodiment. In another embodiment, a process for forming a finFET sensor with a polysilicon gate biasing electrode is disclosed. In a further embodiment, a process for forming a finFET sensor with a single crystal gate biasing electrode is disclosed.

Abstract: A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilizing CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor.