Abstract: A light emitting device includes a substrate and a plurality of protrusions protruding from a top surface of the substrate. A first semiconductor layer is provided on top surfaces of the protrusions and a plurality of seed patterns protrudes from a bottom surface of the first semiconductor layer toward the protrusions. A medium layer is provided between the protrusions and a light emitting structure on a top surface of the first semiconductor layer. The bottom surface of the first semiconductor layer is located at a higher position than that of each of the protrusions, and the first semiconductor layer contacts a c-plane of each protrusion.

Abstract: Disclosed are a phosphor and a light emitting device including the same. The light emitting device includes a light emitting chip, a phosphor layer on the light emitting chip, and a phosphor added into the phosphor layer to absorb a light emitted from the light emitting chip and emit a central wavelength having a first blue color. The phosphor has a composition formula of LaxOySi6Al4N12:Ce3+z, a range of the x is 2?x?8, and a range of the y is 3?y?12.

Abstract: To provide a light emitting device having high light extraction efficiency, and a method for manufacturing the light emitting device. A method for manufacturing a light emitting device (100) according to the present invention, includes: forming a sealing member (40) for sealing a light emitting element (10) on a base body (30) by dropping, the base body (30) including a conductive member (20) for connecting to the light emitting element (10), and a molding (25) integrally molded with the conductive member (20); the sealing member (10) being formed such that at least a part of a periphery of the sealing member (40) is located on an outward surface (38) of the conductive member (20) or the molding (25), the outward surface facing outward in a top view.

Abstract: A phosphor sheet-forming resin composition uses a low-cost resin material having high light fastness and low visible light absorption and is capable of providing a phosphor sheet at low cost with deterioration of a phosphor due to moisture being suppressed. The resin composition contains a film-forming resin composition and a powdery phosphor that emits fluorescence when irradiated with excitation light. The film-forming resin composition used contains a polyolefin copolymer component and a maleic anhydride component. A sulfurized phosphor, an oxide-based phosphor, or a phosphor mixture thereof is preferably used as the phosphor.

Abstract: A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.

Abstract: An LED assembly according to an embodiment of the present invention may improve dark regions generated between LED chips by employing a first reflective layer between the LED chips. By employing a transparent optical layer or an optical layer including a scattering particle between an LED chip and a phosphor layer, direct contact between the LED chip and the phosphor layer may be avoided, thereby preventing a low light extraction efficiency. Further, by employing a second reflection layer on side surfaces of an LED chip, an optical layer, and a phosphor layer, a relatively high contrast may be obtained. An LED assembly may enhance contrast through a reflective layer while increasing light extraction efficiency by including a scattering particle in a phosphor layer.

Abstract: A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°.

Abstract: An electrical contact is formed on a III-V semiconductor comprising gallium. The contact is formed by depositing a first layer comprising In, Au, and a dopant on the surface of a III-V semiconductor and a second layer comprising a conductive oxide on the first layer. The deposited layers are annealed in an inert atmosphere. The annealing causes the formation of a Ga—Au compound at the interface between the III-V semiconductor and the first layer. At least a portion of the dopant migrates into the III-V semiconductor such that the dopant provides n-type or p-type conductivity to the III-V semiconductor. The specific contact resistivity between the III-V semiconductor and the second layer is less than about 10?5 ?cm2. The layers are further annealed in an oxidizing atmosphere such that the indium in the first layer is oxidized to form indium oxide.

Abstract: A light emitting device (LED) includes a stress control layer having a compressive stress on a substrate, a bonding layer on the stress control layer, a semiconductor layer on the bonding layer and including an active region for emitting light on the bonding layer, a first electrode on a lower surface of the substrate, and a second electrode on the semiconductor layer. The compressive stress of the stress control layer is between about 1 and about 20 GPa.

Abstract: A light-emitting device comprises a first semiconductor layer; and a transparent conductive oxide layer comprising a diffusion region having a first metal material and a non-diffusion region devoid of the first metal material, wherein the non-diffusion region is closer to the first semiconductor layer than the diffusion region.

Abstract: Disclosed is a light emitting device. The light emitting device includes a body having a cavity; first and second lead frames spaced apart from each other in the cavity, a gap part between the first and second lead frames, an adhesive material extending from at least one of sidewalls of the cavity to a top surface of at least one of the first and second lead frames, a light emitting chip on at least one of the first and second lead frames, and a molding member adhering to the adhesive material in the cavity.

Abstract: A semiconductor light-emitting element capable of increasing a strength of adhesion between an electrode and a protection film. The semiconductor light-emitting element includes a semiconductor structure having an n-type semiconductor layer and a p-type semiconductor layer. A transparent conductive film is disposed on the p-type semiconductor layer. An insulation film is disposed on the transparent conductive film. A p-side electrode layer is disposed on the insulation film. A protection film is disposed over the insulation film, and the protection film covers part of the p-side electrode layer.

Abstract: Substrates and packages for LED based light devices can incorporate a material with high thermal conductivity in at least the lateral direction (e.g., graphite or graphene) to spread heat across the surface of the substrate. A substrate or layer in a multi-layer substrate can have a graphite core disposed between ceramic sublayers that provide electrical insulation and thermal conductivity in the transverse direction. Another substrate or layer in a multi-layer substrate can be fabricated using a composite of graphite and ceramic materials.

Abstract: A light-emitting apparatus package of the present invention includes (i) an electrically insulated ceramic substrate, (ii) a first concave section formed in the direction of thickness of the ceramic substrate so as to form a light exit aperture in a surface of the ceramic substrate, (iii) a second concave section formed within the first concave section in the further direction of thickness of the ceramic substrate so that one or more light-emitting devices are provided therein, (iv) a wiring pattern for supplying electricity, which is provided in the first concave section, and (v) a metalized layer having light-reflectivity, which is (a) provided between the light-emitting device and the surface of the second concave section of the substrate, and (b) electrically insulated from the wiring pattern.

Abstract: An encapsulation housing for a LED module, may include an upper housing and a lower housing joined together and defining together a cavity, wherein at least one of the upper housing and the lower housing has an inner partition wall partitioning the cavity into an assembly cavity and an anti-leakage cavity encircling the assembly cavity.

Abstract: A light emitting device according to the embodiment includes a conductive support member; a light emitting structure on the conductive support member including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second semiconductor layers; and a protective device on the light emitting structure.

Abstract: A Group III nitride crystal substrate is provided for growing an epitaxial layer in which the Group III nitride crystal substrate is used for growing an epitaxial layer on the Group III nitride crystal substrate. The Group III nitride crystal substrate has a surface roughness Ra of 0.5 nm or less and an affected layer in which crystal lattices are out of order and has a thickness of 50 nm or less. The Group III nitride crystal substrate either has a principal plane parallel to any plane of A-plane and M-plane in the wurtzite structure or has an off-angle formed by the principal plane of the Group III nitride crystal substrate and any plane of A-plane and M-plane in the wurtzite structure being 0.05° to 15°.

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: An IGBT has layers between emitter and collector sides. The layers include a collector layer on the collector side, a drift layer, a base layer of a second conductivity type, a first source region arranged on the base layer towards the emitter side, a trench gate electrode arranged lateral to the base layer and extending deeper into the drift layer than the base layer, a well arranged lateral to the base layer and extending deeper into the drift layer than the base layer, an enhancement layer surrounding the base layer so as to completely separate the base layer from the drift layer and the well, an electrically conducting layer covering the well and separated from the well by a second electrically insulating layer, and a third insulating layer having a recess on top of the electrically conducting layer such that the electrically conducting layer electrically contacts a emitter electrode.

Abstract: An IGBT has layers between emitter and collector sides, including a drift layer, a base layer electrically contacting an emitter electrode and completely separated from the drift layer, first and second source regions arranged on the base layer towards the emitter side and electrically contacting the emitter electrode, and first and second trench gate electrodes. The first trench gate electrodes are separated from the base layer, the first source region and the drift layer by a first insulating layer. A channel is formable between the emitter electrode, the first source region, the base layer and the drift layer. A second insulating layer is arranged on top of the first trench gate electrodes. An enhancement layer separates the base layer from the drift layer. The second trench gate electrode is separated from the base layer, the enhancement layer and the drift layer by a third insulating layer.

Abstract: An IGBT has layers between emitter and collector sides. The layers include a drift layer, a base layer electrically contacting an emitter electrode and separated from the drift layer, a first source region arranged on the base layer towards the emitter side and electrically contacting the emitter electrode, and a first trench gate electrode arranged lateral to the base layer and separated from the base layer, the first source region and the drift layer by a first insulating layer. A channel exits between the emitter electrode, the first source region, the base layer and the drift layer. A second insulating layer is arranged on top of the first trench gate electrode. An enhancement layer separates the base layer from the drift layer in a plane parallel to the emitter side. A grounded gate electrode includes a second, grounded trench gate electrode and an electrically conducting layer.

Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.

Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.

Abstract: A method of fabricating a semiconductor device is disclosed comprising the steps of: providing a substrate having a first region, a second region and a plurality of gate electrodes which are formed on the first and second regions of the substrate; forming a mask film to expose the first region of the substrate while covering the second region of the substrate, such that the mask film has a negative lateral profile at a boundary between the first and second regions of the substrate; forming sigma trenches in the first region of the substrate by etching the first region of the substrate using the mask film and the gate electrodes as a mask; and forming an epitaxial layer in each of the sigma trenches.

Abstract: A semiconductor structure includes agate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer and exposing a portion of the second semiconductor layer, a gate electrode disposed on the portion of the second semiconductor layer exposed via the third semiconductor layer, and a source electrode and a drain electrode disposed on the third semiconductor layer at both sides of the gate electrode to be spaced apart from each other. An electrical segregation region is formed in the third semiconductor layer between the gate electrode and the drain electrode.

Abstract: A nitride semiconductor device includes an undoped GaN layer (1) and an undoped AlGaN layer (2) that are formed on an Si substrate (10), and ohmic electrodes (a source electrode (11) and a drain electrode (12)) that are formed on the undoped GaN layer (1) and the undoped AlGaN layer (2) and that are made of Ti/Al/TiN. Concentration of nitrogen in the ohmic electrodes is set in a range from 1×1016 cm?3 to 1×1020 cm?3. Consequently, contact resistance between the nitride semiconductor layers and the ohmic electrodes can be reduced.

Abstract: A high-speed SiGe HBT is disclosed, which includes: a substrate; STIs formed in the substrate; a collector region formed beneath the substrate surface and located between the STIs; an epitaxial dielectric layer including two portions, one being located on the collector region, the other being located on one of the STIs; a base region formed both in a region between and on surfaces of the two portions of the epitaxial dielectric layer; an emitter dielectric layer including two portions, both portions being formed on the base region; an emitter region formed both in a region between and on surfaces of the two portions of the emitter dielectric layer; a contact hole formed on a surface of each of the base region, the emitter region and the collector region. A method of manufacturing high-speed SiGe HBT is also disclosed.

Abstract: In accordance with an embodiment, a gating device is connected to a pixel core. The gating device may include a control structure and one or more terminals, wherein the one or more terminals are commonly connected to each other and connected to the pixel core. Alternatively, the terminals may be connected to corresponding photodiodes.

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract: One method includes forming first sidewall spacers adjacent opposite sides of a sacrificial gate structure and a gate cap layer, removing the gate cap layer and a portion of the first sidewall spacers to define reduced-height first sidewall spacers, forming second sidewall spacers, removing the sacrificial gate structure to thereby define a gate cavity, whereby a portion of the gate cavity is laterally defined by the second sidewall spacers, and forming a replacement gate structure in the gate cavity, wherein at least a first portion of the replacement gate structure is positioned between the second sidewall spacers. A device includes a gate structure positioned above the substrate between first and second spaced-apart portions of a layer of insulating material and a plurality of first sidewall spacers, each of which are positioned between the gate structure and on one of the first and second portions of the layer of insulating material.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: Disclosed is a photo sensor including a first conductive type semiconductor substrate, a photodiode region in a light receiving region of the semiconductor substrate, a first transistor including a first gate, a first source region and a first drain region, the first transistor being adjacent to the photodiode region, and a light-absorption control layer in a first region of the photodiode region, the light-absorption control layer exposing a second region of the photodiode region, wherein the first region is spaced apart from the first source region, and the second region is another portion of the photodiode region contacting the first source region.

Abstract: A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction.

Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination of which is accompanied with appropriate etch.

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.

Abstract: The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.

Abstract: The invention provides a B4-flash device and the manufacture method thereof, wherein the device comprises a substrate, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, and all those layers are disposed on the substrate in sequence. The first silicon oxide layer comprises a first section, a second section and a third section, and all those sections are along the channel direction in sequence. The thickness ratio among the first section, the second section and the third section is (1.5-2.5):(0.8-1.2):(1.5-2.5). The embodiments of the present invention use the non-uniform silicon oxide to slow down the degeneration of the silicon oxide and to relieve the effect of the programming of the electron injection and the erasing of the holes injection as well. As a result, the reliability of the device is improved.

Abstract: The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

Abstract: According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.

Abstract: A semiconductor transistor device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth shallower than the junction depth in the ion well; a recess at the bottom of the gate trench; a gate oxide layer at surface of the gate trench and in the recess to form a protruding tip structure; a gate in the gate trench; and a drain extension region between the gate trench and the epitaxial layer.

Abstract: A semiconductor transistor device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth shallower than the junction depth in the ion well; a recess at the bottom of the gate trench; a gate oxide layer at surface of the gate trench and in the recess to form a protruding tip structure; a gate in the gate trench; and a drain extension region between the gate trench and the epitaxial layer.

Abstract: Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench.

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon is disclosed. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity type, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A gate structure is disposed on the epitaxial structure. A method for fabricating a semiconductor device is also disclosed.

Abstract: A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region.

Abstract: A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. A drain region and a source region are respectively formed in the semiconductor substrate inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. The semiconductor substrate and the first heavily doped region have a first conductivity type and the well region and the second heavily doped region have a second conductivity type. A method for fabricating a semiconductor device is also disclosed.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method.