Patents Issued in May 8, 2014
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Publication number: 20140124911Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: Panasonic CorporationInventors: TEPPEI IWASE, TAKASHI YUI
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Publication number: 20140124912Abstract: Each stitch part of a plurality of leads of a package has a first region having the most outer surface on which Ag plating is applied and a second region having the most outer surface on which Ni plating is applied. Further, the second region is arranged on a die pad side, and the first region is arranged on a periphery side of a sealer. Therefore, in each stitch part, types of plating applied on the most outer surfaces of the first region and the second region can be differentiated from each other, a thick Al wire can be connected to the second region of the second lead, and a thin Au wire can be connected to the first region of the first lead. As a result, usage of only Au plating can be avoided, so that the cost of the package is reduced.Type: ApplicationFiled: October 28, 2013Publication date: May 8, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yoshiharu Kaneda
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Publication number: 20140124913Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: NVIDIA CORPORATIONInventors: Leilei Zhang, Ron Boja, Abraham Yee, Zuhair Bokharey
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Publication number: 20140124914Abstract: A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals.Type: ApplicationFiled: November 7, 2013Publication date: May 8, 2014Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.Inventors: CHANG-MING LIN, YU-JUAN TAO
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Publication number: 20140124915Abstract: A semiconductor module includes an insulating substrate (200) that is made of AlN and that has a first plane (201) and a second plane (202) both of which face mutually opposite directions, a first conductor layer (210) formed on the first plane (201), a second conductor layer (220) formed on the second plane (202), a semiconductor device (300) bonded to the first conductor layer (210) with a first solder layer (510) interposed therebetween, and a heat dissipation plate (400) that is formed in a rectangular shape when viewed planarly and that is bonded to the second conductor layer (220) with a second solder layer (520) interposed therebetween, and, in this semiconductor module, the heat dissipation plate (400) is deformed so as to become convex in a direction in which the second plane (202) is pointed when viewed from a width direction thereof.Type: ApplicationFiled: June 27, 2012Publication date: May 8, 2014Applicant: ROHM CO., LTD.Inventors: Kenji Hayashi, Masashi Hayashiguchi
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Publication number: 20140124916Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jung Wei Cheng, Tsung-Ding Wang, Ming-Da Cheng, Yung Ching Chen
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Publication number: 20140124917Abstract: A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: FUJITSU LIMITEDInventors: Michael G. Lee, Chihiro Uchibori
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Publication number: 20140124918Abstract: An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: LSI CORPORATIONInventors: Zeki Z. Celik, Allen S. Lim, Atila Mertol
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Publication number: 20140124919Abstract: The present invention relates to a semiconductor device and semiconductor process. The semiconductor device includes a substrate, a circuit layer, a plurality of under bump metallurgies (UBMs), a redistribution layer and a plurality of interconnection metals. The substrate has an active surface and a inactive surface. The circuit layer and the under bump metallurgies (UBMs) are disposed adjacent to the active surface. The redistribution layer is disposed adjacent to the inactive surface. The interconnection metals electrically connect the circuit layer and redistribution layer.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Che-Hau Huang, Ying-Te Ou
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Publication number: 20140124920Abstract: A stud bump structure and method for manufacturing the same are provided. The stud bump structure includes a substrate, and a first silver alloy stud bump disposed on the substrate, wherein the first silver alloy stud bump has a weight percentage ratio of Ag:Au:Pd=60-99.98:0.01-30:0.01-10.Type: ApplicationFiled: February 7, 2013Publication date: May 8, 2014Applicant: WIRE TECHNOLOGY CO., LTD.Inventors: Tung-Han CHUANG, Hsing-Hua TSAI, Jun-Der LEE
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Publication number: 20140124921Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.Type: ApplicationFiled: March 13, 2013Publication date: May 8, 2014Applicant: SK HYNIX INC.Inventors: Sang Eun LEE, Sung Soo RYU, Chang Il KIM, Seon Kwang JEON
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Publication number: 20140124922Abstract: The bump structure includes a metal pattern disposed on an electrode pad to have a vertical sidewall and a recessed region surrounded by the vertical sidewalls, a metal post including a lower portion inserted into the recessed region and a protruded portion upwardly extending from the lower portion, and a passivation spacer on a sidewall of the metal post. The metal post is electrically connected to the electrode pad.Type: ApplicationFiled: March 18, 2013Publication date: May 8, 2014Applicant: SK HYNIX INC.Inventors: Taek Joong KIM, Yong Su HAN
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Publication number: 20140124923Abstract: A semiconductor device includes a plurality of first metal wirings of first to n-th layers disposed on a substrate, and a plurality of pad wirings disposed on the first metal wirings and including a metal material of an n+1-th layer. The pad wirings are disposed in a staggered shape in a first direction and have a rectangular shape lengthily extending in a second direction. A plurality of additional wirings are disposed in an additional wiring region in the first direction and include the metal material of the n+1-th layer. The additional wiring region is disposed between the pad wirings. A plurality of pads may contact an upper surface of the pad wirings. The pads have a rectangular shape having a first width in the first direction and a first length greater than the first width in the second direction.Type: ApplicationFiled: November 6, 2013Publication date: May 8, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Young-Jin CHO
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Publication number: 20140124924Abstract: A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Wei Sen CHANG
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Publication number: 20140124925Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
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Publication number: 20140124926Abstract: Methods and systems for a chaser pellet in a semiconductor mold process are disclosed and may include a semiconductor package comprising semiconductor die coupled to a packaging substrate where the packaging substrate and the coupled semiconductor die may be placed in a mold chase. A chaser pellet may be placed on a target pellet comprising low alpha epoxy mold compound (EMC) in a pellet chamber coupled to the mold chase via a runner. Heat may be applied to the pellet chamber to melt the target pellet. Pressure may be applied to the chaser pellet to force EPM from the molten target pellet through the runner to the mold chase. The die may be encapsulated with the epoxy mold compound from the molten target pellet. Passive devices may be coupled to the semiconductor package and may be encapsulated by the EPM from the molten target pellet.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Inventor: Corey Reichman
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Publication number: 20140124927Abstract: An IC packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a metal pad and an insulating layer and the insulating layer has an opening to expose the meal pad. The method also includes forming an under-the-ball meal electrode on the exposed metal pad. The under-the-ball metal electrode has an electrode body and an electrode tail, the electrode body is located at a bottom portion of the under-the-ball metal electrode and is in contact with the metal pad, and the electrode tail is located at a top portion of the under-the-ball meal electrode. Further, the method includes forming a solder ball on the under-the-ball metal electrode.Type: ApplicationFiled: November 7, 2013Publication date: May 8, 2014Applicant: Nantong Fujitsu Microelectronics Co., Ltd.Inventors: CHANG-MING LIN, LEI SHI, XIAO-CHUN WU
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Publication number: 20140124928Abstract: Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.Type: ApplicationFiled: November 7, 2013Publication date: May 8, 2014Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.Inventors: CHANG-MING LIN, YU-JUAN TAO
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Publication number: 20140124929Abstract: Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the semiconductor substrate, a first insulating layer disposed over the semiconductor substrate, a columnar electrode disposed over the solder pad, and a solder ball disposed on the columnar electrode. The first insulating layer can include a first opening to expose a solder pad of the plurality of solder pads. The columnar electrode can include a bulk material and a through hole in the bulk material. The through hole can expose at least a surface portion of the solder pad. The solder ball can include a convex metal head on a top surface of the bulk material of the columnar electrode, and a filling part filled in the through hole.Type: ApplicationFiled: November 7, 2013Publication date: May 8, 2014Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.Inventors: CHANG-MING LIN, Lei SHI, GUO-HUA GAO
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Publication number: 20140124930Abstract: A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Ian Juso Dedic, Ghazanfer Ali
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Publication number: 20140124931Abstract: A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a polyurethane resin; at least one other resin selected from the group of an ethylene-vinyl acetate copolymer resin, an acrylonitrile resin, and a styrene resin; isobornyl acrylate; and conductive particles.Type: ApplicationFiled: November 5, 2013Publication date: May 8, 2014Inventors: Young Ju SHIN, Kyu Bong KIM, Hyun Joo SEO, Kyoung Hun SHIN, Woo Jun LIM
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Publication number: 20140124932Abstract: A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Min Huang
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Publication number: 20140124933Abstract: A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Marc A. Bergendahl, David V. Horak, Baozhen Li, Shom Ponoth
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Publication number: 20140124934Abstract: An interconnect structure located on a semiconductor substrate within a dielectric material positioned atop the semiconductor substrate is provided having an opening within the dielectric material, the opening includes an electrically conductive material extending from the bottom to the top, and contacting the sidewall; a first layer located on the sidewall of the opening, the first layer is made from a material including titanium oxide or titanium silicon oxide; a second layer located between the first layer and the electrically conductive material, the second layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr; and a third layer located along a top surface of the electrically conductive material, the third layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Daniel C. Edelstein, Takeshi Nogami
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Publication number: 20140124935Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have line widths of less than forty nanometers. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, performing a first sputter etch of the layer of conductive metal using a methanol plasma, and performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines.Type: ApplicationFiled: August 19, 2013Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: CYRIL CABRAL, JR., Benjamin L. Fletcher, Nicholas C.M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
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Publication number: 20140124936Abstract: A power semiconductor module has an insulating layer; a copper base substrate having first and second copper blocks, either the first or the second copper block being fixed on one side and the other being fixed on the other side of the insulating layer; a plurality of power semiconductor elements using silicon carbide, and having one side fixed onto the first copper block with a conductive bond layer; a plurality of implant pins fixed to the other side of each of the plurality of power semiconductor elements with a conductive bond layer; a printed circuit board fixed to the implant pins and disposed to face the power semiconductor elements; a first sealing material containing no flame retardant, and disposed at least between the power semiconductor elements and the printed circuit board; and a second sealing material containing a flame retardant, and disposed to cover the first sealing material.Type: ApplicationFiled: April 16, 2012Publication date: May 8, 2014Applicant: FUJI ELECTRIC CO., LTDInventors: Katsuhiko Yanagawa, Yoshinari Ikeda
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Publication number: 20140124937Abstract: A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Jiun Yi Wu
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Publication number: 20140124938Abstract: A semiconductor integrated circuit includes a semiconductor substrate, one or more devices in or on the semiconductor substrate, and a dielectric layer above the one or more devices, wherein the dielectric layer has openings over at least portions of the one or more devices. The semiconductor integrated circuit also includes plastic packaging material (e.g., plastic granules) on a top surface of the dielectric layer and over the openings. In some implementations, the one or more devices include bi-polar transistors, and the openings in the dielectric layer are located over base-emitter junctions of the bi-polar devices.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: ATMEL CORPORATIONInventor: Scott N. Fritz
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Publication number: 20140124939Abstract: A method of making an electronic device having a discrete device mounted on a surface of an electronic die with both the discrete device and the die connected by heat cured conductive ink and covered with cured encapsulant including placing the discrete device on the die; and keeping the temperature of each of the discrete device and the die below about 200° C. Also disclosed is a method of electrically attaching a discrete device to a substrate that includes placing the device on the substrate, applying conductive ink that connects at least one terminal on the device to at least one contact on the substrate and curing the conductive ink. Also disclosed is an IC package with a discrete electrical device having electrical terminals; an electrical substrate having contact pads on a surface thereof; and cured conductive ink connecting at least one of the electrical terminals with at least one of the contact pads.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Sreenivasan K. Koduri
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Publication number: 20140124940Abstract: Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each non-linear compliant spring may include one or more routing segments. The semiconductor device may be mounted to a circuit board by the bump interconnects. When the semiconductor device operates, heat may be generated by the semiconductor device, causing thermal expansion by the semiconductor device and the circuit board. The semiconductor device and circuit board may expand by different amounts due to differences in their thermal coefficients of expansion. The non-linear compliant springs provide for compliance between the conductive pads and bump interconnects to allow for the different rates of expansion.Type: ApplicationFiled: December 13, 2012Publication date: May 8, 2014Applicant: Broadcom CorporationInventors: Milind S. Bhagavat, Javed Iqbal Sandhu, Rezaur Rahman Khan, Teck Yang Tan
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Publication number: 20140124941Abstract: A semiconductor device includes a first base material having a first surface; a second base material having a coefficient of linear expansion different from that of the first base material, being in contact with the first base material, and having a second surface being adjacent to the first surface; and a first interconnect formed over the first and second surfaces to straddle a borderline between the first and second base materials. The cross-sectional area of the first interconnect along the borderline is greater than the cross-sectional area of at least part of a portion of the first interconnect on the first surface along a width of the first interconnect, or the cross-sectional area of at least part of a portion of the first interconnect on the second surface along the width of the first interconnect.Type: ApplicationFiled: January 8, 2014Publication date: May 8, 2014Applicant: Panasonic CorporationInventor: TAKESHI SAKAMOTO
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Publication number: 20140124942Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Inventors: Damion T. Searls, Edward P. Osburn
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Publication number: 20140124943Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, John E. Sheets, II
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Publication number: 20140124944Abstract: Embodiments of the invention generally relate to package substrates for integrated circuits. The package substrates each include a core having electrically conductive vias therethrough. Build-up layers formed from dielectric materials having different compositions are disposed around the core and include interconnects formed therein for facilitating electrical connections between integrated circuits coupled to the package substrate. The dielectric materials are selected to allow finer interconnect geometries where desired, and to increase the rigidity, and thus planarity, of the package substrate. Exemplary dielectric materials include pre-impregnated composite fibers for increasing the rigidity of a package substrate, and Ajinomoto Build-up Film for allowing the formation finer interconnect geometries.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: NVIDIA CORPORATIONInventors: Leilei ZHANG, Zuhair BOKHAREY
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Publication number: 20140124945Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure, comprising a plurality of conductive strips and a plurality of insulating strips, is formed on a substrate, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively. The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Erh-Kun Lai, Yen-Hao Shih, Shih-Chang Tsai
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Publication number: 20140124946Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal such that the metal is recessed with respect to at least one of the active side and the inactive side and does not entirely fill the TSVs; defining capture pad areas on the at least one of the active side and inactive side adjacent to the recessed TSVs; filling the capture pad areas and recessed TSVs with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs. Also disclosed is a semiconductor substrate having a capture pad.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, Gary Lafontant, Kevin S. Petrarca, Richard P. Volant
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Publication number: 20140124947Abstract: Methods and apparatus for flip chip substrates with guard rings. An embodiment comprises a substrate core with a die attach region for attaching an integrated circuit die; at least one dielectric layer overlying a die side surface of the substrate core; and at least one guard ring formed adjacent a corner of the substrate core, the at least one guard ring comprising: a first trace overlying the dielectric layer having rectangular portions extending in two directions from the corner of the substrate core and in parallel to the edges of the substrate core; a second trace underlying the dielectric layer; and at least one via extending through the dielectric layer and coupling the first and second traces; wherein the first trace, the at least one via, and the second trace form a vertical via stack. Methods for forming the flip chip substrates with the guard rings are disclosed.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chita Chuang, Yao-Chun Chuang, Chen-Cheng Kuo, Chen-Shien Chen
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Publication number: 20140124948Abstract: A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.Type: ApplicationFiled: November 12, 2012Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Minhua Lu, Eric Daniel Perfecto
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Publication number: 20140124949Abstract: Provided are a semiconductor device and a method of manufacturing the same. The method may, for example, comprise forming an interposer on a dummy substrate; forming a conductive pillar on the interposer; contacting the top of the interposer with at least one semiconductor die; encapsulating the conductive pillar and the at least one semiconductor die with an encapsulant; forming a redistribution layer that is electrically connected to the conductive pillar, on the semiconductor die; removing the dummy substrate from the interposer; attaching the interposer, which has the at least one semiconductor die in contact, to a substrate and testing the at least one semiconductor die; and contacting a stacked semiconductor device with the redistribution layer.Type: ApplicationFiled: January 29, 2013Publication date: May 8, 2014Inventors: Jong Sik Paek, Doo Hyun Park
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Publication number: 20140124950Abstract: A semiconductor substrate is disclosed. The semiconductor substrate includes a substrate body having at least an opening formed on a surface thereof, wherein the surface of the substrate body and a wall of the opening are made of an insulating material; and a circuit layer formed on the surface of the substrate body, wherein the circuit layer covers an end of the opening and is electrically insulated from the opening. The opening facilitates to increase the thickness of the insulating structure between the circuit layer and the substrate body of a silicon material to prevent signal degradation when high frequency signals are applied to the circuit layer.Type: ApplicationFiled: January 30, 2013Publication date: May 8, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Bo-Shiang Fang, Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang, Li-Fang Lin
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Publication number: 20140124951Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.Type: ApplicationFiled: August 29, 2013Publication date: May 8, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Woon-Seob Lee, Sin-Woo Kang, Ki-Young Yun, Sung-Dong Cho, Eun-Ji Kim, Yeong-Lyeol Park
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Publication number: 20140124952Abstract: An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.Type: ApplicationFiled: January 7, 2014Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naoyoshi KUSABA, Oh-jung KWON, Zhengwen LI, Hongwen YAN
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Publication number: 20140124953Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips electrically connected and stacked. Each of the semiconductor chips trims a voltage level used in the semiconductor chip in response to a chip select signal.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: SK hynix Inc.Inventors: Byung Deuk JEON, Nam Pyo HONG
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Publication number: 20140124954Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Richard P. Volant
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Publication number: 20140124955Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.Type: ApplicationFiled: November 8, 2012Publication date: May 8, 2014Inventors: Meng-Tse CHEN, Kuei-Wei HUANG, Tsai-Tsung TSAI, Ai-Tee ANG, Ming-Da CHENG, Chung-Shi LIU
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Publication number: 20140124956Abstract: A semiconductor package includes one or more semiconductor stack structures mounted on a package board. The semiconductor stack structures include sequentially stacked first to fourth semiconductor devices. Each of the first to fourth semiconductor devices includes a first unit semiconductor chip and a second unit semiconductor chip. The first unit semiconductor chip and the second unit semiconductor chip are unitary. A method for fabricating the semiconductor package includes forming pairs of unit semiconductor chips on a wafer, forming a scribe lane between the pairs of unit semiconductor chips, separating the pairs of unit semiconductor chips into semiconductor devices, each of the semiconductor devices having a corresponding one pair of unit semiconductor chips.Type: ApplicationFiled: September 16, 2013Publication date: May 8, 2014Applicant: Samsung Electronics Co., Ltd.Inventor: IN LEE
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Publication number: 20140124957Abstract: A semiconductor device includes: a first semiconductor chip having a surface provided with first electrodes; and an expanded semiconductor chip including a second semiconductor chip and an expanded portion extending outward from at least one side surface of the second semiconductor chip. The expanded semiconductor chip has a surface provided with second electrodes. The surface of the first semiconductor chip provided with the first electrodes faces the surface of the expanded semiconductor chip provided with the second electrodes so that the first electrodes are connected to the second electrodes. Each one of the second electrodes that is connected to an associated one of the first electrodes is located only on the expanded portion.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: PANASONIC CORPORATIONInventors: TEPPEI IWASE, KIYOMI HAGIHARA
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Publication number: 20140124958Abstract: A method (80) entails providing (82) a structure (117), providing (100) a controller element (102, 24), and bonding (116) the controller element to an outer surface (52, 64) of the structure. The structure includes a sensor wafer (92) and a cap wafer (94) Inner surfaces (34, 36) of the wafers (92, 94) are coupled together, with sensors (30) interposed between the wafers. One wafer (94, 92) includes a substrate portion (40, 76) with bond pads (42) formed on its inner surface (34, 36). The other wafer (94, 92) conceals the substrate portion (40, 76). After bonding, methodology (80) entails forming (120) conductive elements (60) on the element (102, 24), removing (126) material sections (96, 98, 107) from the wafers to expose the bond pads, forming (130) electrical interconnects (56), applying (134) packaging material (64), and singulating (138) to produce sensor packages (20, 70).Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Philip H. Bowles, Paige M. Holm, Stephen R. Hooper, Raymond M. Roop
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Publication number: 20140124959Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Atsushi IIJIMA
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Publication number: 20140124960Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Suan Jeung Boon, Meow Koon Eng, Yong Poo Chia