Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins.

Abstract: A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses.

Abstract: A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole.

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Abstract: An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.

Abstract: A semiconductor device may include a substrate, source and drain regions in the substrate, a recessed epitaxial channel layer in the substrate between the source and drain regions, and a high-K gate dielectric layer overlying the recessed epitaxial channel layer. The semiconductor device may further include a gate electrode overlying the high-K gate dielectric layer, a dielectric cap layer in contact with top and sidewall portions of the gate electrode, the dielectric cap layer having a lower dielectric constant than the high-K gate dielectric layer, and source and drain contacts coupled to the source and drain regions.

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract: A nitride semiconductor device includes: first electrode interconnect layers extending in parallel with one another over the nitride semiconductor layer and divided by areas extending across a longitudinal direction of the first electrode interconnect layers; first gate electrodes extending along the first electrode interconnect layers; first gate electrode connecting interconnects extending in associated ones of the areas dividing the first electrode interconnect layers and being in connection to the first gate electrodes; first electrode connecting interconnects formed above the first gate electrode connecting interconnects and being in connection to the first electrode interconnect layers; a first electrode upper interconnects formed on the first electrode connecting interconnects with an interconnect insulating film interposed therebetween, and being in connection to the first electrode connecting interconnects through associated ones of openings of the interconnect insulating film.

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract: A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.

Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate. The gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN layer. The metal layer includes aluminum.

Abstract: A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier.

Abstract: A conductive interconnect includes an inorganic collar. The conductive interconnect includes a conductive support layer. The conductive interconnect also includes a conductive material on the conductive support layer. The conductive interconnect further includes an inorganic collar partially surrounding the conductive material. The inorganic collar is also disposed on sidewalls of the conductive support layer.

Abstract: A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density.

Abstract: A packaging concept for MEMS components having at least one diaphragm structure formed in the front side of the component is provided, according to which the MEMS component is mounted on a support which at least laterally delimits a cavity adjoining the diaphragm structure. In addition, at least one electrical feedthrough is formed in the support which allows electrical contacting of the MEMS component through the support. To achieve the largest possible rear volume for the diaphragm structure of the MEMS component for a given chip surface area, and also to simplify the processing of the support, according to the invention the electrical feedthroughs are integrated into the wall of the cavity adjoining the diaphragm structure, in that at least one section of such a feedthrough is implemented in the form of an electrically conductive coating of a side wall section of the cavity.

Abstract: A magnetic random access memory (MRAM) device includes at least one read line, at least one write line and a tunnel junction extending from the at least one read line toward the at least one write line. A heating line is connected to an opposite end of the tunnel junction from the at least one read line. The heating line is configured to supply heat to the tunnel junction to heat the tunnel junction based on current flowing through the heating line.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.

Abstract: Embodiments of the invention implement MEJs having improved read-write characteristics. In one embodiment, an MEJ includes: ferromagnetic fixed and free layers, a dielectric layer interposed between the ferromagnetic layers, and an additional dielectric layer proximate the free layer, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when subject to a potential difference, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, compared to the strength of the magnetic anisotropy along the first easy axis, is magnified during the application of the potential difference, where the extent of the magnification is enhanced by the presence of the additional layer.

Abstract: The semiconductor storage device includes a memory cell array region in which a plurality of storing MTJ elements capable of changing resistance depending on a direction of magnetization are arranged on a semiconductor substrate. The semiconductor storage device includes a resistive element region in which a plurality of resisting MTJ elements are arranged on the semiconductor substrate along a first direction and a second direction perpendicular to the first direction. An area of a first cross section of the resisting MTJ element parallel with an upper surface of the semiconductor substrate is larger than an area of a second cross section of the storing MTJ element parallel with the upper surface of the semiconductor substrate.

Abstract: According to one embodiment, a semiconductor storage device is disclosed. The device includes first magnetic layer, second magnetic layer, first nonmagnetic layer between them. The first magnetic layer includes a structure in which first magnetic material film, second magnetic material film, and nonmagnetic material film between the first and second magnetic material films are stacked. The first magnetic material film is nearest to the first nonmagnetic layer in the first magnetic layer. The nonmagnetic material film includes at least one of Ta, Ar, Nb, Mo, Ru, Ti, V, Cr, W, Hf. The second magnetic material film includes a stacked materials, including first magnetic material nearest to the first nonmagnetic layer among the stacked materials, and second magnetic material which is same magnetic material as the first magnetic material and has smaller thickness than the first magnetic material.

Abstract: Provided is a diode element, a detecting device, and the like which solve problems of a conventional lateral diode element. In the conventional element, a semiconductor interface appears in current path between two electrodes on a surface thereof, and thus noise caused by the interface is large. The diode element includes: a first-conductive-type low carrier concentration layer; a first-conductive-type high carrier concentration layer; and a Schottky electrode and an ohmic electrode which are formed on a semiconductor surface. The low carrier layer has a carrier concentration that is lower than that of the high carrier layer. The diode element includes a first-conductive-type impurity introducing region formed below the ohmic electrode, and includes a second-conductive-type impurity introducing region so as not to be in electrical contact with the Schottky electrode on the semiconductor surface between the Schottky and the ohmic.

Abstract: The present invention provides a module structure comprising a substrate with a partial pierced region. A main chip has a sensing area. At least one component is included, wherein the main chip, the at least one component and the substrate are located at the same level. A holder is disposed on the substrate. A transparent material is disposed on the holder, substantially aligning to the sensing area. A lens holder is disposed on the holder, and a lens is configured on the lens holder, substantially aligning to the transparent material and the sensing area.

Abstract: An image sensor having a pixel region, a logic region, and an analog region, that includes a photodiode region in a substrate in the pixel region, an insulating layer on the substrate containing a zero wiring layer in the pixel region, a first wiring layer in the pixel region, the logic region, and the analog region, and a second wiring layer in the logic region and the analog region, a first trench in a portion of the insulating layer in the pixel region, second trenches in a bottom of the first trench to match to the photodiode region, color filter layers in respective second trenches, and microlenses on respective color filter layers.

Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.

Abstract: According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature.

Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.

Abstract: A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase in reliability and stability of the semiconductor device. A semiconductor device includes a line pattern formed over a semiconductor substrate, a device isolation film formed at a center part of the line pattern, a contact part formed at both sides of the line pattern, configured to include an oxide film formed over the line pattern, and a bit line formed at a bottom part between the line patterns, and connected to the contact part.

Abstract: An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region.

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion.

Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.

Abstract: Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant may include arsenic (As). In an embodiment, a dopant solution is provided that includes a solvent and a dopant. In a particular embodiment, the dopant solution may have a flashpoint that is at least approximately equal to a minimum temperature capable of causing atoms at a surface of the substrate to attach to an arsenic-containing compound of the dopant solution. In one embodiment, a number of silicon atoms at a surface of the substrate are covalently bonded to the arsenic-containing compound.

Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.

Abstract: Manufacturing-friendly and scalable methods for the production of silicon micro- and nanostructures, including silicon nanotubes, are described. The inventive methods utilize conventional integrated circuit and MEMS manufacturing processes, including spin-coating, photolithography, wet and dry silicon etching, and photoassisted electrochemical etch processes. The invention also provides a novel mask, for maximizing the number of tubes obtained per surface area unit of the silicon substrate on which the tubes are built. The resulting tubes have thick and straight outer walls, as well as high aspect ratios.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.

Abstract: A semiconductor device comprises a substrate, a cathode, an outer ring, an anode, an electrically insulating layer, and an electrically conducting layer. The substrate includes a semiconducting material having a first conduction type. The substrate has a first face and a second face substantially parallel to the first face. A cathode is disposed at the second face and has the first conduction type. An outer ring, having the first conduction type, is disposed at an outer perimeter of the first face of the substrate. An anode, having the second conduction type, is disposed at the first face of the substrate within an inner perimeter of the outer ring. An electrically insulating layer is disposed over the outer ring. An electrically conducting layer is disposed over the electrically insulating layer and over the outer ring. The electrically conducting layer electrically is insulated from the outer ring by the electrically insulating layer.

Abstract: A semiconductor package includes a mounting substrate having a chip-mounting region and a peripheral region. A first semiconductor chip is mounted on the chip-mounting region of the mounting substrate. A first molding member covers at least a portion of the first semiconductor chip on the mounting substrate. A plurality of first conductive connection members penetrate through at least a portion of the first molding member to protrude from the first molding member. The first conductive connection members are electrically connected to a plurality of ground connection pads provided on the peripheral region of the mounting substrate, respectively. An electromagnetic interference (EMI) shield member is disposed on an upper surface of the first molding member to cover the first semiconductor chip. The EMI shield member is supported by the first conductive molding members and spaced apart from the first molding member.

Abstract: A semiconductor package includes a mounting substrate having a chip-mounting region and a peripheral region, a first semiconductor chip mounted on the chip-mounting region of the mounting substrate, a first molding member on the mounting substrate to cover at least a portion of the first semiconductor chip, a plurality of first conductive connection members penetrating at least a portion of the first molding member, the first conductive connection members electrically connected to a plurality of ground connection pads provided on the peripheral region of the mounting substrate, respectively, and an electromagnetic interference (EMI) shield member covering the first semiconductor chip and including a graphite layer electrically connected to the first conductive connection members.

Abstract: A compact high frequency switch needing no external control signal is obtained. The high frequency switch includes an anti-parallel diode (first anti-parallel diode) having one end and another end coupled with an antenna terminal (first high-frequency-signal input/output terminal) and a transmitting terminal (second high-frequency-signal input/output terminal), respectively, and becoming a conduction state in the input power not less than predetermined high frequency power. When the high frequency switch is an SPDT type, such a switch may include a ¼-wavelength line in the use frequency of the high frequency switch having one end and another end coupled with the antenna terminal and a receiving terminal (third high-frequency-signal input/output terminal), respectively, and an anti-parallel diode (second anti-parallel diode) coupled between the receiving terminal and a ground and becoming a conduction state in the input power not less than predetermined high frequency power.

Abstract: According to one embodiment, a semiconductor device includes a first electrical conductor, a second electrical conductor, first and second semiconductors between the first and second electrical conductors, a first power terminal, a second power terminal, a signal terminal, and an insulator which covers the components. The insulator includes a flat bottom surface in which the first and second electrical conductors are exposed, a ceiling surface, a first end surface, and a second end surface. The power terminals and the signal terminal extend outwardly from the first and second end surfaces, and the ceiling surface, respectively. The first end surface, the ceiling surface, and the second end surface are formed with a parting line.

Abstract: Semiconductor packages and methods of forming the same may be provided. According to the semiconductor package of the present inventive concepts, a bump attached to and protruded from a bonding pad on a surface of a semiconductor chip is inserted into a through-hole defined in a package substrate. As a result, a thickness of the semiconductor package may be reduced by at least a height of the bump. Because an empty space does not exist between a semiconductor chip and the package substrate, the semiconductor package does not need a conventional underfill resin layer. Accordingly, processes of forming the semiconductor package may be simplified.