Patents Issued in March 31, 2016
  • Publication number: 20160093635
    Abstract: A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Peter RABKIN, Jilin XIA, Jayavel PACHAMUTHU
  • Publication number: 20160093636
    Abstract: Techniques are provided for fabricating a three-dimensional, charge-trapping memory device with improved long term data retention. A corresponding three-dimensional, charge-trapping memory device is also provided which includes a stack of alternating word line layers and dielectric layers. A charge-trapping layer is deposited in a memory hole. The refractive index of portions of the charge-trapping layer which are adjacent to the word line layers is increased relative to the refractive index of portions of the charge-trapping layer which are adjacent to the dielectric layers. This can be achieved by doping the portions of the charge-trapping layer which are adjacent to the word line layers. In one approach, the charge-trapping layer is SiON and is doped with Si or N. In another approach, the charge-trapping layer is HfO and is doped with Hf. In another approach, the charge-trapping layer is HfSiON and is doped with Hf, Si or N.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Liang Pang, Yingda Dong, Jayavel Pachamuthu
  • Publication number: 20160093637
    Abstract: A method of fabricating a memory device includes alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, forming a channel hole by etching the insulating layers and the sacrificial layers to expose a partial region of the substrate, forming a channel structure in the channel hole, forming an opening by etching the insulating layers and the sacrificial layers to exposed a portion of the substrate, forming a plurality of side openings that include first side openings and a second side opening by removing the sacrificial layers through the opening, forming gate electrodes to fill the first side openings, and forming a blocking layer to fill the second side opening.
    Type: Application
    Filed: August 21, 2015
    Publication date: March 31, 2016
    Inventors: Jae-goo LEE, Young-woo PARK
  • Publication number: 20160093638
    Abstract: An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region.
    Type: Application
    Filed: December 3, 2015
    Publication date: March 31, 2016
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20160093639
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Application
    Filed: December 10, 2015
    Publication date: March 31, 2016
    Inventors: PIERRE MORIN, QING LIU, NICOLAS LOUBET
  • Publication number: 20160093640
    Abstract: Provided is a display device, including: a plurality of gate lines extending in a first direction; a plurality of source lines extending in a second direction; a gate driver configured to output a gate signal; and a plurality of gate lead-out lines extending in the second direction and being configured to transmit the gate signal to the plurality of gate lines, in which each of the plurality of gate lines is electrically connected to at least one of the plurality of gate lead-out lines, and at least one of the plurality of gate lines is electrically connected to at least two of the plurality of gate lead-out lines.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 31, 2016
    Inventors: Tetsuya KAWAMURA, Hironori YASUKAWA
  • Publication number: 20160093641
    Abstract: A semiconductor device capable of detecting a minute current with high accuracy is provided. The semiconductor device includes a first circuit, a second circuit, a first transistor, and a second transistor. A first analog signal is input to the first circuit via the first transistor. A second analog signal is input to the first circuit via the second transistor. The first analog signal includes a value of a first current. The second analog signal includes a value of a second current. The first circuit is capable of converting the first analog signal into a first digital signal. The second circuit is capable of generating a second digital signal based on the first digital signal. The first circuit is capable of converting the second analog signal into a third digital signal based on the second digital signal. The first or second transistor includes an oxide semiconductor in a channel.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 31, 2016
    Inventor: Kei TAKAHASHI
  • Publication number: 20160093642
    Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 31, 2016
    Inventors: Atsuo ISOBE, Yutaka OKAZAKI, Kazuya HANAOKA, Shinya SASAGAWA, Motomu KURATA
  • Publication number: 20160093643
    Abstract: An oxide semiconductor transistor used in a pixel element of a display device and a method of manufacturing the same are disclosed. The oxide semiconductor transistor used in a pixel element of a display device comprises a substrate, a first gate electrode located on the substrate, a source electrode and a drain electrode located on the first gate electrode and a second gate electrode located on the source electrode and the drain electrode. Here, the first gate electrode is electrically connected to the second gate electrode, the same voltage is applied to the first gate electrode and the second gate electrode, and a width of the second gate electrode is shorter than a length between the source electrode and the drain electrode.
    Type: Application
    Filed: December 10, 2015
    Publication date: March 31, 2016
    Inventors: Jin Jang, Man Ju Seok, Jae Gwang Um, Su Hui Lee
  • Publication number: 20160093644
    Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Yunho Ki, SieHyug Choi, YoungMin Yu, Sungwoo Kim, YoonDong Cho, SeYeoul Kwon
  • Publication number: 20160093645
    Abstract: A display panel and a display are disclosed. A display panel has an active area and a peripheral area disposed adjacent to the active area and comprises a first substrate, a second substrate, a first insulating layer, a second insulating layer and an organic layer. The second substrate is disposed opposite the first substrate. The first insulating layer is disposed on the side of the first substrate facing the second substrate. The organic layer covers the first insulating layer. The second insulating layer covers the organic layer and includes at least a first opening which is disposed in the peripheral area and exposes the organic layer.
    Type: Application
    Filed: June 25, 2015
    Publication date: March 31, 2016
    Inventors: Kuan-Feng LEE, Jung-Fang CHANG
  • Publication number: 20160093646
    Abstract: A thin film transistor (TFT) substrate, a flat display apparatus including the TFT substrate, a method of manufacturing the TFT substrate, and a method of manufacturing the flat display apparatus, the thin film transistor (TFT) substrate including a substrate; a first gate electrode on the substrate, the first gate electrode including a first branch electrode and a second branch electrode that are spaced apart from one another; a polysilicon layer on the first gate electrode and insulated from the first gate electrode; and a second gate electrode on the polysilicon layer, the second gate electrode being insulated from the polysilicon layer and overlying the first and second branch electrodes.
    Type: Application
    Filed: April 17, 2015
    Publication date: March 31, 2016
    Inventors: Myounggeun CHA, Dongjo KIM, Yoonho KHANG, Myounghwa KIM, Kyoungwon LEE
  • Publication number: 20160093647
    Abstract: A thin film transistor (TFT) substrate is disclosed. The TFT substrate includes a substrate, a blocking layer, a source electrode, and a drain electrode on a same layer over the substrate, an active layer overlapping the blocking layer, the source electrode, and the drain electrode, a gate insulation layer over the active layer, a first gate electrode over the gate insulation layer, an interlayer dielectric over the first gate electrode, a first connection electrode over the interlayer dielectric and connected to the active layer and the source electrode through a first contact hole, a second connection electrode over the interlayer dielectric and connected to the active layer and the drain electrode through a second contact hole, a planarization layer over the first connection electrode and the second connection electrode, and a pixel electrode over the planarization layer and connected to the second connection electrode through a third contact hole.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 31, 2016
    Inventors: Hyun Ho KIM, Woo Joon KIM
  • Publication number: 20160093648
    Abstract: The silicon-based photomultiplier device comprises a substrate (1), a first layer (2) of a first conductivity type, a second layer (3) of a second conductivity type formed on the first layer, wherein the first layer (2) and the second layer (3) form a p-n junction, wherein the first layer (2) and the second layer (3) are disposed on or above the substrate (1). A material layer (15) between the substrate (1) and the first layer (2) fulfils the function of a light absorber, thereby efficiently suppressing crosstalk between adjacent cells of the device. Material layer (15) may further serve as an electrode for readout of electrical signals from the device.
    Type: Application
    Filed: April 16, 2014
    Publication date: March 31, 2016
    Inventors: Razmik Mirzoyan, Masahiro Teshima, Elena Popova
  • Publication number: 20160093649
    Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; providing a gate material layer that overlaps the substrate; providing a blocking layer that partially covers the gate material layer; removing a portion of the gate material layer that is not covered by the blocking layer for forming a gate electrode; providing a blocking material layer that covers both the blocking layer and the substrate; removing a portion of the blocking material layer for forming a blocking member that has an opening, wherein the opening partially exposes the blocking layer and partially exposes the substrate; and performing ion implantation through the opening to form a doped well region in the substrate.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 31, 2016
    Inventors: Xuemei WANG, Fugang CHEN, Shuaibing LIN, Feng HUANG
  • Publication number: 20160093650
    Abstract: An imaging device includes a first pixel electrode, a second pixel electrode adjacent to the first pixel electrode, and a photoelectric conversion film continuously covering the first pixel electrode and the second pixel electrode, in which an insulating film is provided between the first pixel electrode and the photoelectric conversion film, and between the second pixel electrode and the photoelectric conversion film, and an intermediate electrode is provided in a position between the first pixel electrode and the second pixel electrode, the intermediate electrode being in contact with a surface of the photoelectric conversion film, the surface being on a side where the first and second pixel electrodes are arranged.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 31, 2016
    Inventors: Sho Suzuki, Tatsuya Ryoki
  • Publication number: 20160093651
    Abstract: The present disclosure relates to a solid-state imaging device, an electronic apparatus, and a manufacturing method that are designed to further increase conversion efficiency. A solid-state imaging device includes a pixel in which element separation is realized by a first trench element separation region having a trench structure in a region between an FD unit and an amplifying transistor among element separation elements separating the elements constituting the pixel from one another, and a second trench element separation region having a trench structure in a region other than the region between the FD unit and the amplifying transistor among the element separation regions separating the elements constituting the pixel from one another, and the first trench element separation region is deeper than the second trench element separation region. The present technology can be applied to CMOS image sensors, for example.
    Type: Application
    Filed: May 19, 2014
    Publication date: March 31, 2016
    Inventor: Naoyuki SATO
  • Publication number: 20160093652
    Abstract: An imaging device which offers an image with high quality and is suitable for high-speed operation is provided. The imaging device includes a first region to an n-th region (n is a natural number of 2 or more and 16 or less) each including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first to third circuits each include a transistor in which silicon is used in an active layer or an active region. The fourth circuit includes a photoelectric conversion element and a transistor in which an oxide semiconductor is used in an active layer. The first circuit includes a region overlapping with the fourth circuit. The third circuit includes a region overlapping with the fourth circuit.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 31, 2016
    Inventors: Takayuki IKEDA, Yoshiyuki KUROKAWA
  • Publication number: 20160093653
    Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Applicant: Sony Corporation
    Inventors: Keiji Tatani, Fumihiko Koga, Takashi Nagano
  • Publication number: 20160093654
    Abstract: An image sensor includes a photoelectric conversion element suitable for generating photocharges corresponding to incident light, a transfer transistor suitable for transferring the generated photocharges to a floating diffusion node based on a transfer signal, and a reset transistor suitable for resetting the floating diffusion node based on a reset signal and including a memory gate.
    Type: Application
    Filed: December 10, 2014
    Publication date: March 31, 2016
    Inventor: Do-Hwan KIM
  • Publication number: 20160093655
    Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.
    Type: Application
    Filed: December 10, 2015
    Publication date: March 31, 2016
    Inventor: LESTER J. KOZLOWSKI
  • Publication number: 20160093656
    Abstract: An image sensor device includes a top substrate and a subassembly. The top substrate includes a plurality of connection pillars, and the subassembly includes a plurality of connection pads. The connection pillars on the top substrate are bonded to the connection pads in the subassembly. The connection pillars are formed of a first metal and the connection pads are formed of a second metal.
    Type: Application
    Filed: April 21, 2015
    Publication date: March 31, 2016
    Inventors: HaiFang ZHANG, Herb He HUANG, Xuan Jie LIU, Xia FENG, Pinghuan WU
  • Publication number: 20160093657
    Abstract: A photoelectric conversion device includes a photoelectric conversion unit disposed above a substrate and a reading circuit. The photoelectric conversion unit includes a first electrode disposed above the substrate, a second electrode disposed above the first electrode, and a photoelectric conversion film disposed between the first electrode and the second electrode. The second electrode includes an opening, and is disposed in contact with the photoelectric conversion film at a boundary between adjacent photoelectric conversion units. An insulating film is disposed in contact with the second electrode.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 31, 2016
    Inventor: Tatsuya Ryoki
  • Publication number: 20160093658
    Abstract: An image-sensor structure is provided. The image-sensor structure includes a substrate, a plurality of photoelectric conversion units formed in the substrate, a plurality of separated color filters formed above the substrate and the photoelectric conversion units, a first light shielding layer surrounding the separated color filters, and a first conductive polymer element blended with a low-refractive-index component filled between the individual separated color filters and between the all separated color filters and the first light shielding layer, wherein the first conductive polymer element is electrically connected to a grounding pad.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Chung-Jung HSU, Chin-Chuan HSIEH, Zong-Ru TU
  • Publication number: 20160093659
    Abstract: There is provided a solid-state image pickup device including: a semiconductor substrate (21); a photodiode (11A, 11B) formed in the semiconductor substrate; a transistor (10) having a gate electrode (14) part or all of which is embedded in the semiconductor substrate, the transistor being configured to read a signal electric charge from the photodiode via the gate electrode; and an electric charge transfer layer (13) provided between the gate electrode and the photodiode.
    Type: Application
    Filed: May 9, 2014
    Publication date: March 31, 2016
    Inventors: Ryosuke NAKAMURA, Fumihiko KOGA, Taiichiro WATANABE
  • Publication number: 20160093660
    Abstract: A semiconductor apparatus includes: an MOS type field effect transistor formed on a semiconductor substrate and having a first gate electrode set at a predetermined impurity concentration; and a charge modulation device formed on the semiconductor substrate and having a second gate electrode set at a predetermined impurity concentration lower than the impurity concentration of the first gate electrode.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 31, 2016
    Inventor: Kunio Anzai
  • Publication number: 20160093661
    Abstract: The invention relates to the field of semiconductor manufacturing process, more particularly, to an image sensor having an embedded color filter and its preparation method, providing a bonded wafer with leads, and performing preparation process of metal insulated gates and embedding process of color filters on bonded wafers, etching to expose the opening of the lead, and eventually combining color filter process with lead process; the implementation of the invention is simple, implementation difficulty is relatively small, and can greatly improve the transmission speed of output image signal and image quality, at the same time, the technical scheme can be used in front-illuminated, back-illuminated and stackable image sensors, etc.
    Type: Application
    Filed: July 29, 2015
    Publication date: March 31, 2016
    Inventors: Siping Hu, Jifeng Zhu, Sheng'an Xiao, Jinwen Dong
  • Publication number: 20160093662
    Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 31, 2016
    Applicants: STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Michel Marty, Laurent Frey
  • Publication number: 20160093663
    Abstract: The invention relates to the field of semiconductor, more particularly, to a preparation process of image sensors, comprising: Step S1, providing a semiconductor structure, a top of which is provided with a groove, and leads being formed in said groove, the top of said semiconductor structure and an exposed surface of said groove are covered with a first dielectric layer; Step S2: depositing a second dielectric layer covering the upper surface of said first dielectric layer and said leads and filling said groove; Step S3: performing a reversed-etching process to thin said second dielectric layer, and to form a convex structure on a surface of said second dielectric layer above the groove; Step S4: performing a planarization process to said second dielectric layer to improve surface evenness of said second dielectric layer after grinding by the convex structure.
    Type: Application
    Filed: July 30, 2015
    Publication date: March 31, 2016
    Inventors: Siping HU, Jifeng ZHU, Sheng'an XIAO, Jinwen DONG
  • Publication number: 20160093664
    Abstract: A pixel cell includes a photodiode coupled to photogenerate image charge in response to incident light. A deep trench isolation structure is disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure. An amplifier transistor is coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure. A row select transistor is coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Johannes Solhusvik, Dominic Massetti
  • Publication number: 20160093665
    Abstract: A set of light emitting devices can be formed on a substrate. A growth mask having a first aperture in a first area and a second aperture in a second area is formed on a substrate. A first nanowire and a second nanowire are formed in the first and second apertures, respectively. The first nanowire includes a first active region having a first band gap and a second active region having a second band gap. The first band gap is greater than the second band gap. The second nanowire includes an active region having the first band gap and does not include, or is adjoined to, any material having the second band gap.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 31, 2016
    Inventors: Martin SCHUBERT, Daniel Bryce THOMPSON, Michael GRUNDMANN, Nathan GARDNER
  • Publication number: 20160093666
    Abstract: The invention relates to an optoelectronic device (50) including: a semiconductor substrate (14) doped with a first conductivity type; semiconductor contact pads (54) or a semiconductor layer, in contact with a surface of the substrate, doped with a second conductivity type opposite to the first type; conical or frusto-conical wired semiconductor elements (26), doped with the first conductivity type, each element being in contact with one of the contact pads or with the layer; light-emitting semiconductor portions (30), each portion at least partially covering one of the semiconductor elements; and a circuit (S) for polarising the contact pads (54) or the layer. The contact pads or the layer are selected among: aluminium nitride, boron nitride, silicon carbide, magnesium nitride, gallium and magnesium nitride, or a combination of same and the nitride compounds thereof.
    Type: Application
    Filed: May 13, 2014
    Publication date: March 31, 2016
    Inventors: Philippe Gilet, Alexei Tchelnokov, Ivan Christophe Robin
  • Publication number: 20160093667
    Abstract: A light emitting structure includes lower and upper semiconductor layers having different conductive types, and an active layer disposed between the lower and upper semiconductor layers. The light emitting structure is provided on the substrate. A first electrode layer provided on the upper semiconductor layer includes a first adhesive layer and a first bonding layer overlapping each other. A reflective layer is not provided between the first adhesive layer and the first bonding layer.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Inventors: Byung Yeon CHOI, Hee Young Beom, Yong Gyeong Lee, Ji Hwan Lee, Hyun Seoung Ju, Gi Seok Hong
  • Publication number: 20160093668
    Abstract: Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Yu LU, Xia LI, Seung Hyuk KANG
  • Publication number: 20160093669
    Abstract: Magnetic memory devices may include a substrate, a circuit device on the substrate, a plurality of lower electrodes electrically connected to the circuit device, a magnetic tunnel junction (MTJ) structure commonly provided on the plurality of the lower electrodes, and a plurality of upper electrodes on the MTJ structure. The MTJ structure may include a plurality of magnetic material patterns and a plurality of insulation material patterns separating the magnetic material patterns from each other.
    Type: Application
    Filed: May 19, 2015
    Publication date: March 31, 2016
    Inventors: Sung-Chul LEE, Kwang-Seok KIM, Kee-Won KIM, Young-Man JANG, Ung-Hwan PI
  • Publication number: 20160093670
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer includes a first upper interconnect level with one or more metal lines in the memory cell region. A second upper dielectric layer is provided over the first upper dielectric layer. The second upper dielectric layer includes a via plug coupled to the metal line of the first upper interconnect level. An alignment trench which extends from a top surface of the second upper dielectric layer to a portion of the second upper dielectric layer is formed. Various layers of a MTJ stack are formed over the second upper dielectric layer. Profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 31, 2016
    Inventors: Yi JIANG, Wanbing YI, Juan Boon TAN, Danny Pak-Chum SHUM
  • Publication number: 20160093671
    Abstract: A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventor: ANIRBAN ROY
  • Publication number: 20160093672
    Abstract: Methods and apparatuses, wherein the method includes providing a logic device. The method substantially surrounds a metal gate with a transition metal oxide on at least one side, wherein the transition metal oxide is comprised of hafnium oxalate and silicon dioxide. The method provides a bottom electrode (BE), wherein the BE is comprised of at least one of silicon or tungsten.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Xia LI, Daniel Wayne PERRY, JR., Seung Hyuk KANG
  • Publication number: 20160093673
    Abstract: A semiconductor device includes a pillar-shaped resistance-changing layer on a contact and a reset gate insulating film that surrounds the pillar-shaped resistance-changing layer. A reset gate surrounds the reset gate insulating film, and the reset gate is electrically insulated from the pillar-shaped resistance-changing layer.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 31, 2016
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20160093674
    Abstract: According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.
    Type: Application
    Filed: February 18, 2015
    Publication date: March 31, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki ASAO
  • Publication number: 20160093675
    Abstract: An image sensor including a semiconductor substrate integrated with a plurality of photo-sensing devices and a nanopattern layer on the semiconductor substrate, the nanopattern layer having a plurality of nanopatterns, wherein a single nanopattern of the plurality of nanopatterns corresponds to a single photo-sensing device in the plurality of photo-sensing devices.
    Type: Application
    Filed: February 25, 2015
    Publication date: March 31, 2016
    Inventors: Gae Hwang LEE, Kwang Hee LEE, Dong-Seok LEEM, Yong Wan JIN
  • Publication number: 20160093676
    Abstract: A display panel includes an array substrate including a thin film transisitors array, a lighting device formed on a surface of the array substrate where the thin film transistors array is formed to emit a backlight, and a color conversion layer formed on a side of the array substrate opposite to the lighting device. The display panel defines a number of pixel areas, each of the pixel areas includes at least three sub-pixels to correspondingly emit lights with three-primary colors. The color conversion layer includes a number of quantum dot blocks corresponding to the sub-pixels to convert the backlight to the lights with three-primary colors.
    Type: Application
    Filed: December 12, 2014
    Publication date: March 31, 2016
    Inventors: I-WEI WU, JUNG-AN CHENG
  • Publication number: 20160093677
    Abstract: A color filter includes a first filtering part and a number of first quantum dot particles formed in the first filtering part. A color of the first filtering part is a first primary color. The first quantum dot particles convert a light having a wavelength less than a wavelength of the first primary color to a light with the first primary color.
    Type: Application
    Filed: December 18, 2014
    Publication date: March 31, 2016
    Inventor: SHIH-PIN TSENG
  • Publication number: 20160093678
    Abstract: To provide a novel light-emitting device with high productivity, the light-emitting device includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. In the first light-emitting element, a first lower electrode, a first transparent conductive layer, a first light-emitting layer, a second light-emitting layer, and an upper electrode are stacked in this order. In the second light-emitting element, a second lower electrode, a second transparent conductive layer, the first light-emitting layer, the second light-emitting layer, and the upper electrode are stacked in this order. In the third light-emitting element, a third lower electrode, a third transparent conductive layer, the second light-emitting layer, and the upper electrode are stacked in this order. The first transparent conductive layer includes a first region. The second transparent conductive layer includes a second region as thick as the third transparent conductive layer.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 31, 2016
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Ryohei YAMAOKA, Shogo UESAKA
  • Publication number: 20160093679
    Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate and a plurality of pixels formed over the substrate, each pixel including a first region from which light is emitted and a second region through which external light is transmitted. The display also includes a plurality of pixel circuit units each formed in the first region and including at least one thin-film transistor, an inorganic insulating film formed in the second region, a transparent conductive film formed over at least a portion of the inorganic insulating film, and an organic insulating film covering the pixel circuit units and at least a portion of the transparent conductive film. The display further includes a plurality of first electrodes formed over the organic insulating film and in the first regions of the pixels.
    Type: Application
    Filed: May 26, 2015
    Publication date: March 31, 2016
    Inventors: Sangho Moon, Sungho Kim, Sangkyung Lee
  • Publication number: 20160093680
    Abstract: An organic light emitting diode display device, and method of fabricating an organic light emitting diode display device are discussed. The organic light emitting diode display device according to one embodiment includes a first electrode on a thin film transistor and connected to a drain electrode; an auxiliary electrode on a same layer as the first electrode; a bank layer covering edges of the first electrode and edges of the auxiliary electrode and having a transmissive hole corresponding and an auxiliary contact hole; a light emitting layer on the first electrode in the transmissive hole; a residual layer on the auxiliary electrode in the auxiliary contact hole. A central portion of the residual layer has a larger thickness than an edge portion of the residual layer. The organic light emitting diode display device further includes a second electrode on the light emitting layer and the residual layer.
    Type: Application
    Filed: July 9, 2015
    Publication date: March 31, 2016
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Seung-Han PAEK, Hyo-Dae BAE, Young-Mu OH, Jeong-Won LEE, Heon-Il SONG, Jong-Hoon YEO
  • Publication number: 20160093681
    Abstract: There is provided a method of forming an active matrix electro-optical device, the method comprising providing a backplane comprising: a backplane substrate; a semiconductor particle formed separately from the backplane substrate and then fixed upon the backplane substrate at a predetermined position; the semiconductor particle planarized to remove portions of the semiconductor particle and to expose at a cross-section of the semiconductor particle a planar surface; and a controllable gated electronic component on or directly beneath the planar surface, the controllable gated electronic component configured to control one or more pixels of the electro-optical device. The method also comprises providing an optical portion comprising one or more pixel regions, the optical portion electrically connected to the backplane such that at least one of the pixel regions of the optical portion is electrically connected to the controllable gated electronic component.
    Type: Application
    Filed: October 9, 2015
    Publication date: March 31, 2016
    Inventor: Douglas R. DYKAAR
  • Publication number: 20160093682
    Abstract: A thin film encapsulation unit including an inorganic layer, a first organic layer on the inorganic layer and including a light-blocking unit and a light-transmitting unit, and a reflection-preventing layer on the first organic layer.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 31, 2016
    Inventors: Byoung-Duk Lee, Yun-Ah Chung, Yoon-Hyeung Cho
  • Publication number: 20160093683
    Abstract: A flexible display device and a method of manufacturing the same are provided. The flexible display device comprises a first flexible substrate including a display area including an organic light emitting layer, and a peripheral circuit area, and a second flexible substrate coming in contact with the first flexible substrate and including a pattern for facilitating bending thereof, wherein the second flexible substrate has a certain shape according to the pattern, and the first flexible substrate has a shape corresponding to the certain shape. Various embodiments of the present invention provide a flexible display device capable of realizing a narrow bezel-type or bezel-free display device and simultaneously realizing improved types of design, facilitating bending of a bezel area so as to realize a narrow bezel-type or bezel-free display device, and minimizing damage to an area to be bent.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 31, 2016
    Inventors: Chanwoo LEE, JongHyun PARK, TaeWoo KIM, Jaekyung CHOI, Sangcheon YOUN, SungJoon MIN, SeYeoul KWON, KwonHyung LEE
  • Publication number: 20160093684
    Abstract: Disclosed is a display device that includes a substrate having an active area and a dead area around the active area; an alignment mark on the inside surface of the substrate in a part of the dead area; and a light-shielding pattern on a rear surface of the substrate in the dead area, the light-shielding pattern including a mark hole for exposing the alignment mark. By providing the light-shielding pattern on a display surface in the dead area, the display device has expanded active display area and improved visual appreciation.
    Type: Application
    Filed: December 22, 2014
    Publication date: March 31, 2016
    Inventors: Seung-Hyun YOUK, Chul-Ho KIM, Nam-Kook KIM, Yun-Ho KOOK