Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.

Abstract: A fuse includes a body, a first conductive terminal coupled with a first end of the body, and a second conductive terminal coupled with a second end of the body. The body, the first conductive terminal, and the second conductive terminal define an exterior of the fuse. The fuse also includes an interruption assembly including a fusible element. The fusible element includes carbon fiber, is disposed on a conductive path between the first conductive terminal and the second conductive terminal, and is configured to break when a current through the fusible element exceeds a predetermined current.

Abstract: A method, apparatus, and system for protection from fires and electrical shock of components used in construction of electrical conduits is disclosed using non-electrical means to disrupt flow of electricity before an arc fault, with the purpose to disrupt flow of current before risk of arcing. The purpose of this invention is to remove the hazard before an electrical arc occurs.

Abstract: According to embodiments of the present invention, an electron device is provided. The electron device includes a support substrate, a conductive planar slow-wave structure on the support substrate, the conductive planar slow-wave structure being adapted to receive an electromagnetic wave signal for interaction with an electron beam, and a dielectric layer arrangement in between the conductive planar slow-wave structure and the support substrate, the dielectric layer arrangement being arranged on the support substrate at only one or more support substrate portions overlapping with the conductive planar slow-wave structure. According to further embodiments of the present invention, a method for manufacturing an electron device is also provided.

Abstract: According to one embodiment, an X-ray tube includes an elongated anode target, a cathode, and a vacuum envelope. The cathode includes an electron emission source and a converging electrode including a trench portion. The trench portion includes a closest inner circumferential wall, an upper inner circumferential wall, and a lower inner circumferential wall. The electron emission source projects towards a opening of the trench portion from a boundary between the closest inner circumferential wall and the upper inner circumferential wall.

Abstract: In one embodiment, a blanking aperture array includes a substrate including an upper surface on which an insulating film is provided, a plurality of blanking aperture portions provided in the substrate, each of the plurality of blanking aperture portions including one of penetration holes, through which a predetermined beam passes, and one of blanking electrodes and one of ground electrodes which are provided on the insulating film, and the blanking electrodes and the ground electrodes configured to perform blanking deflection of the predetermined beam, and a high-resistivity film provided so as to cover the insulating film and at least part of the ground electrodes, the high-resistivity film having an electric resistance that is higher than an electric resistance of the ground electrodes and lower than an electric resistance of the insulating film.

Abstract: Provided are an antenna, which is disposed in a vacuum chamber for generating an inductively coupled plasma, and a plasma processing device. The antenna and the plasma processing device suppress increase of the impedance even if the antenna is lengthened. An antenna 20 is disposed in a vacuum chamber 2 for generating an inductively coupled plasma 16 in the vacuum chamber 2 by applying a high frequency current. The antenna 20 includes an insulating pipe 22 and a hollow antenna body 24 which is disposed in the insulating pipe 22 and in which cooling water flows. The antenna body 24 has a structure that a plurality of metal pipes 26 are connected in series with a hollow insulator 28 interposed between the adjacent metal pipes 26, and each connecting portion has a sealing function with respect to vacuum and the cooling water.

Abstract: Disclosed is a method of processing a workpiece including a mask. The processing method includes: a first process of generating plasma of a first gas containing a silicon halide gas in a processing container of a plasma processing apparatus that accommodates a workpiece having a mask, to form a reactive precursor; a second process of purging a space in the processing container; a third process of generating plasma of a second gas containing oxygen gas in the processing container to form a silicon oxide film; and a fourth process of purging the space in the processing container. In the processing method, a sequence including the first to fourth processes is repeated.

Abstract: A system and method for reactive ion etching (RIE) system of a material is provided. The system includes a plasma chamber comprising a plasma source and a gas inlet, a diffusion chamber comprising a substrate holder for supporting a substrate with a surface comprising the material and a gas diffuser, and a source of a processing gas coupled to the gas diffuser. In the system and method, at least one radical of the processing gas is reactive with the material to perform etching of the material, the gas diffuser is configured to introduce the processing gas into the processing region, and the substrate holder comprises an electrode that can be selectively biased to draw ions generated by the plasma source into the processing region to interact with the at least one processing gas to generate the at least one radical at the surface.

Abstract: A method for processing substrate in a processing chamber, which has at least one plasma generating source and a gas source for providing process gas into the chamber, is provided. The method includes exciting the plasma generating source with an RF signal having RF frequency. The method further includes pulsing the gas source, using at least a first gas pulsing frequency, such that a first process gas is flowed into the chamber during a first portion of a gas pulsing period and a second process gas is flowed into the chamber during a second portion of the gas pulsing period, which is associated with the first gas pulsing frequency. The second process gas has a lower reactant-gas-to-inert-gas ratio relative to a reactant-gas-to-inert-gas ratio of the first process gas. The second process gas is formed by removing at least a portion of a reactant gas flow from the first process gas.

Abstract: An arc evaporation coating source includes a target made of a coating material to be vapor-deposited, a ferromagnetic yoke for influencing the vapor deposition of the coating material to be vapor-deposited and at least one permanent-magnetic body for influencing the vapor deposition of the coating material to be vapor-deposited. The ferromagnetic yoke is disposed in contact with the target. The permanent-magnetic body is fastened to the target by the ferromagnetic yoke.

Abstract: A rectangular hollow sputtering source includes a box-shaped cathode including therethrough an aperture that is open at a first side and a second side of the box-shaped cathode. A cooling block surrounds the box-shaped cathode and a number of magnets are disposed in the cooling block around the aperture. An electrical insulating part surrounds and electrically isolates the cooling block, the bar magnets, and the cathode from an anode which surrounds the exterior of the electrical insulating part.

Abstract: Systems and methods are provided for maximizing the data acquired from a sample in a mass spectrometry imaging experiment. An ion source device is instructed to produce and transmit to a tandem mass spectrometer a plurality of ions for each location of two or more locations of a sample. A mass range is divided into two or more mass window widths. For each location of the two or more locations, the tandem mass spectrometer is instructed to fragment the plurality of ions received for each location using each mass window width of the two or more mass window widths and to analyze resulting product ions. A product ion spectrum is produced for each mass window width, and a plurality of product ion spectra are produced for each location of the two or more locations.

Abstract: The disclosure features mass spectrometry systems and methods that include an ion source, an ion trap, a detector subsystem featuring first and second detector elements, and a controller electrically connected to the ion source, the ion trap, and the detector subsystem and configured so that during operation of the system, the controller: applies an electrical signal to the ion source to generate positively and negatively charged particles from sample particles in the system; applies an electrical signal to the ion trap to eject a plurality of particles from the ion trap through a common aperture of the ion trap, and determines information about the sample particles based on first and second electrical signals generated by the ejected particles.

Abstract: The invention relates to a low-cost spring steel plate as the sample support on a dimensionally stable and precisely shaped substructure, machined from an aluminum alloy, for example, and using a pattern of embedded magnets so that said plate is removable and that a body is created overall which is suitable for use in robots, for example by giving it the dimensions of a conventional microtitration plate. The planarity of the surface onto which the (organic) samples are applied is provided within the near region by the spring steel plate itself and in the far region over the whole spring steel plate by the substructure. The spring steel plate may be designed for single use in order to satisfy IVD diagnostic regulations also, for example. It can be equipped with identification codes, sample site markings and pre-coatings for different types of analytical tasks, such as MALDI-TOF mass spectrometric analysis.

Abstract: A mass microscope apparatus includes: a measuring unit including an ionization unit configured to ionize a sample present in an observation region, and a mass spectrometry unit configured to perform mass spectrometry of ions generated by the ionization unit; an object moving device configured to relatively move the observation region as to the sample; and a switching unit configured to switch measurement conditions of the measuring unit depending on whether the mass microscope apparatus is operating in a moving measurement mode where the observation region is moved by the object moving device to sequentially perform measurement by the measuring unit, and a stationary measurement mode where the observation region is stationary and measurement is performed by the measuring unit.

Abstract: A collar includes two sections that join together in an adhesive-less manner to form an aperture, an arm with a distally-located pawl extending from a base of each section, a frame on the other section at a position corresponding to the arm, a lower clamp located on the sections, an upper clamp including a distally-located projection extending from the base surface, first and second flexible clamps located at opposing ends of the aperture. A gas discharge tube lighting assembly includes a discharge tube collar, a discharge tube having a stem assembly with a first portion fitting within the discharge tube and a second portion having a seal ring with a diameter greater than the discharge tube outer diameter, the collar and tube connected by adhesive-less mechanical forces exerted on the upper, lower, and first and second flexible clamps with the discharge tube located partially in the aperture.

Abstract: The specification and drawings present a new apparatus such as a halogen incandescent lamp is presented herein, the apparatus comprising a light source such as a light-generating element made of tungsten, configured to generate a visible light such as white light having chromaticity coordinates of the light source in a clear center in a color space, and a component such as light-transmissive envelope, enclosing the light source and comprising a coating with a compound comprising elements of neodymium and fluorine and configured to provide a desired light spectrum by filtering the generated visible light using the compound, where the desired light spectrum having chromaticity coordinates in the color space being shifted from the clear center below the black-body locus and outside of a four-step MacAdam ellipse of the light source to meet a predefined requirement for a modified spectrum lamp.

Abstract: A lamp for automotive vehicle front lighting is described. The lamp (10) comprises a base (12) for mechanical and electrical connection to an automotive headlight (50) and a burner (14) fixed to the base (12). The burner (14) comprises an enclosed transparent vessel (22). A first and a second filament (34, 36) are arranged within the vessel (22). A baffle (40) is arranged proximate to the first filament (34) to shield the second filament (36) from the first filament (34). When the first filament (34) is supply voltage of 13.2 V at an electrical power greater operated at a supply voltage of 13.2 V at an electrical power greater than 35 W and less than or equal to 38 W, light with a luminous flux of 500-700 lm is emitted from the lamp 10. If the second filament (36) is operated at a supply voltage of 13.2 V at an electrical power greater than 35 W and less than or equal to 38 W, light with a luminous flux of 800-1000 lm is emitted from the lamp (10).

Abstract: Processes for depositing SiO2 films on a wafer surface utilizing an aminosilane compound as a silicon precursor are described.

Abstract: Atomic layer deposition methods for the low temperature deposition of silicon dioxide films having low nitrogen content and low wet etch rates. Silicon dioxide films are deposited and treated with plasma and re-oxidized resulting in low nitrogen content films.

Abstract: A composition for forming a silica layer including a silicon-containing polymer having a weight average molecular weight of about 20,000 to about 70,000 and a polydispersity index of about 5.0 to about 17.0 and a solvent; a silica layer manufactured using the same; and an electronic device including the silica layer.

Abstract: Provided are methods of depositing silicon-containing films utilizing certain precursors at temperatures of 400° C. or higher. Certain methods comprise exposing a substrate surface to a silicon precursor and another precursor to achieve various films. Examples of silicon-containing films which can be deposited include SiN, SiC, SiO2, SiCN, etc.

Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.

Abstract: A controllability of a size of a mask can be improved in a multi-patterning method. A process of forming a silicon oxide film on a first mask and an antireflection film is performed. In this process, plasma of a first gas including a silicon halide gas and plasma of a second gas including an oxygen gas are alternately generated. Then, a region of the silicon oxide film is removed such that only a region along a side wall of the first mask is left, and then, the first mask is removed and the antireflection film and an organic film is etched.

Abstract: A method for manufacturing a semiconductor substrate. An impurity diffusion ingredient can be diffused well and uniformly from a coating film into a semiconductor substrate by forming a coating film having a thickness of not more than 30 nm on a surface of a semiconductor substrate with a diffusion agent composition containing an impurity diffusion ingredient and a silicon compound that can be hydrolyzed to produce a silanol group.

Abstract: An embodiment is a method including forming a fin on a substrate, forming a first doped region in a top portion of the fin, the first doped region having a first dopant concentration, and forming a second doped region in a middle and bottom portion of the fin, the second doped region having a second dopant concentration, the second dopant concentration being less than the first dopant concentration.

Abstract: A method includes providing a semiconductor substrate; forming a doping oxide layer on the semiconductor substrate; forming a patterning layer on the doping oxide layer, the patterning layer leaving exposed regions of the doping oxide layer; performing a sputtering process to the substrate; and after the sputtering process, performing a wet etching process to the semiconductor substrate to remove the doping oxide layer from the exposed regions.

Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.

Abstract: A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall. The devices also includes a control gate adjacent the select gate, a charge storage layer located between the select gate and the control gate and between the control gate and the substrate, and an isolation region over the bottom portion of the select gate and between the top sidewall of the select gate and the charge storage layer. The bottom sidewall of the bottom portion extends to the charge storage layer.

Abstract: Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall.

Abstract: A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N2O). A source of carbon and the nitrous oxide (N2O) are introduced to the substrate under a plasma ambient of an inert gas. The amorphous carbon layer has a nitrogen content ranging from about 0.05 at % to about 30 at % and an oxygen content ranging from about 0.05 at % to about 10 at %. In forming a semiconductor device, the hard mask layer is patterned, and a target layer beneath the hard mask layer is etched using the patterned hard mask layer as an etch mask.

Abstract: A polishing apparatus is provided. The polishing apparatus includes: a polishing unit configured to polish a substrate by bringing a polishing tool into contact with the substrate and moving the substrate relatively to the polishing tool; a cleaning unit; and a first transfer robot configured to transfer the substrate before polishing to the polishing unit and/or configured to transfer the substrate after polishing from the polishing unit to the cleaning unit. The cleaning unit includes: at least one cleaning module, a buff processing module configured to perform a buff process to the substrate, and a second transfer robot configured to transfer the substrate between the cleaning module and the buff processing module, the second transfer robot being different from the first robot.

Abstract: The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC.

Abstract: The present invention relates to a method of selectively removing metal oxide, particularly tungsten oxide without etching the un-oxidized metal. The method removes metal oxide with little or no loss of the clean metal to improve the contact resistance for contact metal in semiconductor device fabrication. The method includes a step of exposing a substrate containing a tungsten oxide layer over a tungsten layer to a low oxygen aqueous ammonia solution to selectively remove the tungsten oxide layer. The low oxygen aqueous ammonia solution has an ammonia concentration in a range of about 0.01 M to about 2.0 M. The oxygen level in the solution is no more than 50 ppb. The solution may further contain a corrosion inhibitor and/or a compound having two or more carboxyl groups separated by at least one carbon atom.

Abstract: Molding assemblies and methods for dual side package molding are described. In an embodiment, a molding compound is injected into a front cavity with a first actuator, and a molding compound is injected into a back cavity with a second actuator, with the first and second actuator assemblies being independently controlled. In an embodiment, the molding compound flows through a through-hole in a molding substrate from a front side of the molding substrate to a back side of the molding substrate, and into the back cavity.

Abstract: A method for drying a substrate including a plurality of high aspect ratio (HAR) structures includes, after at least one of (i) wet etching, and (ii) wet cleaning, and (iii) wet rinsing the substrate using at least one of (a) wet etching solution, and (b) wet cleaning solution, and (c) wet rinsing solution, respectively, and without drying the substrate: depositing, between the plurality of HAR structures, a solution that includes a polymer component, a nanoparticle component, and a solvent; wherein as the solvent evaporates, a sacrificial bracing material precipitates out of solution and at least partially fills the plurality of HAR structures, the sacrificial bracing material including (i) polymer material from the polymer component of the solution and (ii) nanoparticle material from the nanoparticle component of the solution; and exposing the substrate to plasma generated using a plasma gas chemistry to volatize the sacrificial bracing material.

Abstract: A plasma etching method includes a holding step of holding a substrate, a processing gas supplying step of supplying processing gas to a space between the holding unit and an electrode plate facing the holding unit within the processing chamber, and a high frequency power supplying step of converting the processing gas supplied to the space from the plurality of supply parts into plasma by supplying a high frequency power from a high frequency power supply to at least one of the holding unit and the electrode plate. The processing gas supplying step includes controlling an adjustment unit configured to adjust a supply condition for supplying processing gas with respect to each of the plurality of supply parts such that the supply condition that is adjusted varies between a first position and a second position.

Abstract: Embodiments of the invention provide a single ring comprising a circular ring-shaped body with an inner surface, closest in proximity to a centerline of the body, and an outer surface opposite the inner surface. The body has a bottom surface with a slot formed therein and a top surface with an outer end, adjacent to the outer surface, and an inner end adjacent to a slope extending, towards the centerline, down to a step on the inner surface. The body has a lip, disposed on the inner surface extending out from a vertical face below the step toward the centerline of the body, and is configured to support a substrate thereon. The body is sized such that a gap of less than about 2 mm is formed on the lip between the substrate and the vertical face of the step.

Abstract: A method of making a semiconductor manufacturing equipment component, such as an electrostatic chuck, includes an application step of applying a photosensitive metal paste onto a ceramic green sheet, which is to become the body substrate, the photosensitive metal paste being a heating element material; an exposure-and-development step of exposing the photosensitive metal paste, which has been applied onto the ceramic green sheet, to light and developing the photosensitive metal paste to form an intermediate heating element, which is to become the heating element, on the ceramic green sheet; and a firing step of co-firing the ceramic green sheet and the intermediate heating element to form the body substrate and the heating element.

Abstract: A member for semiconductor manufacturing device includes a susceptor 10 which is a ceramic plate formed of AlN and a gas introduction pipe 20 which is joined to the susceptor 10. An annular pipe joining bank 14 is provided at a position of the susceptor 10 facing a flange 22 of the gas introduction pipe 20. In addition, a pipe brazed part 24 is formed between the flange 22 and the pipe joining bank 14. The flange 22 has a width of 3 mm or more and a thickness of from 0.5 to 2 mm. It is preferable that the height of the pipe joining bank 14 be 0.5 mm or more, the edge of the bank facing the outer edge of the flange 22 be chamfered as designated by C0.3 or more or rounded as designated by R0.3 or more.

Abstract: A method of manufacturing a semiconductor device comprises providing a carrier, disposing a plurality of dies over the carrier along a first direction and a second direction orthogonal to the first direction to arrange the plurality of dies in a plurality of rows, and shifting one of the plurality of rows along the first direction or the second direction in a predetermined distance.

Abstract: Apparatus and methods for processing a semiconductor wafer including a susceptor assembly with recesses comprising at least three lift pins. The lift pins include a sleeve with a spring and pin positioned therein. The spring and pin elevate the wafer to a position where the wafer can be pre-heated and, upon compression, lowers the wafer to a processing position.

Abstract: Methods for reducing the k value of a layer using air gaps and devices produced by said methods are disclosed herein. Methods disclosed herein can include depositing a carbon containing stack over one or more features in a substrate, depositing a porous dielectric layer over the carbon containing stack, and curing the substrate to volatilize the carbon containing stack. The resulting device includes a substrate with one or more features formed therein, a porous dielectric layer formed over the features with an air gap formed in the features.

Abstract: Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure.

Abstract: The methods for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Abstract: Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Abstract: A method of forming low-k interconnect structure is disclosed, which comprises: providing at least one protruding structure on a substrate traversing between a first connection region to a second connection region defined thereon; performing anodic oxidation on the substrate having the protruding structure; forming one or more nanowire interconnect in the protruding structure traversing between the first connection region and the second connection region; the nanowire interconnect being surrounded by a dielectric layer formed during the anodic oxidation.

Abstract: Embodiments of the present disclosure provide methods for etching a barrier layer disposed under a metal layer, such as a copper layer, when the metal layer is etched open exposing the barrier layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of etching a barrier layer disposed under a metal layer formed on a substrate includes supplying a first etching gas mixture comprising a hydrogen containing gas and an inert gas into a processing chamber to clean a surface of a barrier layer disposed on a substrate for a first period of time, supplying a second etching gas mixture comprising fluorine containing gas into the processing chamber to etch the barrier layer, and switching to supply the first etching gas in the processing chamber to clean the etched barrier layer for a second period of time.