Patents Issued in April 7, 2016
-
Publication number: 20160099174Abstract: Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate. A spacer material layer is formed on a sidewall at least one trench. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Inventors: Yung-Hsu Wu, Cheng- Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee, Yung-Sung Yen, Chun-Kuang Chen, Tien-I Bao, Ru-Gun Liu, Shau-Lin Shue
-
Publication number: 20160099175Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventors: Akihiro Horibe, Hiroyuki Mori, Yasumitsu Orii, Kuniaki Sueoka, Kazushige Toriyama
-
Publication number: 20160099176Abstract: A method for manufacturing a semiconductor chip includes forming a front-side groove in a front surface of a substrate; forming a back-side groove wider than the front-side groove by a rotating cutting member from the back surface of the substrate toward the front-side groove; attaching a holding member having an adhesive layer to the back surface of the substrate after forming the back-side groove; dry-washing the back surface before attaching the holding member to the back surface; extending the distance between adjacent semiconductor chips by expanding the holding member attached to the back surface; and separating the semiconductor chips at the extended distance therebetween from the holding member.Type: ApplicationFiled: August 4, 2015Publication date: April 7, 2016Applicant: FUJI XEROX CO., LTD.Inventors: Hirokazu MATSUZAKI, Kenji YAMAZAKI, Michiaki MURATA, Takahiro HASHIMOTO, Takeshi MINAMIRU
-
Publication number: 20160099177Abstract: In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An ARC layer is formed on the isolation layer pattern to at least partially cover sidewalls of the first and second active fins. A level of a top surface of the ARC layer is equal to or less than, and equal to or greater than half of, those of the first and second active fins. A photoresist layer is formed on the first and second active fins and the ARC layer. A portion of the photoresist layer is removed to form a photoresist pattern covering the first active fin and exposing the second active fin. A portion of the ARC layer under the removed portion of the photoresist layer is removed to form an ARC layer pattern. Impurities are implanted into the exposed second active fin to form an impurity region.Type: ApplicationFiled: May 1, 2015Publication date: April 7, 2016Inventors: Bum-Joon YOUN, Tae-Sun KIM, Yeo-Jin LEE, Yu-Ra KIM, Jin-Man KIM, Jae-Kyung SEO, Ki-Man LEE
-
Publication number: 20160099178Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.Type: ApplicationFiled: October 5, 2015Publication date: April 7, 2016Inventors: Ying ZHANG, Hua CHUNG
-
Publication number: 20160099179Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.Type: ApplicationFiled: October 3, 2014Publication date: April 7, 2016Inventors: Chun-Tsen Lu, Chih-Jung Su, Jian-Wei Chen, Shui-Yen Lu, Yi-Wen Chen, Po-Cheng Huang, Chen-Ming Huang, Shih-Fang Tzou
-
Publication number: 20160099180Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim, and forming a plurality of switchable cells in the active area. Each of the switchable cells includes a body region, a gate electrode structure, and a source region. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region. The method further includes forming a source metallization in ohmic contact with the source regions of the switchable cells, and forming a gate metallization in ohmic contact with the gate electrode structures of the switchable cells.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventors: Christian Fachmann, Enrique Vecino Vazquez
-
Publication number: 20160099181Abstract: A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a first sub-fin and a second sub-fin protruding from a surface of the substrate. The first isolation structure is disposed in the semiconductor fin used for electrically isolating the first sub-fin and the second sub-fin. The first dummy structure is disposed on the first isolation structure and laterally extends beyond the first isolation structure along a long axis of the semiconductor fin, so as to partially overlap a portion of the first sub-fin and a portion of the second sub-fin.Type: ApplicationFiled: November 12, 2014Publication date: April 7, 2016Inventor: Yu-Cheng Tung
-
Publication number: 20160099182Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventor: Jam-Wem Lee
-
Publication number: 20160099183Abstract: The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Denis Rideau, Elise Baylac, Emmanuel Richard, Francois Andrieu
-
Publication number: 20160099184Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Inventors: Wei-Chi Lee, Yu-Lin Wang, Chun-Chieh Chang, Tzu-Feng Chang, Po-Peng Lin
-
Publication number: 20160099185Abstract: A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.Type: ApplicationFiled: September 15, 2015Publication date: April 7, 2016Inventors: Chongkwang Chang, Sungwoo Kang, Chunghowan Kim, Youngmook Oh, Seobum Lee, Gahyun Lim
-
Publication number: 20160099186Abstract: A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and adapting the basic doping of the semiconductor wafer by postdoping. The postdoping includes at least one of the following methods: a proton implantation and a subsequent thermal process for producing hydrogen induced donors. In this case, at least one of the following parameters is dependent on the determined doping concentration of the basic doping: an implantation dose of the proton implantation, and a temperature of the thermal process.Type: ApplicationFiled: December 9, 2015Publication date: April 7, 2016Inventors: Reinhard Ploss, Helmut Oefner, Hans-Joachim Schulze
-
Publication number: 20160099187Abstract: Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, performing an etching process to etch a portion of the film stack exposed by the trimmed patterned photoresist layer, directing an optical signal to a surface of the trimmed patterned photoresist layer continuously during the trimming and the etching process, collecting a return reflected optical signal reflected from the trimmed patterned photoresist layer, determining a change of reflected intensify of the return reflected optical signal as collected; and calculating a photoresist thickness loss based on the change of the reflected intensity.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventor: Lei LIAN
-
Publication number: 20160099188Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region.Type: ApplicationFiled: September 22, 2015Publication date: April 7, 2016Inventors: Christian Jaeger, Johannes Georg Laven, Frank Dieter Pfirsch, Alexander Philippou
-
Publication number: 20160099189Abstract: A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The semiconductor package further includes a semiconductor die attached to the die paddle and having a plurality of pads including a gate pad, a plurality of electrical conductors connecting the pads to the leads, an encapsulant encasing the semiconductor die and a portion of the leads such that part of the leads are not covered by the encapsulant, and a ferrite material embedded in the encapsulant and surrounding a portion of the electrical conductor that connects the gate pad to the gate lead. A method of manufacturing the semiconductor package and a semiconductor module with integrated ferrite material are also provided.Type: ApplicationFiled: October 6, 2014Publication date: April 7, 2016Inventors: Charles Low Khai Yen, Daryl Quake Chin Wern
-
Publication number: 20160099190Abstract: Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy material and a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventor: Sivakumar Nagarajan
-
Publication number: 20160099191Abstract: An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive pipe. The metal pad includes a center portion overlapped by a region encircled by the conductive pipe, and an outer portion in contact with the conductive pipe. A dielectric layer is underlying the core dielectric material and the metal pad. A via is in the dielectric layer, wherein the via is in physical contact with the center portion of the metal pad.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventor: Jiun Yi Wu
-
Publication number: 20160099192Abstract: Dual-sided radio-frequency package having ball grid array. In some embodiments, a packaged radio-frequency (RF) device may include a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side. The packaged RF device also includes a shielded package implemented on the first side of the packaging substrate, the shielded package including an RF circuit, the shielded package configured to provide RF shielding for at least a portion of the RF circuit. The packaged RF device further includes a ball-grid array (BGA) implemented on the second side of the packaging substrate, the BGA defining a mounting volume on the second side of the packaging substrate and a component implemented within the mounting volume.Type: ApplicationFiled: July 31, 2015Publication date: April 7, 2016Inventors: Howard E. CHEN, Robert Francis DARVEAUX, Matthew Sean READ
-
Publication number: 20160099193Abstract: A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.Type: ApplicationFiled: July 10, 2015Publication date: April 7, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Yoichi NOGAMI
-
Publication number: 20160099194Abstract: A semiconductor module includes a first semiconductor element, a second semiconductor element, a first heat spreader electrically and thermally connected to the first semiconductor element, a second heat spreader electrically and thermally connected to the second semiconductor element, a DCB substrate including a first metal foil on a top surface of a ceramic insulating substrate and including a second metal foil on a bottom surface, the first metal foil being electrically and thermally joined to the first heat spreader and the second heat spreader, and a cooler thermally connected to the second metal foil of the DCB substrate. The first semiconductor element is disposed on an upstream side, and the second semiconductor element is disposed on a downstream side with respect to a flowing direction of a refrigerant of the cooler. An area of the second heat spreader is greater than an area of the first heat spreader.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventors: Hiromichi GOHARA, Nobuhide ARAI, Shinichiro ADACHI, Yoshitaka NISHIMURA
-
Publication number: 20160099195Abstract: A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.Type: ApplicationFiled: October 7, 2015Publication date: April 7, 2016Inventor: Yu-Lung HUANG
-
Publication number: 20160099196Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.Type: ApplicationFiled: December 7, 2015Publication date: April 7, 2016Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
-
Publication number: 20160099197Abstract: Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein Young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than Young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit.Type: ApplicationFiled: October 2, 2015Publication date: April 7, 2016Inventors: Yutaka UEMATSU, Hiroyuki NAGATOMO, Junichi MASUKAWA
-
Publication number: 20160099198Abstract: A semiconductor package apparatus includes a lead frame, a first semiconductor chip, a second semiconductor chip, a first connecting element, and a second connecting element. The lead frame includes a power input plate, a ground plate, a phase plate, and a phase detection plate. The second electrode of first semiconductor chip is disposed on the power input plate. The first electrode of second semiconductor chip is disposed on the ground plate. The first connecting element is disposed on the first semiconductor chip and the second semiconductor chip and electrically connects the first electrode of first semiconductor chip with the second electrode of second semiconductor chip. The second connecting element is disposed on the second semiconductor chip and phase plate and electrically connects the second electrode of second semiconductor chip with the phase plate. The first connecting element and the phase detection plate are electrically connected.Type: ApplicationFiled: June 5, 2015Publication date: April 7, 2016Inventor: Chau-Chun Wen
-
Publication number: 20160099199Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
-
Publication number: 20160099200Abstract: Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry the die, and leads, which are designed to be electrically coupled to the die; and a package, of encapsulating material, which is designed to encapsulate the die and partially coming out of which are the leads. The lead frame has as constituent material an aluminum alloy comprising a percentage of silicon ranging between 1% and 1.5%.Type: ApplicationFiled: June 25, 2015Publication date: April 7, 2016Inventors: Laura Ceriati, Paolo Crema, Agatino Minotti
-
Publication number: 20160099201Abstract: An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.Type: ApplicationFiled: October 2, 2015Publication date: April 7, 2016Inventors: Ju-il Choi, Atsushi Fujisaki, Byung-lyul Park, Ji-soon Park, Joo-hee Jang, Jeong-gi Jin
-
Publication number: 20160099202Abstract: A semiconductor packaging structure including a circuit board, a chip, and a paste is provided. The circuit board includes a base layer, a first circuit layer, and a second circuit layer. The base layer has a first surface, a second surface opposite to the first surface, and a recess located on the first surface. The first circuit layer is located on the first surface. The second circuit layer is located on the second surface. The chip is disposed on the first surface and is electrically connected to first circuit layer, where the recess is located on at least one side of the chip. The paste is filled between the chip and the first surface and filled in the recess, where the paste covers a side surface of the chip.Type: ApplicationFiled: November 20, 2014Publication date: April 7, 2016Inventor: Ming-Hung Lin
-
Publication number: 20160099203Abstract: A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the PCB to be spaced apart from each other. Each of the first and second semiconductor chips includes a command/address (CA) chip pad and a data input/output (DQ) chip pad. The CA chip pad of the first semiconductor chip is electrically coupled to the CA chip pad of the second semiconductor chip through a CA bonding wire.Type: ApplicationFiled: March 4, 2015Publication date: April 7, 2016Inventor: Moon Soo KIM
-
Publication number: 20160099204Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.Type: ApplicationFiled: May 12, 2015Publication date: April 7, 2016Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chia-Cheng Chen, Chih-Jen Yang, Fu-Tang Huang
-
Publication number: 20160099205Abstract: A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the PCB, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (eMUF) structure covering the sides of the chip while exposing the backside surface of the chip. A PoP package includes a top package stacked on and electrically connected to the semiconductor package.Type: ApplicationFiled: September 4, 2015Publication date: April 7, 2016Inventors: HEUNG KYU KWON, HAE GU LEE, BYEONG YEON CHO
-
Publication number: 20160099206Abstract: Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.Type: ApplicationFiled: October 1, 2015Publication date: April 7, 2016Applicant: VIAGAN LTD.Inventor: Mordechai Margalit
-
Publication number: 20160099207Abstract: An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip.Type: ApplicationFiled: October 6, 2015Publication date: April 7, 2016Inventors: Edward Fuergut, Martin Gruber, Juergen Hoegerl
-
Publication number: 20160099208Abstract: A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may include a first set of conductor layers made of a first type conductor material and a second set of conductor layers made of a second type conductor material different from the first. A pair of conductor posts may traverse the stacked conductor layers. A first post may be electrically connected to the first set of conductor layers and electrically insulated from the second set of conductor layers. A second post electrically connected to the second set of conductor layers and electrically insulated from the first set of conductor layers.Type: ApplicationFiled: October 3, 2014Publication date: April 7, 2016Applicant: ANALOG DEVICES, INC.Inventor: Baoxing Chen
-
Publication number: 20160099209Abstract: A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above the third wiring, a first contact electrically connected between the first wiring and the fourth wiring, a first insulator on the first contact, and a second contact on the first insulator, the second contact being electrically connected between the second wiring and the third wiring. The first contact overlaps the second contact in a direction that is orthogonal to an upper surface of the substrate.Type: ApplicationFiled: February 24, 2015Publication date: April 7, 2016Inventor: Kiyohito NISHIHARA
-
Publication number: 20160099210Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.Type: ApplicationFiled: September 25, 2015Publication date: April 7, 2016Applicant: NEPES CO., LTD.Inventors: Yong-Tae KWON, Jun-Kyu LEE
-
Publication number: 20160099211Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.Type: ApplicationFiled: October 1, 2015Publication date: April 7, 2016Inventors: Sang-Hoon BAEK, Sun-Young PARK, Sang-Kyu OH, Ha-Young KIM, Jung-Ho DO, Moo-Gyu BAE, Seung-Young LEE
-
Publication number: 20160099212Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (3) having pre-formed and placed through package circuit devices (35) which include an embedded circuit component (39) and conductor terminals (37A, 37B) extending from a molded package (38) embedding the circuit component (39). The through package circuit devices (35) are placed on end with integrated circuit die (34) and encapsulated in a molded device package (32) which leaves exposed the one or more conductor terminals (37A, 37B) positioned on first and second surfaces of the through package circuit device, where the conductor terminals (37A, 37B) and embedded circuit component (39) form a circuit path through the molded device package.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Applicant: Freescale Semiconductor, Inc.Inventor: Michael B. Vincent
-
Publication number: 20160099213Abstract: A semiconductor package includes a package substrate with a cavity, a plurality of semiconductor chips vertically stacked in the cavity, a first insulating layer on a first surface of the package substrate, a first interconnection layer on the first insulating layer, a second insulating layer on a second surface of the package substrate opposite the first surface, and a second interconnection layer on the second insulating layer.Type: ApplicationFiled: May 26, 2015Publication date: April 7, 2016Inventors: Yujung TAE, Pyoungwan KIM
-
Publication number: 20160099214Abstract: Flexible integrated circuit (IC) modules, flexible IC devices, and methods of making and using flexible IC modules are presented herein. A flexible integrated circuit module is disclosed which includes a flexible substrate and a semiconductor die attached to the flexible substrate. An encapsulating layer, which is attached to the flexible substrate, includes a thermoplastic resin and/or a polyimide adhesive encasing therein the semiconductor die. The encapsulating layer may be an acrylic-based thermally conductive and electrically isolating polyimide adhesive. Optionally, the encapsulating layer may be a B-stage FR-4 glass-reinforced epoxy thermoplastic polymer or copolymer or blend. The die may be embedded between two flexible substrates, each of which includes a layer of flexible polymer, such as a polyimide sheet, with two layers of conductive material, such as copper cladding, disposed on opposing sides of the layer of flexible polymer.Type: ApplicationFiled: September 30, 2015Publication date: April 7, 2016Inventors: Mitul Dalal, Sanjay Gupta
-
Publication number: 20160099215Abstract: In a method for manufacturing a device embedded substrate, a conductive via that penetrates a first insulating layer and a second insulating layer from an outer metal layer to reach a second terminal of an IC device is formed after forming the outer metal layer.Type: ApplicationFiled: May 14, 2013Publication date: April 7, 2016Applicant: MEIKO ELECTRONICS CO., LTD.Inventors: Mitsuaki Toda, Tohru Matsumoto, Seiko Murata
-
Publication number: 20160099216Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.Type: ApplicationFiled: October 2, 2014Publication date: April 7, 2016Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Rueijer LIN, Chen-Yuan KAO, Chun-Chieh LIN, Huang-Yi HUANG
-
Publication number: 20160099217Abstract: A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line, and a fourth line. The second line and the third line are disposed between the first line and the fourth line. The first line, the second line, the third line, and the fourth line respectively extend in a first direction. An end segment of the second line and an end segment of the third line respectively include a first protrusion portions that extend in a second direction. The first protrusion portion of the end segment of the second line protrudes toward the first line. The first protrusion portion of the end segment of the third line protrudes toward the fourth line.Type: ApplicationFiled: October 2, 2014Publication date: April 7, 2016Inventor: Chi-Sheng Peng
-
Publication number: 20160099218Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.Type: ApplicationFiled: July 31, 2015Publication date: April 7, 2016Inventors: Baik-woo LEE, Dong-hun LEE, Jae-gwon JANG, Chul-yong JANG
-
Publication number: 20160099219Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.Type: ApplicationFiled: October 2, 2014Publication date: April 7, 2016Applicant: Secure Silicon Layer, Inc.Inventor: William Eli Thacker, III
-
Publication number: 20160099220Abstract: A high isolation wideband switch is disclosed. In one aspect, the switch includes an integrated circuit package having an integrated circuit die with a first plurality of leads that is positioned on a package substrate that has a second plurality of leads. The first leads of the integrated circuit die are connected to the second the leads of the package substrate via bond wires and a first electrical coupling occurs between the first leads and the integrated circuit die in response to an RF signal applied to the integrated circuit package. The bond wires have a second electrical coupling in response to the RF signal and the bond wires are arranged such that the second electrical coupling is matched to the first electrical coupling within a selected frequency band so as to reduce the overall electrical coupling of the integrated circuit package for RF signals within the selected frequency band.Type: ApplicationFiled: September 11, 2015Publication date: April 7, 2016Inventors: Yusuf Alperen Atesal, Turusan Kolcuoglu
-
Publication number: 20160099221Abstract: A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Inventors: YUNG-PING CHIANG, CHAO-WEN SHIH, HAO-YI TSAI, MIRNG-JI LII
-
Publication number: 20160099222Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.Type: ApplicationFiled: November 30, 2015Publication date: April 7, 2016Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao Chung Foh, Zigmund Ramirez Camacho
-
Publication number: 20160099223Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Inventors: CHEN-CHIH HSIEH, HAO-YI TSAI, CHAO-WEN SHIH, YUNG-PING CHIANG, TSUNG-YUAN YU