Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

Abstract: A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness greater than the first thickness.

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Abstract: A thin film transistor array panel is capable of increasing an aperture ratio and decreasing parasitic capacitance between a gate electrode and a drain electrode by reducing an area of a thin film transistor. The thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer on the gate line; a semiconductive island on the gate insulating layer; a circular drain electrode on the semiconductive island; and a source electrode disposed on the semiconductive island and shaped like a circular band bent in a direction from which the drain electrode is disposed. The gate electrode may include a circular portion that is overlapped by the drain electrode and a circular sector portion that is overlapped by the source electrode.

Abstract: According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second nanowire over the substrate and substantially symmetric with the first nanowire.

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract: An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.

Abstract: A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.

Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.

Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract: A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided.

Abstract: A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

Abstract: Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type FinFETs and p-type FinFETs. Each of first source/drain contact structures for the n-type FinFETs includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type FinFETs includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion.

Abstract: One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

Abstract: A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.

Abstract: A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive type well, a linear graded high voltage first conductive type well and a first conductive type buried layer is provided. The first conductive type buried layer is located within the first conductive type epitaxial layer and below the high voltage second conductive type well, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well.

Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the top of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

Abstract: An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion.

Abstract: A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts. In the semiconductor device, the first oxide semiconductor film, the second oxide semiconductor film, and the oxide film are each formed using a IGZO film, where the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film, the first oxide semiconductor film has a higher indium content than the oxide film, the oxide film has a higher gallium content than the first oxide semiconductor film, and the first oxide semiconductor film has a higher gallium content than the second oxide semiconductor film.

Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.

Abstract: A non-volatile memory device combines thin-film transistor-based memory cells with bulk mono-crystalline silicon transistors, which can more efficiently drive bit lines for fast sensing of the stored data in the thin-film memory cells.

Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.

Abstract: Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%.

Abstract: A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.

Abstract: A solar panel is provided with a stack including at least one back contacted solar cell and a back-sheet layer. The back-sheet layer has a patterned conductive layer of a first material. The conductive layer is arranged with contacting areas each located at a location corresponding to a location of an electrical contact on the solar cell. The solar cell is arranged on top of the conductive layer with the rear surface of the solar cell facing the patterned conductive surface. Each electrical contact of the solar cell is in contact with a corresponding contacting area on the conductor circuit by a body of conductive connecting material. The conductive layer includes at the location of the contacting area a patch of a second material. Each patch is arranged in between the body of conductive connecting material on one electrical contact and the layer of the first material.

Abstract: Provided is a wafer for solar cell which can be produced using a polycrystalline semiconductor wafer cut out using a bonded abrasive wire, which wafer can be used for manufacturing a solar cell with high conversion efficiency. In a wafer for solar cell before acid texturing of the present invention, produced from a polycrystalline semiconductor wafer cut out using a bonded abrasive wire, an amorphous layer does not exist, and irregularities caused due to the cutting using the bonded abrasive wire are left in at least one surface of the wafer for solar cell.

Abstract: The invention provides an element including a semiconductor substrate and an electrode disposed on the semiconductor substrate, the electrode being a sintered product of a composition for an electrode that includes phosphorus-containing copper alloy particles, glass particles and a dispersing medium, and the electrode includes a line-shaped electrode having an aspect ratio, which is defined as electrode short length : electrode height, of from 2:1 to 250:1.

Abstract: A radiation energy conversion system comprises: an environmental barrier cover having a barrier cover inner surface; an environmental barrier enclosure supporting the environmental barrier cover, the environmental barrier enclosure having a barrier enclosure internal surface extending to the barrier cover inner surface; a radiation-tranparent optic disposed in at least one of the environmental barrier cover and the environmental barrier enclosure; and at least one radiation energy conversion cell secured to at least one of the barrier enclosure internal surface and the barrier cover inner surface.

Abstract: A solar panel includes a plurality of solar cells, a bypass diode unit, and a heat spreader. The bypass diode unit includes a bypass diode coupled in an electrical shunting configuration across at least a first solar cell of the plurality of solar cells to bypass current around at least the first solar cell in an event of failure of the first solar cell. The heat spreader is disposed over a portion of one or more of the solar cells. The bypass diode unit is disposed on a first side of the heat spreader with the bypass diode in thermal contact with the heat spreader. A second side of the heat spreader is mounted in thermal contact with the one or more of the solar cells to dissipate heat generated in the bypass diode to the one or more of the solar cells.

Abstract: The invention is related to a method for forming dendritic silver with periodic structure as light-trapping layer, includes these steps: form a photoresist layer on a conductive substrate, and at least two coherent light beams is provided in using a laser interference lithography apparatus, to form a plurality of particular patterns respectively on the setting-exposure positions of the conductive substrate in sequence till the particular periods pattern formed. Thereafter, form the dendritic silver nanostructure with period pattern on the conductive substrate via electrochemical process, wherein operating voltage is 2V or higher, and electrochemical reaction time is 10 sec or higher.

Abstract: An interconnected arrangement of photovoltaic cells is achieved using laminating current collector electrodes. The electrodes comprise a pattern of conductive material extending over a first surface of sheetlike substrate material. The first surface comprises material having adhesive affinity for a selected conductive surface. Application of the electrode to the selected conductive surface brings the first surface of the sheetlike substrate into adhesive contact with the conductive surface and simultaneously brings the conductive surface into firm contact with the conductive material extending over first surface of the sheetlike substrate. Use of the laminating current collector electrodes allows facile and continuous production of expansive area interconnected photovoltaic arrays.

Abstract: A solar cell module, a method for manufacturing the solar cell module, a solar power system, and an interconnection ribbon are provided. The solar cell module includes a plurality of solar cells which are connected in series or in parallel through interconnection ribbons, wherein the interconnection ribbons have a zigzag shape to reduce tension generated according to bending of the solar cell module.

Abstract: A solar power method is provided using two-stage light concentration to drive concentrating photovoltaic conversion in conjunction with thermal collection. The method concentrates light rays received in a plurality of transverse planes towards a primary linear focus in an axial plane, which is orthogonal to the transverse planes. T hand wavelengths of light are transmitted to the primary linear focus. R hand wavelengths of light are reflected towards a secondary linear focus in the axial plane, which is parallel to the primary linear focus. The light received at the primary linear focus is translated into thermal energy. The light received at the secondary linear focus is focused by optical elements along a plurality of tertiary linear foci, which are orthogonal to the axial plane. The focused light in each tertiary primary focus is focused into a plurality of receiving areas, and translated into electrical energy.

Abstract: The invention bears on elementary nanoscale units nanostructured-formed inside a silicon material and the manufacturing process to implement them. Each elementary nanoscale unit is created by means of a limited displacement of two Si atoms outside a crystal elementary unit. A localized nanoscale transformation of the crystalline matter gets an unusual functionality by focusing in it a specific physical effect as is a highly useful additional set of electron energy levels that is optimized for the solar spectrum conversion to electricity. An adjusted energy set allows a low-energy secondary electron generation in a semiconductor, preferentially silicon, material for use especially in very-high efficiency all-silicon light-to-electricity converters. The manufacturing process to create such transformations in a semiconductor material bases on a local energy deposition like ion implantation or electron beam irradiation and suitable thermal treatment and is industrially easily available.

Abstract: An integrated thin-film lateral multi junction solar device and fabrication method are provided. The device includes, for instance, a substrate, and a plurality of stacks extending vertically from the substrate. Each stack may include layers, and be electrically isolated against another stack. Each stack may also include an energy storage device above the substrate, a solar cell above the energy storage device, a transparent medium above the solar cell, and a micro-optic layer of spectrally dispersive and concentrating optical devices above the transparent medium. Furthermore, the device may include a first power converter connected between the energy storage device and a power bus, and a second power converter connected between the solar cell and the power bus. Further, different solar cells of different stacks may have different absorption characteristics.

Abstract: A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

Abstract: A photon detector includes a single photon avalanche diode (SPAD) disposed proximate to a front side of a semiconductor layer. The SPAD includes a multiplication junction that is reversed biased above a breakdown voltage such that light directed into the SPAD through a backside of the semiconductor layer triggers an avalanche multiplication process. A guard ring is disposed in a guard ring region that surrounds the SPAD to isolate the SPAD in the semiconductor layer. A guard ring region reflecting structure is disposed in the guard ring region proximate to the guard ring and proximate to the front side of the semiconductor layer such that light directed into the guard ring region through the backside of the semiconductor layer that bypasses the SPAD is redirected by the guard ring region reflecting structure back into the semiconductor layer and into the SPAD.

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

Abstract: An optical detection sensor functions as a proximity detection sensor that includes an optical system and a selectively transmissive structure. Electromagnetic radiation such as laser light can be emitted through a transmissive portion of the selectively transmissive structure. A reflected beam can be detected to determine the presence of an object. The sensor is formed by encapsulating the transmissive structure in a first encapsulant body and encapsulating the optical system in a second encapsulant body. The first and second encapsulant bodies are then joined together. In a wafer scale assembling the structure resulting from the joined encapsulant bodies is diced to form optical detection sensors.