Abstract: Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies.

Abstract: There is provided a solid-state imaging device including a wafer in which a guard ring with conductivity in an insulation film layered on a first conductivity type substrate is formed between an edge portion of at least a first chip, out of the first chip and a second chip of a layered chip, and a scribe line region, at least two second conductivity type layers are formed at an interval within a region corresponding to the guard ring, in the first conductivity type substrate, and the guard ring includes a first guard ring part connected to one of the second conductivity type layers on a chip edge portion side, and a second guard ring part connected to another one of the second conductivity type layers on a scribe line side.

Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies.

Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.

Abstract: An image sensor device includes a substrate having a first conductivity type. A plurality of photo-sensing regions including a first, a second, and a third photo-sensing regions corresponding to the R, G, B pixels are provided on the substrate. An insulation structure is disposed on the substrate to separate the photo-sensing regions from one another. A photodiode structure is formed within each photo-sensing region. A deep well structure having a second conductivity type. The deep well structure only overlaps with the second and third photo-sensing regions. The deep well structure does not overlap with the first photo-sensing region.

Abstract: An image sensor is provided. The image sensor includes a red (R) pixel, a green (G) pixel, a blue (B) pixel and an infrared (IR) pixel, and R, G and B filters respectively disposed at the R, G and B pixels. The image sensor also includes an IR pass filter disposed at the IR pixel and an IR filter stacked with the R, G and B filters, wherein the IR filter cuts off at least IR light with a specific wavelength. Furthermore, a method of forming an image sensor is also provided.

Abstract: Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies.

Abstract: Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies.

Abstract: A pixel cell includes a charge accumulation region having a second doping polarity buried completely in a semiconductor substrate having a first doping polarity beneath a first surface. The charge accumulation region accumulates image charge in response to light directed through a second surface. A channel region is disposed in the semiconductor substrate between the first surface and the charge accumulation region. A variable resistance of the channel region is responsive to the image charge accumulated in the charge accumulation region. A center contact coupled to a central portion of the channel region through the first surface to provide a radial current path through the channel region between the central portion of the channel region and a periphery of the channel region around the charge accumulation region to the semiconductor substrate. A readout signal responsive to the image charge in the charge accumulation region is provided at the center contact.

Abstract: In one aspect, a method includes providing a lens substrate having an array of lenses. The lens substrate includes an overflow region next to each lens of the array. Each overflow region includes an overflow lens material. The method also includes separating the lens substrate into a plurality of smaller lens substrates. Each of the smaller lens substrates has one of the single lens and the plurality of stacked lenses. Separating the lens substrate into the smaller lens substrates may include removing or substantially removing the overflow regions. In one aspect, the method may be performed as a method of making a miniature camera module. Other methods are also described, as are miniature camera modules.

Abstract: Certain embodiments provide a method for manufacturing a solid-state imaging device including: forming a sensor chip fixed to a supporting substrate by a first adhesive; peeling off the sensor chip from the supporting substrate by softening the first adhesive; and fixing the peeled off sensor chip onto a curved surface of a mounting body to allow the sensor chip to be curved along the curved surface.

Abstract: The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that has a gate length larger than that of the gate electrode part.

Abstract: According to one embodiment, a magnetoresistive memory device, includes a metal buffer layer provided on a substrate, a crystalline metal nitride buffer layer provided on the metal buffer layer, and a magnetoresistive element provided on the metal nitride buffer layer. The metal nitride buffer layer and the metal buffer layer contain a same material.

Abstract: According to one embodiment, a magnetic memory includes a first magnetic layer, a second magnetic layer, a non-magnetic intermediate layer provided between the first magnetic layer and the second magnetic layer and an underlying layer provided on an opposite side of the first magnetic layer with respect to the intermediate layer, and the underlying layer contains AlN of a hcp structure.

Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

Abstract: According to one embodiment, a memory device includes a first gate electrode, a second gate electrode, a third gate electrode, a first active area and a second active area on a substrate. The first to the third gate electrodes extend in a first direction. The first active area and the second active area extend in a second direction. The first direction and the second direction cross each other. The memory device includes a first contact, a second contact, a third contact, a fourth contact, variable resistance layer, a first interconnection layer, a second interconnection layer and the second interconnection layer. The variable resistance layer and the first interconnection layer extend in the first direction. The second interconnection layer and the third interconnection layer extend in the second direction.

Abstract: Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

Abstract: According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared.

Abstract: Disclosed is an organic light emitting diode (OLED) display device for preventing a dark spot (dead pixel). The OLED display device includes a white OLED disposed in each of a plurality of pixels, a driving circuit unit disposed in each of the plurality of pixels, a first color filter disposed between the white OLED and the driving circuit unit, and a second color filter or a third color filter configured to overlap the first color filter between the white OLED and the driving circuit unit.

Abstract: An organic light emitting display device includes a substrate having a first width in a first direction and a second width in a second direction, the second width being perpendicular to and smaller than the first width, and pixel regions on the substrate, each of the pixel regions including a first light emitting portion, a second light emitting portion, a third light emitting portion, and a transmission portion arranged along the second direction, each of the first to third light emitting portions extending in the first direction.

Abstract: An organic light emitting display device includes a plurality of first sub-pixels arranged adjacent to each other along a first direction, each of the first sub-pixels includes a first emission region configured to emit light of a first color and a first transmission region configured to transmit external light, the first emission regions of at least two of the first sub-pixels are adjacent to each other; and a plurality of second sub-pixels arranged adjacent to each other along the first direction and adjacent to corresponding ones of the plurality of first sub-pixels along a second direction crossing the first direction, each of the plurality of second sub-pixels includes a second emission region configured to emit light of a second color and a second transmission region configured to transmit external light, the second emission regions of at least two of the sub-pixels are adjacent to each other.

Abstract: An organic light-emitting display apparatus includes a substrate; a plurality of pixels provided on a first surface of the substrate and each comprising a first area configured to emit light and a second area configured to have external light transmit therethrough; a pixel circuit unit provided in the first area of each of the plurality of pixels and comprising at least one thin-film transistor (TFT); a first electrode provided in the first area of each of the plurality of pixels and electrically connected to the pixel circuit unit; a second electrode facing the plurality of first electrodes, electrically connected throughout the plurality of pixels, and provided in at least in the first area of each of the plurality of pixels; an intermediate layer disposed between the first electrode and the second electrode and comprising an organic emission layer; and an inorganic insulating film provided in the second area of each of the plurality of pixels, and comprising a plurality of layers having different refractiv

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract: An organic light-emitting display apparatus includes a thin film transistor including an active layer, gate, source and drain electrodes, a first insulating layer disposed between the active layer and the gate electrode, and a second insulating layer disposed between the gate electrode and the source and drain electrodes; a pad electrode including a first pad layer disposed on the same layer as the source and drain electrodes and a second pad layer disposed on the first pad layer; a third insulating layer covering the source electrode and the drain electrode and an end portion of the pad electrode; a pixel electrode including a semi-transmissive metal layer and disposed in an opening formed in the third insulating layer; and a fourth insulating layer having an opening formed in a location corresponding to an opening formed in the third insulating layer and covering the end portion of the pixel electrode.

Abstract: An organic light emitting display device includes a substrate comprising a major surface; a display region and a peripheral region surrounding the display region when viewed in a viewing direction perpendicular to the major surface; an array of a plurality of pixels disposed in the display region; and a first power line extending from the peripheral region into the display region, the first power line being electrically connected to the array of pixels at a contact point in the display region. When viewed in the viewing direction, the first power line includes: a first extension extending from the peripheral region to the display region; and a second extension connected to the first extension; and a third extension connected to the second extension and extending from a location in the display region toward the peripheral region.

Abstract: A thin film transistor (TFT) array substrate and organic light-emitting diode (OLED) display including the same are disclosed. In one aspect, the array substrate includes a substrate, a driving TFT formed over the substrate and including a driving gate electrode, and a storage capacitor including a first electrode electrically connected to the driving gate electrode and a second electrode formed over and insulated from the first electrode. The array substrate also includes an interlayer insulating film at least partially covering the first electrode and a driving voltage line formed over the interlayer insulating film and configured to supply a voltage to the driving TFT. The driving voltage line is formed on the same layer as the second electrode.

Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.

Abstract: A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.

Abstract: In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or more dopants. The dopants may influence the crystallinity, resistivity, and/or work function of the second electrode material. The dopants may be uniformly distributed throughout the second electrode material or may be distributed with a gradient in their concentration profile.

Abstract: A capacitor stack includes a base bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. A molybdenum nitride or a molybdenum oxy-nitride layer is formed above the dielectric layer. A fourth top electrode layer is formed above the third top electrode layer. The base top electrode layer includes a conductive metal nitride material.

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract: A monolithic merged PIN Schottky (MPS) diode including a chip, at least one PIN diode, at least one Schottky diode and a termination structure is provided. The chip has a first active area, a second active area and a termination area. The PIN diode is disposed in the first active area. The Schottky diode is disposed in the second active area. The termination structure is disposed in the termination area. The first active area and the second active area are separated by the termination area. The PIN diode and the Schottky diode share the termination structure.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type. A dopant region of the second conductivity type disposed below the surface shield region extending across and surrounding a trench bottom portion of the trenches.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device.

Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.

Abstract: The present invention is directed to a method for forming multiple active components, such as bipolar transistors. MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance.

Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.

Abstract: A method of providing an out-of-plane semiconductor structure and a structure fabricated thereby is disclosed. The method comprises acts of: providing a substrate defining a major surface; providing a template layer having a predetermined template thickness on the major surface of the substrate; forming a recess in the template layer having a recess pattern and a recess depth smaller than the template thickness; and epitaxilally growing a semiconductor structure from the recess. A planar shape of the recess pattern formed in the template layer substantially dictates an extending direction of the semiconductor structure.

Abstract: A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a confronting pair of wall parts. One of the wall parts is more arcuate than the other of the wall parts. A method for fabricating the semiconductor structure is also disclosed.

Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.

Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n?-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p?-type body layer, and the n?-type drift layer between the p?-type body layer and the n?-type drift layer.

Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.

Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.

Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

Abstract: A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the semiconductor layer, and a dielectric layer positioned above the etch stop layer. A contact structure that includes a conductive contact material extends through at least a portion of the dielectric layer and through an entirety of the etch stop layer to the silicide contact region, and a silicide protection layer is positioned between sidewalls of the etch stop layer and sidewalls of the contact structure.

Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Abstract: Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.