Abstract: Deterioration of holding characteristics due to fluctuations in power supply voltage VDD is prevented. During writing or reading in one of memory circuits, a pair of bit lines in the other memory circuit is controlled to a dummy-bit-line voltage ranging from a ground voltage to ½×VDD. In a subsequent precharge period, a pair of bit lines in one of the memory circuits and the pair of bit lines in the other memory circuit are coupled to a reference voltage generating circuit.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: A nonvolatile memory device may include a power-on reset signal generation unit suitable for receiving a power supply voltage, and generating a power-on reset signal that changes based on the power supply voltage, and a discharging signal generation unit suitable for generating a discharging signal for discharging a word line to be activated earlier than an activation timing of the power-on reset signal when the power supply voltage decreases.

Abstract: A data storage device may include: a nonvolatile memory device including first and second memory cells adjacent to each other; and a controller suitable for performing a distribution adjusting operation for adjusting a threshold voltage of the second memory cell based on whether a read operation on the first memory cell fails.

Abstract: Provided is a semiconductor device including first to fifth circuits. The first circuit includes first and second transistors. The second circuit is capable of supplying one of first and second wirings with a gradually changing potential. The third circuit is capable of supplying a predetermined potential to the other of the first and second wirings and is capable of reading data stored in the first circuit. The fourth circuit is capable of comparing first data to be written to the first circuit with second data read by the third circuit. When a comparison result obtained by the fourth circuit concludes that the first data is consistent with the second data, the fifth circuit disconnects the second circuit from the first circuit, and a potential of the one of the first and second wirings is supplied to a gate of the second transistor.

Abstract: A data storage device includes a nonvolatile memory apparatus including a plurality of memory areas, and a controller configured to randomize write data and generate random write data based on an offset value of a target memory area of the memory areas and a flag corresponding to the target memory area.

Abstract: A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

Abstract: A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal.

Abstract: The invention may include a semiconductor apparatus comprising: a first die configured to latch and output external input data according to a strobe signal, to detect a valid pulse from among pulses of the strobe signal, and to generate a valid signal; and a second die configured to write data transmitted from the first die in response to the valid signal.

Abstract: A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop. The semiconductor apparatus may include a timing tuning block configured to generate delay control signals according to a phase difference of the delay-locked clock signal and the delay-locked internal command, and tune a delay time of the internal read command according to the delay control signals and generate a timing-tuned read command.

Abstract: An embodiment provides a method, including: reading validity timing information written to a non-volatile memory device; and determining validity of the non-volatile memory device using the validity timing information read from the non-volatile memory device. Other aspects are described and claimed.

Abstract: A latency control circuit may include a first latency control section configured to control a latency of a delay-locked termination signal according to a first divided clock signal, and generate a first preliminary signal, and a second latency control section configured to control the latency of the delay-locked termination signal according to a first divided clock bar signal which is generated by inverting the first divided clock signal, and generate a second preliminary signal. The latency control circuit may also include a signal combination unit configured to shift the first preliminary signal and the second preliminary signal by latency values set differently from each other, according to the first divided clock signal, and generate a first combined signal and a second combined signal, and a signal generation unit configured to generate a latency-controlled termination signal in response to the first combined signal and the second combined signal.

Abstract: Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store data. A testmode security system is configured to allow a user to access one or more testmodes of the apparatus at least partially responsive to the data storage not storing sensitive data and disallow the user from accessing the one or more testmodes of the apparatus at least partially responsive to the data storage storing sensitive data.

Abstract: The semiconductor device incorporates a selected sub word line driver and a first voltage switching circuit. The selected sub word line driver has an input node connected to a selected main word line, an output node connected to a selected sub word line, a reference node supplied with a common reference voltage, and a power node. The first voltage switching circuit selectively supplies a first power voltage, a second power voltage, or the common reference voltage to the power node of the selected sub word line driver. In an active mode, the first voltage switching circuit supplies the first power voltage to pull the selected sub word line to a logic high level. In a precharge mode, the first voltage switching circuit supplies the common reference voltage and then supplies the second power voltage, thereby pulling the selected sub word line to a logic low level. A voltage level of the second power supply node is lower than a voltage level of the first power voltage and higher than the common reference voltage.

Abstract: An active control device and a semiconductor device including the same are disclosed, which can control an active command in response to a pin change of a command address. The active control device includes: a bank decoding unit configured to decode a bank address to output a bank selection signal; an active controller configured to output a first active control signal, a second active control signal, and an active delay signal to control an active operation of a bank in response to the bank selection signal, a first active signal, and a second active signal; an address latch unit configured to latch a row address to output an address delay signal; and an address output unit configured to output an address corresponding to the address delay signal.

Abstract: A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells. The first interface circuit is configured to receive a DRAM interface signals, and the second interface circuit is configured to receive a flash memory interface signals.

Abstract: A semiconductor apparatus includes a first memory, a second memory, and a shared reference resistor. The first memory is electrically coupled to the shared reference resistor, and the second memory is also electrically coupled to the shared reference resistor. Each of the first and second memories performs a basic calibration operation thereof by selectively using the shared reference resistor in response to a clock signal, and a mirror function signal, which has different logic levels according to which memory between the first and second memories performs calibration operations.

Abstract: A method for healing phase-change memory device includes steps as follows: At least one memory cell comprising a phase-change material with a shifted current-resistance characteristic function (shifted I-R function) is firstly provided. A healing stress is then applied to the phase-change material to transform the shifted I-R function into an initial current-resistance characteristic function (initial I-R function), wherein the shifted I-R function is a translation function of the initial I-R function.

Abstract: Embodiments are directed to a system for sensing a data state of a selected memory cell. The system includes a first reference cell, a sample-and-hold sense amplifier and a switching system. During a first sensing phase the switching system is configured to open a first series communication path that places the selected memory cell in series with the first reference cell, thereby creating a first series voltage divider. During the first sensing phase, the switching system is further configured to open a first branch communication path that taps an input of the sample-and-hold sense amplifier into a first divided voltage between the selected memory cell and the first reference cell.

Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.

Abstract: A semiconductor memory may include: a bank control signal generation unit suitable for sequentially generating a plurality of bank control signals for controlling a memory bank based on an active command, a signal detection unit suitable for detecting a firstly activated signal and a lastly activated signal among the bank control signals, and a bank enable control unit suitable for controlling an active period of the memory bank in response to the detected signals.

Abstract: Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises: a data latch storage unit comprising a first terminal and a second terminal; a first dummy circuit coupled to the first terminal of the data latch storage unit, the first dummy circuit comprising a first partial dummy transistor and a second partial dummy transistor, wherein the first partial dummy transistor is formed in a first active area of a substrate and the second partial dummy transistor is formed in a second active area of the substrate; and a first gate electrode extending over an edge of the first active area and over an edge of the second active area, wherein the edges of the first active area and the second active area are disposed within a width of the first gate electrode.

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

Abstract: A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed sense enable signal is not asserted and to stop charging the corresponding pair of output terminals while the delayed sense enable signal is asserted.

Abstract: A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern includes read word lines, read bit lines, and read source lines. Each of the plurality of memory cells includes: first and second inverters which are cross-coupled to each other; a first transistor which is connected between a read bit line and a read source line and of which the gate is connected to the output terminal of the first inverter; and a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line.

Abstract: A semiconductor memory device, may include a memory cell array including memory cells, in which a page to be programmed within the memory cell array may include: a first memory cell programmed in a first program state; a second memory cell programmed in a second program state; and a third memory cell programmed in a third program state, and the second program state has a threshold voltage distribution higher than that of the first program state by one step or more, and a threshold voltage distribution lower than that of the third program state by one step or more, and a first main verification voltage for verifying the first program state is used as a third pre-verification voltage for verifying the third program state.

Abstract: A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: A reference column of a semiconductor memory includes a reference bit line; a reference source line; and first to Nth resistive memory cells disposed between the reference bit line and the reference source line. Data of a first state is stored in the first resistive memory cell and data of a second state is stored in the Nth resistive memory cell before a read operation, and the first and Nth resistive memory cells form current paths between the reference bit line and the reference source line in the read operation.

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract: Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.

Abstract: A method can include programming programmable resistive elements (PREs) in a first integrated circuit (IC) device to establish functions of configurable circuits of the first IC device; and creating at least one second IC device by forming non-programmable connections based on resistive states of the PREs of the first IC device to provide the functions of the first IC device in the second IC device.

Abstract: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.

Abstract: A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation.

Abstract: A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of normal memory cells, a select transistor, and a dummy memory cell. The semiconductor memory device may include a voltage generator configured for generating a program voltage applied to a normal memory cell selected among the plurality of normal memory cells, and for generating a dummy word line voltage applied to the dummy memory cell in a program operation. The semiconductor memory device may include a control logic configured for controlling the voltage generator to adjust the dummy word line voltage based on the program voltage.

Abstract: The present invention relates to 3D memory devices and methods for programming such devices, and more particularly to memory devices having control circuitry which is responsive to the indicator memory to apply a first control voltage to a selected one of the horizontal structures, apply a second control voltage to a non-selected one of the horizontal structures, and apply a third control voltage to an excluded one of the horizontal structures.

Abstract: In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells.

Abstract: Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed.

Abstract: A method transfers read data from a flash memory to a controller synchronously with respect to a data strobe signal during a read data transfer period. During an initial control period of the read data transfer period, the cycle of the data strobe signal is expanded such that a pulse width of the resulting cycle-controlled data strobe signal is greater than a pulse width of the data strobe signal.

Abstract: A non-volatile memory device with a current injection sensing amplifier is disclosed.

Abstract: A non-volatile memory has an ADC that digitizes an analog voltage in a range delimited by V1 and V2 into N intervals, resulting in a digital Vx with x between 1 to N. A ramp voltage Vramp(x) calibrated to rise linearly from V1 to V2 in x=1 to N clock cycles is used to scan the analog voltage. Vx is then given by Vx=Vramp(x). The ramp voltage is provided by a constant current charging a capacitor and has a slope proportional to a DAC resistor, R(x) that is programmable from 1 to N. In a calibration mode, the R(x) is set to N, which results in K clock cycles spanning V1 to V2. In a subsequent normal mode, the DAC resistor is reset to R(K) to result in a calibrated ramp voltage that would rise from V1 to V2 in N clock cycles.

Abstract: Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.

Abstract: Providing for a memory cell capable of operating a one time programmable, multi-level cell memory is described herein. In some embodiments, a program signal having a first polarity and a first current compliance is applied to a memory cell. In an aspect, the memory cell is switched to a first program state from a non-program state in response to the first program signal. Furthermore, in an embodiment, an additional program signal having a second polarity is applied to the memory cell. In another aspect, the memory cell is switched to an additional program state different from the first program state in response to the additional program signal, wherein: the memory cell inherently resists switching back from the additional program state to the first program state, and the second polarity is opposite to the first polarity.

Abstract: A method of reading an antifuse in a semiconductor memory device during a power-up routine includes; generating a read voltage used during an antifuse read operation performed during the power-up routine to read data stored in an antifuse cell array of the antifuse, and beginning execution of the antifuse read operation only after an activation delay has elapsed following a sensing of the level of the read voltage.

Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.

Abstract: A shift register unit, a shift register circuit, an array substrate and a display device can avoid a phenomenon that light lines and dark lines appear alternately in a horizontal direction in a gray scale state when the display device is lighted up normally, wherein the phenomenon is generated because a clock signal causes an abnormal output of a gate scanning voltage of the shift register unit when a frame start signal comes. The shift register unit comprises a capacitor (C1), a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a voltage pulling-down control module. The shift register unit, the shift register circuit, the array substrate and the display device can be used for the manufacture of a display.

Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.