Abstract: Provided are methods and apparatus for functionalizing a substrate surface used as the channel in a gate stack. Silicon, germanium and silicon germanium substrates surfaces are functionalized with one or more of sulfur and selenium by plasma processing.

Abstract: Semiconductor processing systems are described including a process chamber. The process chamber may include a lid assembly, grid electrode, conductive insert, and ground electrode. Each component may be coupled with one or more power supplies operable to produce a plasma within the process chamber. Each component may be electrically isolated through the positioning of a plurality of insulation members. The one or more power supplies may be electrically coupled with the process chamber with the use of switching mechanisms. The switches may be switchable to electrically couple the one or more power supplies to the components of the process chamber.

Abstract: A method for combinatorially processing a substrate is provided. The method includes introducing a first etchant into a reactor cell and introducing a fluid into the reactor cell while the first etchant remains in the reactor cell. After initiating the introducing the fluid, contents of the reactor cell are removed through a first removal line and a second removal line, wherein the first removal line extends farther into the reactor cell than the second removal line. A level of the fluid above an inlet to the first removal line is maintained while removing the contents. A second etchant is introduced into the reactor cell while removing the contents through the first removal line and the second removal line. The method includes continuing the introducing of the second etchant until a concentration of the second etchant is at a desired level, wherein the surface of the substrate remains submerged.

Abstract: A method for creating a pattern on a substrate (101) is presented, the method comprises: providing a substrate (101) comprising silicon; creating a sacrificial layer (102) on the substrate (101), wherein the sacrificial layer is formed on a first surface area (101a) of the substrate thereby leaving a second surface area (101b) exposed; depositing a first functional layer (103) at least on the second surface area (101b) of the substrate (101); removing the sacrificial layer (102); wherein: removing the sacrificial layer (102) is performed by etching the sacrificial layer (102) with an acidic aqueous solution that does not adversely affect the first functional layer (103) and the substrate (101).

Abstract: In one embodiment of the present invention, there is provided a method for etching a multilayer film formed by laminating a plurality of alternating layers of a first layer having a first dielectric constant and a second layer having a second dielectric constant. This method includes (a) a multilayer film etching step, in which an etchant gas is supplied into a processing chamber and a microwave is supplied into the processing chamber to excite a plasma of the etchant gas; and (b) a resist mask reducing step in which an oxygen-containing gas and a fluorocarbon-based gas are supplied to the processing chamber and a microwave is supplied into the processing chamber to excite a plasma of the oxygen-containing gas and the fluorocarbon-based gas. In this method, the steps (a) and (b) are alternately repeated.

Abstract: An etching processing method for etching a substrate formed with a target film and a mask film is performed in a substrate processing apparatus including a first and a second power supply for respectively supplying a higher and a lower high frequency power to a processing space and a mounting table, and a DC power supply for supplying a DC power to an electrode. The method includes a modification step for modifying a shape of a pattern formed on the mask film; and an etching step for etching the target film by using the mask film. The mask film is etched by the plasma in the modification step. Further, in the etching step, the DC power is applied to the electrode and the lower high frequency power is applied to the mounting table in a pulse wave form in which a higher and a lower power level are repeated.

Abstract: A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask and the non-porous carbon layer are removed with a gas-phase etch using plasma effluents formed in a remote plasma from a chlorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the non-porous carbon layer and the titanium nitride.

Abstract: A semiconductor device manufacturing method includes performing reactive ion etching of the film containing a metal disposed on the bottom of the first groove and the film containing a metal disposed on the bottom of the second groove under a same condition in a state where the substrate is heated to the target temperature.

Abstract: A method of polishing a wafer at the die level with a targeted slurry delivery system. The wafer is placed on a wafer carrier exposing the top side of the wafer, the wafer contains a die. The polishing apparatus will polish a portion of the die using a pad that is smaller than the die and the pad is located above the die. A slurry is applied to a portion of the die being polished. Embodiments of the invention provide multiple pads working on the same die.

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.

Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Abstract: A substrate processing apparatus 1 includes a substrate processing unit 40 configured to process a substrate W by supplying a mixed liquid M of a first liquid C and a second liquid D to the substrate W, a first flow rate regulator 10 disposed in a first supply pipe 31 configured to allow the first liquid C to flow therethrough, and the first flow rate regulator 10 configured to measure a flow rate by a differential pressure and to regulate the flow rate, a second flow rate regulator 20 disposed in a second supply pipe 32 configured to allow the second liquid D to flow therethrough, and the second flow rate regulator 20 configured to measure a flow rate by a differential pressure and to regulate the flow rate, a concentration meter 51 disposed in a mixed liquid pipe 33 configured to guide the mixed liquid M with a mixture of the first liquid C having passed through the first flow rate regulator 10 and the second liquid D having passed through the second flow rate regulator 20 to the substrate processing unit 4

Abstract: A processing tool includes a chamber configured to receive a wafer, the chamber having a sidewall and a sidewall heating source configured to heat the sidewall of the chamber. The processing tool further includes a first heating source configured to provide energy to an interior of the chamber through a top surface of the chamber and a second heating source configured to provide energy to the interior of the chamber through a bottom surface of the chamber. The sidewall heating source is separate from the first heating source and the second heating source.

Abstract: A pick tool for picking a planar object from a supply station is presented, in particular to be used for picking a semiconductor die from a carrier tape, said pick tool comprising: a work surface, said work surface comprising at least one contact region that may be brought into contact with a first surface on a first side of the planar object; one or more vacuum outlets in the work surface that may be connected to a vacuum source to allow for temporarily fixing the planar object to the work surface; and wherein a flexible seal is provided to maintain vacuum if the planar object becomes deformed.

Abstract: A substrate can be appropriately accommodated in a cassette. A substrate transfer device includes a substrate transfer unit that delivers the substrate with respect to the cassette configured to accommodate the substrate; a detection unit that detects the substrate accommodated in the cassette; and a control device than controls the substrate transfer unit.

Abstract: The present invention provides a guide apparatus including a guide member located on a base, and a moving member movable along the guide member. The guide apparatus comprising a plurality of plate members each including a portion facing the base and extending from the portion in a direction to separate from the base, wherein the plurality of plate members are located apart from each other in a direction to separate from the moving member.

Abstract: Systems and methods for providing wafer access in a wafer processing system are disclosed herein. The methods may include docking a first wafer cassette on the wafer processing system and removing a selected wafer from the first wafer cassette with the wafer processing system. The methods further may include performing a process operation on the selected wafer with the wafer processing system and undocking the first wafer cassette from the wafer processing system while performing the process operation. The methods also may include docking a second wafer cassette (which may be the same as or different from the first wafer cassette) on the wafer processing system, inventorying the second wafer cassette with the wafer processing system, and/or subsequently placing the selected wafer in the second wafer cassette. The systems may include wafer processing systems that include a controller that is programmed to perform at least a portion of the methods.

Abstract: A rotary positioning apparatus includes a fixing base, a rotation mechanism, two driving modules and a carrier. The rotation mechanism is disposed on the fixing base, the first driving module is disposed on the fixing base and coupled to the rotation mechanism to drive the rotation mechanism rotating around a first rotation axis relatively to the fixing base. The carrier has plural accommodating slots on a circular-arc surface thereof and is pivoted to the rotation mechanism through a second rotation axis passing through the curvature center of the circular-arc surface and perpendicular to the first rotation axis, on which the curvature center is located. The second driving module is disposed on the rotation mechanism and coupled to the carrier to drive the carrier rotating around the second rotation axis relatively to the rotation mechanism. An automatic pick-and-place system and an operation method using the rotary positioning apparatus are also provided.

Abstract: Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure.

Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract: A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating patterns having a stair structure and being alternately stacked, pad patterns connected to end portions of upper surfaces of the conductive patterns exposed through the stair structure, and a channel film penetrating the conductive patterns and the interlayer insulating patterns.

Abstract: A method includes forming a barrier layer in a via hole and over a hard mask layer. The hard mask layer is disposed over a dielectric layer. The via hole is located through the dielectric layer and the hard mask layer. A filler layer is formed in the via hole and over the barrier layer. The filler layer and the hard mask layer are removed. A metal layer is formed in the via hole.

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract: A method includes forming a stack of materials including a first dielectric layer having a conductive feature positioned therein, and a second dielectric layer positioned above the first dielectric layer. An etch mask including a plurality of spaced apart mask elements is formed above the second dielectric layer. The mask elements define at least a first via opening exposing the second dielectric layer. A patterning layer is formed above the etch mask. A second via opening is formed in the patterning layer to expose the first via opening in the etch mask. The second dielectric layer is etched through the second via opening to define a third via opening in the second dielectric layer exposing the conductive feature. The patterning layer and the etch mask are removed. A conductive via contacting the conductive feature is formed in the third via opening.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract: Provided is a method for forming a two-dimensional array of semiconductor quantum confined structures. The method includes providing a layer that has first atoms and second atoms, the first atoms having a different size than the second atoms; providing an indenter template that includes at least one indenter structure extending from a surface of the indenter template; contacting the layer and the at least one indenter structure together with a pressure sufficient to generate an elastic deformation in the layer but without generating plastic deformation of the layer; annealing the layer; and forming at least one quantum confined structure in a region of the layer in a region of the layer not pressed by the at least one indenter structure.

Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

Abstract: A method includes selectively degrading a current capacity of a first finned-field-effect-transistor (finFET) relative to a second finFET by forming a material on a fin of the first finFET to increase a current resistance of the first finFET. The second finFET is electrically connected to the first finFET in a circuit such that a current flow through the second finFET is a multiple of a current flow through the first finFET.

Abstract: An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity.

Abstract: A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes providing a first patterned photo resist layer having an etch coating layer disposed thereon and using the first patterned photo resist layer and the etch coating layer to pattern an underlying layer. The patterned underlying layer is then used as a masking element when etching the substrate pattern into the substrate. A second photo resist pattern is formed over the substrate pattern. An overlay measurement is executed of the second photo resist pattern to the substrate pattern.

Abstract: A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.

Abstract: A method of monitoring an OLED production process for making an OLED device is disclosed. According to the method, at least one reference OLED device similar to said OLED device is fabricated. Said at least one reference OLED device has a layered structure corresponding to said OLED device and a range of hole injection and/or transport layer thicknesses. A spectral variation of a light output of said at least one reference OLED device with respect to variation in said hole injection and/or transport layer thickness is characterized. A said OLED device is partially fabricated by depositing one or more layers comprising at least said hole injection and/or transport layer and a thickness of said one or more layers is measured such that a light output for said partially fabricated OLED device can be predicted, in a target color space, from said measuring, using said characterized spectral variation.

Abstract: A power semiconductor module includes a metal plate having a through hole with an eaves; an insulated metal block including a metal block having an element mounting region on an upper surface, and an insulating layer on surfaces other than the upper surface and a portion of the upper surface other than the element mounting region; a circuit pattern disposed over the metal plate with the insulating material interposed therebetween; a power semiconductor element fixed to the element mounting region of the upper surface of the metal block; and a connection conductor connecting the power semiconductor element and the circuit pattern. The insulated metal block is fitted into the through hole in the metal plate so that the insulating layer on the upper surface of the insulated metal block contacts the eaves of the through hole to electrically insulate between the metal block and the metal plate.

Abstract: A module IC package structure for increasing heat-dissipating efficiency includes a substrate unit, an electronic unit, a package unit, a first heat-dissipating unit and a second heat-dissipating unit. The substrate unit includes a circuit substrate. The electronic unit includes a plurality of electronic components disposed on the circuit substrate and electrically connected to the circuit substrate. The package unit includes a package gel body disposed on the circuit substrate for enclosing the electronic components. The first heat-dissipating unit includes a heat-dissipating base layer disposed on the top surface of the package gel body. The second heat-dissipating unit includes a plurality of heat-dissipating auxiliary layers disposed on the top surface of the heat-dissipating base layer. Whereby, the heat-dissipating efficiency of the module IC package structure can be increased by matching the heat-dissipating base layer and the heat-dissipating auxiliary layers.

Abstract: A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment.

Abstract: The present invention is intended to increase the moisture resistance of a resin-sealed electronic control device. The resin-sealed electronic control device includes: a semiconductor chip; a chip capacitor; a chip resistor; a bonding member; a substrate; a case; a heat radiating plate; a glass coating; and a first sealing material. The glass coating directly covers the electronic circuit formed by the element group including: the semiconductor chip; the chip capacitor; and the chip resistor, the bonding member and the substrate, and is sealed by the first sealing material. By being water impermeable, the glass coating prevents water absorption in the vicinity of the element group, and can prevent an increase in the leak current of the semiconductor chip due to water absorption, and an insulation performance drop such as lowered insulation resistance caused by migration within the element group.

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.

Abstract: A drive circuit device includes a circuit board having a multilayer structure, which includes first to fourth circuit conductor layers, and first to third insulating layers; and heat sinks that dissipate heat of the circuit board to an outside. An upper FET state is embedded in the first insulating layer, and a lower FET state is embedded in the second insulating layer. The upper FET and the lower FET are disposed so that a region in which the upper FET is positioned and a region in which the lower FET is positioned overlap each other in a stacking direction. A lead-out portion is formed at a second circuit pattern of the circuit conductor layer, the lead-out portion extending from the circuit board in a direction orthogonal to the stacking direction, and being connected to the heat sinks so that heat is transferred to the heat sinks.

Abstract: A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This continuous cooling channel may provide a path for a cooling source such as a fluid pumped from an external fluidic-cooling circulation driver to make physical contact locally with and cool the back end levels within the IC chip that may generate heat as a byproduct of the IC device's routine operations. Such a cooling structure is achieved by removing a horizontal portion of a barrier layer from an intermediate region of an interlevel interconnect structure, selective to a vertical portion of the barrier layer located on a sidewall of the interlevel interconnect structure, using gas cluster ion beam etching as well as removing the bulk conductor by additional means.

Abstract: A semiconductor device provided herewith includes a semiconductor substrate; a brazing material bonded to the semiconductor substrate; a heat sink connected to the semiconductor substrate via the brazing material and a resin. The heat sink includes a protruding portion formed outside of a range in which the heatsink is connected to the semiconductor substrate via the brazing material. The protruding portion is making contact with the brazing material. The resin seals the semiconductor substrate, the brazing material and the protruding portion.

Abstract: A semiconductor assembly, power semiconductor module, a housing and methods for assembling the power semiconductor housing is disclosed. One embodiment provides an electrically insulating substrate has an inner housing having a cover and a peripheral rim, and at least one pressure element arranged adjacent a side-face of the peripheral rim. The pressure element is resiliently coupled to the inner housing.

Abstract: A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

Abstract: In an embodiment an electronic component includes a semiconductor die having a first surface, the first surface including a first current electrode and a control electrode. The electronic component further includes a die pad having a first surface, a plurality of leads and a gull-wing shaped conductive element coupled to a first lead of the plurality of leads. The first current electrode is mounted on the die pad and the gull-wing shaped conductive element is coupled between the control electrode and the first lead.