Abstract: Provided is a semiconductor device in which a reverse leakage current is suppressed and the mobility of a two-dimensional electron gas is high. A semiconductor device includes: an epitaxial substrate in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane is substantially in parallel with a substrate surface; and a Schottky electrode. The epitaxial substrate includes: a channel layer made of a first group-III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0); an intermediate layer made of GaN adjacent to the barrier layer; and a cap layer made of AlN and adjacent to the intermediate layer. A Schottky electrode is bonded to the cap layer.

Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both re-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. The etch stop layer includes the etch stop layer comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer.

Abstract: A field effect transistor includes multi-finger electrodes, a gate terminal electrode, a drain terminal electrode, a source terminal and a source terminal electrode. Each of the multi-finger electrodes includes two finger gate electrodes, a finger drain electrode, and at least two finger source electrodes. Finger electrodes are arranged so as to intersect with the first straight line at an angle of approximately +45 degrees and approximately ?45 degrees alternately. The gate terminal electrode commonly bundles and connects the finger gate electrodes of two adjacent cell regions. The drain terminal electrode commonly bundles and connects the finger drain electrodes of two adjacent cell regions. And the source terminal electrode commonly bundles and connects the finger source electrodes of two adjacent cell regions. The gate terminal electrodes and the drain terminal electrodes are alternately provided in a connecting region of the multi-finger electrodes of two adjacent cell regions.

Abstract: A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.

Abstract: A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes: a drift region, a source region, and a body region arranged between the source and drift regions; a diode region and a pn junction between the diode and drift regions; a trench having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; a gate electrode in the trench and dielectrically insulated from the body, diode and drift regions by a gate dielectric. The diode region has a lower diode region arranged below the trench bottom, and the lower diode region has a maximum of a doping concentration distant to the trench bottom. A corresponding method of manufacturing the device also is provided.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.

Abstract: A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions.

Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract: One illustrative device disclosed herein includes, among other things, a dielectric layer disposed above a source/drain region and a gate structure of a transistor, a first conductive contact positioned in the dielectric layer and contacting the gate structure, wherein a first spacer is disposed on a sidewall of the first conductive contact, and a second conductive contact positioned in the dielectric layer and contacting the source/drain region, wherein the first spacer at least partially defines a spacing between the first conductive contact and the second conductive contact.

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract: A thin film transistor is disclosed in the present invention. The thin film transistor comprises: a substrate, an active layer, a first etching barrier layer, a second etching barrier layer, a source and a drain, wherein: the active layer is disposed over the substrate; the first etching barrier layer is disposed over the active layer; the second etching barrier layer is disposed over the first etching barrier layer; the source and the drain are disposed over the second etching barrier layer, and are connected to each other through the active layer by means of via holes formed in the first etching barrier layer and the second etching barrier layer by etching; and a length of the first etching barrier layer at a channel position is less than a length of the second etching barrier layer. A method of manufacturing the thin film transistor, an array substrate and a display apparatus are also disclosed in the present invention.

Abstract: A thin film transistor, a method of manufacturing the thin film transistor, and a display device including the thin film transistor are provided. The thin film transistor comprises an oxide semiconductor layer, a gate electrode, a source electrode and a drain electrode formed on a substrate in a coplanar configuration. A first conductive member is in direct contact with the oxide semiconductor layer and in direct contact with the source electrode. A second conductive member is in direct contact with the oxide semiconductor layer and in direct contact with the drain electrode. The first conductive member and the second conductive member are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes.

Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.

Abstract: To provide an oxide semiconductor film having stable electric conductivity and a highly reliable semiconductor device having stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film contains indium (In), gallium (Ga), and zinc (Zn) and includes a c-axis-aligned crystalline region aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed. Further, the composition of the c-axis-aligned crystalline region is represented by In1+?Ga1-?O3(ZnO)m (0<?<1 and m=1 to 3 are satisfied), and the composition of the entire oxide semiconductor film including the c-axis-aligned crystalline region is represented by InxGayO3(ZnO)m (0<x<2, 0<y<2, and m=1 to 3 are satisfied).

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.

Abstract: A non-volatile semiconductor storage device disclosed in the embodiment has a semiconductor substrate, a first insulating film, a first charge storage film, a second insulating film, a second charge storage film, a third insulating film, and a control electrode. In this non-volatile semiconductor storage device, the first and second charge storage films comprise a metallic material, a semi-metallic material or a semiconductor material. One of the first, second, and third insulating films is a multi-layered insulating film formed by layering multiple insulating films. This non-volatile semiconductor storage device further has a film comprising of any one of an oxide film, nitride film, boride film, sulfide film, and carbide film that is in contact with one interface of the laminated insulating film and contains one type of atom selected from aluminum, boron, alkaline earth metal, and transition metal at a concentration in the range of 1E12 atoms/cm2 to 1E16 atoms/cm2.

Abstract: A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.

Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

Abstract: The semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor, a trench that is selectively formed on a surface portion of the semiconductor layer and that defines a unit cell having a predetermined shape on the surface portion, and a surface electrode that is embedded in the trench so as to cover an upper surface of the unit cell and that forms a Schottky junction between the unit cell and the surface electrode, and side surfaces of the trench are formed of only a plurality of planes that have plane orientations crystallographically equivalent to each other.

Abstract: A method of manufacturing a circuit board includes: forming a plurality of metal electrodes so as to be separated from each other on a holding sheet by cutting a metal foil held on the holding sheet to remove a portion of the metal foil; forming adhesive layers on surfaces of the plurality of metal electrodes; adhering the adhesive layers to a base material by closely contacting the adhesive layers with the base material; and transcribing the adhesive layers and the plurality of metal electrodes onto the base material by detaching the holding sheet from the plurality of metal electrodes.

Abstract: The disclosure relates to a method for localizing and quenching an arc in a PV generator of a PV system, wherein the PV generator includes at least two PV subgenerators. An arc quenching circuit is associated with each PV subgenerator. The method includes detecting an arc in the PV generator. Then, a probability value is determined for each of the PV subgenerators, wherein the probability value is correlated with a probability that the arc is located in the corresponding PV subgenerator. A sequence for activating the arc quenching circuits is then determined that is dependent on the determined probability values. Then, the arc quenching circuits are activated successively in the order of the determined sequence.

Abstract: A light sensing device includes a substrate, a plurality of light sensing elements and a cover. The plurality of light sensing elements are disposed on the substrate for sensing light. The cover is utilized for sheltering the plurality of light sensing elements, wherein the cover includes a hole for passing the light. A set of the plurality of light sensing elements is selected to be enabled according to a location of the hole relative to the plurality of light sensing elements.

Abstract: An electronic device includes a substrate plate with a traversing passage. An electronic component, mounted to the substrate plate, includes an integrated circuit chip with an optical sensor and an opaque protective plate mounted above the sensor. The electronic component is mounted with the chip facing the substrate plate such that the protective plate is engaged with the traversing passage. Electrical connection elements extend between the chip and the substrate plate. An internal block of encapsulation material extends into the traversing passage of the substrate plate between the chip and the substrate plate so as to embed the electrical connection elements.

Abstract: A front sheet of solar cell, a method of manufacturing the same and a photovoltaic module are provided. The front sheet of solar cell can effectively block infrared rays (IRs) by forming an IR blocking layer including a cholesteric liquid crystal (CLC) material on a substrate. Thus, an increase in temperature of a cell can be suppressed so that the power generation efficiency of the cell can be improved. Also, the multi-layered sheet can be configured so that a UV blocking layer including a fluorine-based polymer and a wavelength conversion material can be formed on the IR blocking layer. Thus, wavelengths of a UV region can be converted into wavelengths of a VR region so that the power generation efficiency of the cell can be improved, and discoloration and deformation caused by UVs can be prevented so that the weather resistance can be improved.

Abstract: A method of processing a solar cell is disclosed, where the edges of the solar cell are covered, coated or masked during the ion implantation process and/or the screen printing process. This covering may be a substance that blocks the penetration of ions during implantation, or may be a substance that resists the diffusion of fritted metal paste during the metallization process. In some embodiments, the edges are covered during both of these processes. In further embodiments, the same material may perform both functions.

Abstract: A solar cell can include a substrate of a first conductive type; an emitter layer of a second conductive type opposite the first conductive type, and positioned on the substrate; a plurality of finger electrodes formed in a first direction, each finger electrode being electrically connected to the emitter layer; a plurality of first collector regions; a plurality of first electrodes positioned in a plurality of first collector regions and extending in the first direction from the plurality of finger electrodes; a plurality of second electrodes positioned in the plurality of first collector regions and formed in a perpendicular direction crossing the first direction; a plurality of third electrodes positioned in the plurality of first collector regions, connecting two neighboring first electrodes of the plurality of first electrodes and formed in the perpendicular direction; and a plurality of deletions positioned in the plurality of first collector regions.

Abstract: Fabricating a wafer-scale spacer/optics structure includes replicating optical replication elements and spacer replication sections directly onto an optics wafer (or other wafer) using a single replication tool. The replicated optical elements and spacer elements can be composed of the same or different materials.

Abstract: The infrared sensor includes: an infrared sensor chip in which a plurality of pixel portions each including a temperature-sensitive portion formed of a thermopile is disposed in an array on one surface side of a semiconductor substrate; and an IC chip that processes an output signal of the infrared sensor chip. A package includes a package main body on which the infrared sensor chip and the IC chip are mounted to be arranged side-by-side, and a package cover that has a lens transmitting infrared rays and is hermetically bonded to the package main body. The package is provided therein with a cover member that includes a window hole through which infrared rays pass into the infrared sensor chip and equalizes amounts of temperature change of hot junctions and cold junctions among the pixel portions, the temperature change resulting from heating of the IC chip.

Abstract: A sensor unit includes a metallic base member, a solid-state imaging element, and amplifier chips. The base member has a first placement surface and a second placement surface. The solid-state imaging element has a photodetecting surface, and is disposed on the first placement surface such that a rear surface and the first placement surface face each other. The amplifier chips are mounted on a substrate disposed on the second placement surface. The base member further has side wall portions facing side surfaces of the solid-state imaging element. The chips and the solid-state imaging element are electrically connected to one another via a bonding wire. The chips are thermally coupled to the base member via a thermal via of the substrate.

Abstract: Disclosed are three-layer core-shell structure nanoparticles used to form a light absorption layer of solar cells including a core including a copper (Cu)-containing chalcogenide, and (i) a first shell including a tin (Sn)-containing chalcogenide and a second shell including a zinc (Zn)-containing chalcogenide; or (ii) a first shell including a zinc (Zn)-containing chalcogenide and a second shell including a tin (Sn)-containing chalcogenide, and a method of manufacturing the same.

Abstract: Photodetector devices and methods for making the photodetector devices are disclosed herein. In an embodiment, the device may include a substrate; and one or more core structures, each having one or more shell layers disposed at least on a portion of a sidewall of the core structure. Each of the one or more structures extends substantially perpendicularly from the substrate. Each of the one or more core structures and the one or more shell layers form a Schottky barrier junction or a metal-insulator-semiconductor (MiS) junction.

Abstract: A method for producing a heterojunction solar cell including the following successive steps: providing a substrate made from crystalline semiconductor material, doped with a first type of doping, and provided with a first main face; depositing a first layer of intrinsic amorphous semiconductor material on said first main face of the substrate; and forming a second layer of amorphous semiconductor material on the first layer. The method includes deposition of a barrier layer between the first and second layers, said barrier layer being of different nature from those of the first and second layers and includes doping of the second layer by ion implantation.

Abstract: In a solar cell in a sheet form, a first cured resin layer, a substrate containing a resin, a photoelectric conversion layer, and a second cured resin layer are stacked in this order. The linear expansion coefficient of the first cured resin layer is not less than that of the second cured resin layer, and the linear expansion coefficient of the second cured resin layer is larger than that of the substrate. When the cure degree of a first surface of the first cured resin layer facing the substrate is C1 % and the cure degree of a second surface of the first cured resin layer is C2 %, C2 is larger than C1 and (C2?C1) is 2 to 15%. A surface on the first cured resin layer of the solar cell is warped convexly and a surface on the second cured resin layer is warped concavely.

Abstract: An attachment member and a solar cell array are disclosed. The attachment member includes a first member; a second member on the first member; and a fixing member that fixes the first and second members. The first member includes a bottom portion; two first side walls facing each other. The second member includes a top portion; two second side walls facing to each other. The first and the second side walls are alternately arranged and face to each other. Each of the first and second side walls comprises an engagement portion. The engagement portion of one of the first side walls adjustably engages in height direction with the engagement portion of one of the second side walls. The engagement portion of the other one of the first side walls adjustably engages in height direction with the engagement portion of the other one of the second side walls.

Abstract: A high-speed germanium on silicon (Ge/Si) avalanche photodiode may include a substrate layer, a bottom contact layer disposed on the substrate layer, a buffer layer disposed on the bottom contact layer, an electric field control layer disposed on the buffer layer, an avalanche layer disposed on the electric field control layer, a charge layer disposed on the avalanche layer, an absorption layer disposed on the charge layer, and a top contact layer disposed on the absorption layer. The electric field contact layer may be configured to control an electric field in the avalanche layer.

Abstract: A photo-detecting device includes a first nitride layer, a light absorption layer disposed on the first nitride layer, and a Schottky junction layer disposed on the light absorption layer. According to a photoluminescence (PL) properties measurement of the photo-detecting device, a first peak light intensity is greater than a second peak light intensity, and the first peak light intensity is a peak light intensity of light emitted from the light absorption layer, and the second peak light intensity is a peak light intensity of light emitted from the first nitride layer.

Abstract: The light receiving/emitting device uses an integrated light receiving/emitting element wherein a light receiving element and a light emitting element are provided on one main surface of a substrate. The substrate comprises a first-conductivity-type semiconductor. At least one electrode layer is placed in an area corresponding to at least the light receiving element and the light emitting element on the other main surface of the substrate. The light receiving element comprises: a first second-conductivity-type semiconductor layer formed on the one main surface of the substrate; a first anode electrode formed on the top surface of the first second-conductivity-type semiconductor layer; and a first cathode electrode formed on the top surface of the one main surface of the substrate. The electrode layer, the first anode electrode and the first cathode electrode have the same electric potential.

Abstract: A photonic conversion layer receives incoming photons in a plurality of X-ray bands, the incoming photons passing through an item on a path from an X-ray source to the photonic conversion layer. The incoming photons are converted in each X-ray band of the plurality of X-ray bands to outgoing photons in corresponding different converted bands in the visible-to-near infrared (VNIR) spectrum. The outgoing photons are emitted in the corresponding different converted bands in the VNIR spectrum. A sensor detects the outgoing photons in the corresponding different converted bands in the VNIR spectrum and generates output data representative of the outgoing photons. Image data is generated based on the output data.

Abstract: An optical module package includes a substrate having a recessed portion, a cover covered on the substrate and defining with the substrate a first chamber and a second chamber therebetween, the cover having a light-emitting hole disposed in communication with the first chamber, a light-receiving hole disposed in communication with the second chamber and a stop wall positioned in the recessed portion to separate the first chamber and the second chamber, a light-emitting chip and a light-receiving chip mounted at the substrate and respectively disposed in the first chamber and the second chamber, and two encapsulation colloids respectively mounted in the first chamber and the second chamber and respectively wrapped about the light-emitting chip and the light-receiving chip. Thus, the optical module package not only can prevent crosstalk but also can greatly reduce the manufacturing cost and the level of difficulty.

Abstract: A conductive contact pattern is formed on a surface of solar cell by forming a thin conductive layer over at least one lower layer of the solar cell, and ablating a majority of the thin conductive layer using a laser beam, thereby leaving behind the conductive contact pattern. The laser has a top-hat profile, enabling precision while scanning and ablating the thin layer across the surface. Heterocontact patterns are also similarly formed.

Abstract: The invention relates to a method of manufacturing a I-III-VI2 layer with photovoltaic properties, comprising: deposition of a metal on a substrate to form a contact layer, deposition of a precursor of the photovoltaic layer, on the contact layer, and heat treatment of the precursor with an addition of element VI to form the I-III-VI2 layer. The element VI usually diffuses into the contact layer (MO) during the heat treatment and combines with the metal to form a superficial layer (SUP) on the contact layer. In the method of the invention, the metal deposition comprises a step during which an additional element is added to the metal to form a compound (MO-EA), in the contact layer, acting as a barrier to the diffusion of the element VI, which allows precisely controlling the properties of the superficial layer, particularly its thickness.

Abstract: The object cutting method comprises a step of locating a converging point of laser light within a monocrystal sapphire substrate, while using a rear face of the monocrystal sapphire substrate as an entrance surface of the laser light, and relatively moving the converging point along each of a plurality of lines to cut set parallel to the m-plane and rear face of the substrate, so as to form first and second modified regions within the substrate along each line and cause a fracture to reach a front face. In this step, in each line, with respect to a tilted surface passing the first region while being parallel to the r-plane of the substrate, the second region is positioned on the side where the tilted surface and rear face form an acute angle.

Abstract: In some embodiments, a substrate carrier for holding a plurality of substrates comprises a disk formed of a continuous material to a nominal dimension which is approximately a multiple of a nominal dimension of a standard substrate size used in the manufacture of light emitting diode devices. In an embodiment, the disk is formed symmetrically about a central axis and defines a substantially planar upper surface. A first pair of pockets is defined in the upper surface of the disk, wherein the disk and each of the first pair of pockets are bisected by a first reference plane passing through the central axis. A second pair of pockets is defined in the upper surface of the disk, wherein the disk and each of the second pair of pockets are bisected by a second reference plane passing through the central axis.

Abstract: A light-emitting device is disclosed and comprises: a transparent substrate; a semiconductor light-emitting stack on the transparent substrate, wherein the semiconductor light-emitting stack comprises a first semiconductor layer close to the transparent substrate, a second semiconductor layer away from the transparent substrate, and a light-emitting layer capable of emitting a light disposed between the first semiconductor layer and the second semiconductor layer; and a bonding layer between the transparent substrate and the semiconductor light-emitting stack, wherein the bonding layer has a gradually changed refractive index, and each of critical angles at the bonding layer and the transparent substrate for the light emitted from the light-emitting layer towards the transparent substrate is larger than 35 degrees.

Abstract: A nanowire comprises a polar semiconductor material that is compositionally graded along the nanowire from a first end to a second end to define a polarization doping profile along the nanowire from the first end to the second end. The polar semiconductor material may comprise a group IH-nitride semiconductor, such as an alloy of GaN and AlN, or an alloy of GaN and InN. Such nanowires may be formed by nucleating the first ends on a substrate, growing the nanowires by depositing polar semiconductor material on the nucleated first ends on a selected growth face, and compositionally grading the nanowires during growth to impart the polarization doping. The direction of the compositional grading may be reversed during the growing of the nanowires to reverse the type of the imparted polarization doping. In some embodiments, the reversing forms n/p or p/n junctions in the nanowires.