Abstract: An integrated circuit device includes an integrated circuit substrate having an at least two piece package thereon. The package has a sealed cavity therein and a patterned metal inductor in the cavity. The inductor has at least a first terminal electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package, which may include a material selected from a group consisting of glass and ceramics, includes a base and a cap sealed to the base. The metal inductor includes a metal layer patterned on at least one of the cap and base of the package. The base may also include first and second electrically conductive vias therein, which are electrically connected to first and second terminals of the inductor.

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Abstract: In a semiconductor device, plate-shaped upper electrodes are formed on a lower electrode with a dielectric film interposed therebetween. The lower electrode, the dielectric film, and the upper electrodes constitute MIM capacitors. One of the upper electrodes and another upper electrode that are adjacent to each other are arranged at an equal distance, without the guard ring being interposed therebetween. The upper electrodes positioned on the outermost periphery and the guard ring positioned outside those upper electrodes are arranged at a distance equal to the distance from each other.

Abstract: A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.

Abstract: To provide an oxide semiconductor film which has high stability and does not easily cause variation in electric characteristics of a transistor, a transistor including the oxide semiconductor film in its channel formation region, and a highly reliable semiconductor device including the transistor. The oxide semiconductor film including indium includes a crystal part whose c-axis is substantially perpendicular to a surface of the oxide semiconductor film. In the crystal part, the length of a crystal arrangement part containing indium and oxygen on a plane perpendicular to the c-axis is more than 1.5 nm. Further, the semiconductor device includes the transistor including the oxide semiconductor film in its channel formation region.

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A high power, high current Unidirectional Transient Voltage Suppressor, formed on SiC starting material is disclosed. The device is structured to avalanche uniformly across the entire central part (active area) such that very high currents can flow while the device is reversely biased. Forcing the device to avalanche uniformly across designated areas is achieved in different ways but consistently in concept, by creating high electric fields where the device is supposed to avalanche (namely the active area) and by relaxing the electric field across the edge of the structure (namely in the termination), which in all embodiments meets the conditions for an increased reliability under harsh environments.

Abstract: An electronic device can include a semiconductor layer having a primary surface, and an isolation structure. The isolation structure can include a first well region within the semiconductor layer and having a first conductivity, a second well region within the semiconductor layer and having a second conductivity type opposite the first conductivity type, and a third well region within the semiconductor layer having the first conductivity type. The second well region can be disposed between the first and third well regions. The first, second, and third well regions can be electrically connected to one another. The electronic device can help to allow more electrons during an electrostatic discharge or similar event to flow where the electrons will be less problematic. A process of forming the electronic device may be implemented with changes to existing masks without adding any processing operations.

Abstract: Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure. Additionally, the clamp device includes a first p-type active region and a first n-type active region in the first p-type well region and electrically connected to a first terminal of the clamp device. Furthermore, the clamp device includes a second p-type active region and a second n-type active region in the second p-type well region and electrically connected to a second terminal of the clamp device. The n-type isolation structure is in a p-type region of a semiconductor substrate, and electrically isolates the first and second p-type well regions from the p-type substrate region. The clamp device further includes a blocking voltage tuning structure positioned between the first and second n-type active regions.

Abstract: An integrated circuit comprises a first cell having first cell height and a first line routed at a first line height and having a first line width. The integrated circuit also comprises a second cell having a second cell height different from the first cell height and a second line routed at a second line height and a second line width different from the first line width. The integrated circuit further comprises a third cell. The third cell has a third line having a first end and a second end. The first end has a first end width. The second end has a second end width. The first end width is equal to the first line width. The second end width is equal to the second line width. The first end is coupled with the first line. The second end is coupled with the second line.

Abstract: A method and apparatus for transforming vertically-aligned nanostructures into densified, horizontally-aligned arrays. A contact element such as a roller is used to topple an array of carbon nanotubes or other nanostructures by drawing or rolling the contact element across the surface of the substrate such that the vertically-aligned nanostructures are forced into at least partial horizontal-alignment while being densified to give the transformed array enhanced properties. The contact element engages the nanostructures at a location below their upper distal end to topple and densify the array without disrupting the relative alignment of the individual nanostructures in the array. Transfer printing of the nanostructures is also provided.

Abstract: An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

Abstract: A display panel including an oxide thin film transistor is disclosed. In the oxide thin film transistor, a part of the active layer between a source region and a drain region is covered with an etch stopper layer, and the etch stopper layer is partially covered by the first electrode and the second electrode of the oxide thin film transistor. The length in which the etch stopper layer is overlapped by the second electrode is greater than the length in which the etch stopper layer is overlapped by the first electrode to suppress threshold voltage shift in the oxide thin film transistor.

Abstract: A semiconductor system for a current sensor in a power semiconductor includes: on a substrate, a multiple arrangement of transistor cells having an insulated gate electrode, whose emitter terminals are connected in a first region via a first conductive layer to at least one output terminal and whose emitter terminals are connected in a second region via a second conductive layer to at least one sensor terminal, which is situated outside of a first cell region boundary, which encloses the transistor cells of the first region and the second region, a trench structure belonging to the first cell region boundary being developed between the transistor cells of the second region and the sensor terminal.

Abstract: A semiconductor device has mesa form first and second p-type base regions and a floating p-type region provided in a surface layer of an n?-type drift layer. The first p-type base region and floating p-type region are separated by a first trench. The second p-type base region is separated from the floating p-type region by a second trench. The first and second p-type base regions are conductively connected to an emitter electrode. The floating p-type region is in a floating state electrically isolated from the emitter electrode. A first gate electrode is provided via a first gate insulating film inside the first trench. An emitter potential second gate electrode is provided via a second gate insulating film inside the second trench. Therefore, di/dt controllability when turning on the semiconductor device can be increased.

Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.

Abstract: A semiconductor device includes a fin-shaped active region protruding from a surface of a base substrate. The fin-shaped active region includes a first impurity region and a second impurity region spaced apart from each other along a first direction and a channel region disposed between the first and second impurity regions. A trench is provided in the base substrate under the channel region. The trench extends in a second direction to intersect the fin-shaped active region in a plan view. A blocking layer fills the trench to overlap with the channel region of the fin-shaped active region. A gate is disposed to overlap with blocking layer and the channel region.

Abstract: The present invention provides a diamond semiconductor device which includes: a diamond substrate; a diamond step section disposed over substrate surface of the diamond substrate having a {001} crystal face to rise substantially perpendicularly to substrate surface; an n-type phosphorus-doped diamond region; and a diamond insulation region. In the diamond step section, a first step section having a {110} crystal face over a side surface is integrated with a second step section having a {100} crystal face over a side surface. The phosphorus-doped diamond region is formed by crystal growth started from base angle of the step shape of the first step section over the side surface of the first step section and substrate surface of the diamond substrate as growth base planes. The diamond insulation region is formed by crystal growth over the side surface of the second step section and substrate surface of the diamond substrate as growth base planes.

Abstract: The element electrodes of a semiconductor element are disposed in a cell region, while an outermost peripheral electrode electrically connected to a semiconductor substrate is disposed in a peripheral region. In the peripheral region, a second-conductivity-type layer is disposed above a super-junction structure. A potential division region is disposed above the second-conductivity-type layer to electrically connect the element electrodes and the outermost peripheral electrode and also divide the voltage between the element electrodes and the outermost peripheral electrode into a plurality of stages. A part of the potential division region overlaps the peripheral region when viewed from the thickness direction of the semiconductor substrate.

Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

Abstract: A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall.

Abstract: An vertical gate-all-around transistor and method of making is provided. The vertical gate-all-around transistor includes a first semiconductor structure extending above a substrate, and a gate structure extending completely around the first semiconductor structure in a plan view. An outermost perimeter of the gate structure comprises a first protruding arcuate section interposed between linear sections, the first protruding arcuate section aligned with the first semiconductor structure.

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the substrate and surrounded at a bottom portion thereof by isolation material, and resistor(s) situated in the gate region(s), the gate regions being filled with undoped dummy gate material. As part of a replacement gate process, the resistor(s) are realized by forming silicide over dummy gate material, i.e., the dummy gate material for the resistor(s) is not removed.

Abstract: A semiconductor device structure and method for forming the semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate electrode formed on the substrate. The semiconductor device structure also includes a first contact structure including a first portion and a second portion. The first portion of the first contact structure is formed in the gate electrode, and the second portion is formed on the first portion.

Abstract: A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is lower than the energy bandgap of the first metal oxide layer and that of the third metal oxide layer. The semiconductor structure includes a metal oxide layer on a substrate, wherein the energy bandgap of the metal oxide layer changes along a direction perpendicular to the surface of the substrate. The present invention also provides a semiconductor process forming said semiconductor structure.

Abstract: A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Abstract: In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region.

Abstract: A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.

Abstract: Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region.

Abstract: A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin having an upper surface and a plurality of side surfaces, forming a sacrificial gate structure comprised of a low-density oxide material having a density of less than 1.8 g/cm3 on and in contact with the upper surface and the side surfaces of the fin and a sacrificial gate material positioned on and in contact with the upper surface of the low-density oxide material, and forming a sidewall spacer adjacent the sacrificial gate structure. The method further includes removing the sacrificial gate material so as to thereby expose the low-density oxide material, so as to define a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract: Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer.

Abstract: The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer.

Abstract: A method of forming trench electrode structures includes forming a first dielectric layer on a semiconductor substrate, forming a second layer above the first dielectric layer and forming an opening which extends through the second layer and the first dielectric layer to the semiconductor substrate such that part of the semiconductor substrate is uncovered. The method further comprises forming an epitaxial layer on the uncovered part of the semiconductor substrate, removing the second layer after forming the epitaxial layer and filling an open space formed by removing the second layer with an electrically conductive material. The electrically conductive material forms an electrode which is laterally surrounded by the epitaxial layer.

Abstract: An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed.

Abstract: Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed.

Abstract: A semiconductor structure, such as a FinFET, etc., includes a bi-portioned junction. The bi-portioned junction includes a doped outer portion and a doped inner portion. The dopant concentration of the outer portion is less than the dopant concentration of the inner portion. An electrical connection is formed by diffusion of the dopants within outer portion into a channel region and diffusion of the dopants within the outer portion into the inner region. A low contact resistance is achieved by a contact electrically contacting the relatively higher doped inner portion while device shorting is limited by the relatively lower doped outer portion.

Abstract: A memory structure having at least substantially aligned floating and control gates. Such a memory structure can include a control gate material disposed between a first insulator layer and a second insulator layer, a floating gate material disposed between the first insulator layer and the second insulator layer and at least substantially aligned with the control gate material, the floating gate material including a metal region, and an interpoly dielectric (IPD) layer disposed between the control gate material and the floating gate material such that the IPD layer electrically isolates the control gate material from the floating gate material.

Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well region having the first conduction type is disposed in the semiconductor layer. A second well and a third well having a second conduction type are disposed to opposite sides of the first well region. The second well and the third well are separated from the first well region. A first anode doped region is disposed in the second well. A second anode doped region and a third anode doped region having the first conduction type are disposed in the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.

Abstract: Provided is a longitudinal bidirectional device in which current flows in a layering direction of a semiconductor layered portion formed on a front surface of a substrate, the bidirectional device comprising a first semiconductor element that includes a first channel and is formed on the semiconductor layered portion; and a second semiconductor element that includes a second channel and is provided on the substrate side of the first semiconductor element within the semiconductor layered portion. The first semiconductor element further includes a first control electrode that controls the first channel and that is formed on a surface of the semiconductor layered portion that faces away from the substrate, and the second semiconductor element is formed on at least a portion of the surface of the semiconductor layered portion on which the first control electrode is formed and includes a second control electrode that controls the second channel.

Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Abstract: A semiconductor device is configured such that the distance between the trench gate in the IGBT and the trench gate in the diode is reduced or a p-well layer is provided between the trench gate in the IGBT and the trench gate in the diode.

Abstract: A shield electrode is formed above a floating p region in a semiconductor layer and connected to a gate electrode in a trench. The shield electrode is composed of a material having an electrical resistivity lower than that of the gate electrode.

Abstract: A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer, N-drift layer and N-type CS layer within the N-drift layer near the top side. Multiple trench structures are formed by polysilicon core and gate oxide layer near the front side. There are active cells and plugged cells on top of the device. The polysilicon cores of the trenches in the active cells are connected to the gate electrode, and the polysilicon cores of the trenches in the plugged cells are connected to the emitter electrode. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and plugged cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in plugged cells are divided by N-drift layer, forming discontinuous P-type regions along the direction of trenches.