Abstract: Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films).

Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.

Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

Abstract: An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.

Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor. The conductive feature further includes a second leg having a second extending direction. The first longitudinal direction and the second extending direction are un-perpendicular and un-parallel to each other. The second leg interconnects the drain of the first pull-up transistor and a gate of the second pull-up transistor.

Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

Abstract: According to various embodiments, a method for processing a carrier may include: doping a carrier with fluorine such that a first surface region of the carrier is fluorine doped and a second surface region of the carrier is at least one of free from the fluorine doping or less fluorine doped than the first surface region; and oxidizing the carrier to grow a first gate oxide layer from the first surface region of the carrier with a first thickness and simultaneously from the second surface region of the carrier with a second thickness different from the first thickness.

Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.

Abstract: A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory layer each has a series of socket components aligned to embed respective floating gates of a group memory cells. This structure allows reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. The memory is fabricated by using odd and even subarrays of vertical shafts on a multi-layer slab to create at different times odd and even socket components that overlap to form continuous word lines with socket components. In particular, with only three masks, the even memory cells are fabricated to have their word line socket component enlarged to overlap with those of the odd memory cells in order to form continuous word lines in the row direction.

Abstract: A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.

Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

Abstract: A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided.

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract: The embodiments of the present invention provide an array substrate, a method for fabricating the array substrate and a display panel. The array substrate comprises a first region and a second region adjoining the first region, a plurality of signal lines are provided in the first region, and a plurality of lead wires connected with the plurality of signal lines are provided in the second region, the array substrate comprises at least one conductive member, each conductive member is connected in parallel with one lead wire, and an overall resistance of the conductive member and the lead wire connected in parallel with the conductive member is smaller than a resistance of the lead wire connected in parallel with the conductive member.

Abstract: In an embodiments of the present invention, since two pixel electrodes are arranged in the pixel unit and each of the pixel electrodes is respectively controlled by a corresponding TFT, the rotation direction of the liquid crystal molecules may be controlled by the voltage difference between the two pixel electrodes, while the voltage on the pixel electrodes of other pixel units in the array substrate is not affected, so that the greenish phenomenon can be avoided. Furthermore, since the two TFTs for controlling the two pixel electrodes respectively may have same parasitic capacitor when the pixel unit is turned off, the voltage difference between the two pixel electrodes is kept unchanged, and thus the occurrence of the image flickering can be avoided.

Abstract: A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of bottom-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also includes a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality pre-reserved blank regions are configured among the scan lines, the data lines and the plurality of sub-pixels; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.

Abstract: A photoelectric conversion device includes a first output line, a second output line; and a photoelectric conversion cell. The photoelectric conversion cell further includes, a photoelectric conversion element configured to generate an output current corresponding to an intensity of incident light, a first switch element configured to transmit the first output current to the first output line according to a first control signal, and a second switch element configured to transmit the second output current to second output line according to a second control signal. As a result, the photoelectric conversion device can be provided to generate rapidly the image data with wide dynamic range without the need for complex control outside of the photoelectric conversion device.

Abstract: The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with respect to the power supply wiring nearly uniform. As a result, it is possible to suppress variation of load capacitance of the vertical signal line for each pixel. It becomes possible to suppress deviation in a black level, variation of charge transfer, and variation of settling. It becomes possible to obtain an image with higher quality.

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Abstract: A solid-state imaging device includes a plurality of photoelectric conversion portions each provided to correspond to each of a plurality of pixels in a semiconductor substrate and receiving incident light through a light sensing surface, and a pixel separation portion that is embedded into a trench provided on a side portion of the photoelectric conversion portion and electrically separates the plurality of pixels in a side of an incident surface of the semiconductor substrate into which the incident light enters. The pixel separation portion is formed by an insulation material which absorbs the incident light entering the light sensing surface.

Abstract: A solid-state imaging apparatus includes: an imaging section having a light-receiving portion for receiving light from an object to image the object; and a substrate on which the imaging section is disposed, wherein a predetermined member provided on the substrate in the neighborhood of the light receiving portion is partially or entirely coated in black.

Abstract: A front-side illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode, transistor gate structures, shallow trench isolation structures, and other associated pixel circuits formed in a semiconductor substrate. Buried light shielding structures that are opaque to light may be formed over regions of the substrate to prevent the transistor gate structures, shallow trench isolation structures, and the other associated pixel circuits from being exposed to stray light. Buried light shielding structures formed in this way can help reduce optical pixel crosstalk.

Abstract: An image sensor includes a first pixel having a first color filter, a first reflection region which reflects light from the first color filter, and a first photoelectric conversion portion arranged in a semiconductor layer and located between the first color filter and the first reflection region, and a second pixel including a second color filter, a second reflection region which reflects light from the second color filter, and a second photoelectric conversion portion arranged in the semiconductor layer and located between the second color filter and the second reflection region. Wavelength corresponding to a maximum transmittance of the first color filter is shorter than wavelength corresponding to a maximum transmittance of the second color filter. An area of the first reflection region is smaller than area of the second reflection region.

Abstract: A method for fabricating a sealed-sidewall device die may include filling grooves of a deeply-grooved device wafer with a sealant, yielding a sealed grooved device wafer. The method may also include forming grooves in a device wafer to yield the deeply-grooved device wafer. The step of forming grooves may include forming a groove that at least partially penetrates each layer of the device wafer. The method may further include masking each device of the deeply-grooved device wafer. A sealed-sidewall device die may include at least one layer including a device substrate layer, a sidewall including a respective surface of each layer of the at least one layer, a sidewall sealant covering the sidewall, and a device formed on the device substrate layer. The sidewall sealant optionally does not cover a top surface of the device. The top surface of the device may directly adjoin an ambient medium thereabove.

Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

Abstract: An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.

Abstract: A backside-illuminated photosensor array IC is formed in a thinned circuit wafer. Silicon is removed in at least one substrate-stripped zone where a doped edge-contact ring surrounds the substrate-stripped zone, the edge-contact ring formed in a same first side of the wafer as a plurality of transistors, and opposite to a backside of the wafer. Backside metal is disposed on the backside of the wafer, the backside metal having window openings over the photosensors, and having sidewalls contacting the edge-contact ring around the substrate-stripped zone. The edge contact region is formed in the first side of the device wafer before providing structural support and thinning the device wafer. Substrate-stripped zones, such as bondpad openings and guardring openings, are formed by removing silicon to expose the edge-contact region, and backside metal is deposited with sidewall metal at edges of the substrate-stripped zones and thereby contacting the edge-contact region.

Abstract: A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.

Abstract: A pixel cell, and a method of use thereof, the pixel cell including: an output, a photosensor configured to generate a first measuring current in a first measurement cycle and a second measuring current in a second measurement cycle as a function of radiation, an output node, a power storage device configured so that in a first operating mode a current can be injected by the power storage device as a function of the first measuring current, and so that in a second operating mode the power storage device is configured to hold the injected current so that the injected current can be detected at the output node, and a switching unit configured to form a difference between the injected current and the second measuring current at the output node in a reading cycle and to couple the output node to the output.

Abstract: A conformable electronic device and methods for forming such devices are described. Embodiments of a conformable electronic device may include a silicon substrate having a thickness of 50 ?m or less. An array of LEDs that are electrically coupled to a controller chip may be formed on a surface of the silicon substrate. In an embodiment, a top passivation layer is formed over the array of LEDs, the one or more controller chips, and the top surface of the silicon substrate. An embodiment also includes a bottom passivation layer formed on a bottom surface of the silicon substrate.

Abstract: A nonvolatile memory device includes an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs, each of the plurality of the contact plugs penetrating through each of the plurality of the oxygen diffusion prevention layers and at least a part of the insulating layer, and a plurality of resistance-variable elements, each of the plurality of the resistance-variable elements covering each of the plurality of the contact plugs exposed on surfaces of the oxygen diffusion prevention layers and being electrically connected to each of the plurality of the contact plugs Each of the oxygen diffusion prevention layers is provided only between the insulating layer and each of the plurality of the resistance-variable elements to correspond to each of the plurality of the contact plugs arranged for each of the plurality of the resistance-variable elements.

Abstract: There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the functional region.

Abstract: A thin film transistor array substrate having a pixel arrangement structure includes a first sub-pixel for displaying a first color and a second sub-pixel for displaying a second color alternately located in a first column, and a third sub-pixel for displaying a third color in a second column adjacent to the first column, and via holes of the first through third sub-pixels in a same row are at different positions.

Abstract: An array structure for light emitting diodes (LEDs) uses a patterned metal layer buried beneath LED chips to electrically interconnect non-adjacent chips in series, such that each chip in the LED array can be adjacently surrounded by LED chips of different colors. Thus, when the emission from the LED array is projected to a spot in the far field, its color uniformity over the spot is enhanced. Methods are also described for fabricating the multi-layer circuit board for such an array. Top and bottom patterned metal layers are formed, separated by a patterned insulating layer, so that electrical connections may be made between the metal layers. This provides “vias” between the metal layers for creating “cross-under” electrical connections under the second insulation layer, such that spatially-separated LED chips can be interconnected into strings, while maintaining electrical isolation between LED chips of different colors.

Abstract: The present invention relates to an electronic apparatus which contains an electronically active material and an oxygen ion pump for removing oxygen from the apparatus. Furthermore, the present invention also relates to the use of an oxygen ion pump for removing oxygen from an electronic apparatus.

Abstract: An in-cell OLED touch display panel structure with metal layer for sensing includes an upper substrate, a lower substrate parallel to the upper substrate, an OLED layer configured between the upper and lower substrates, a black matrix layer, a sensing electrode layer, and a thin film transistor layer. The black matrix layer is disposed at one surface of the upper substrate facing the OLED layer, and is composed of a plurality of opaque lines. The sensing electrode layer is disposed at one side of the black matrix layer facing the OLED layer, and is composed of a plurality of sensing conductor lines. The thin film transistor layer is disposed at one side of the lower substrate facing the OLED layer. The plurality of sensing conductor lines are disposed at positions corresponding to those of the plurality of opaque lines of the black matrix.

Abstract: An organic light emitting display device can include a substrate, two or more first electrodes positioned on the substrate and spaced apart from one another, an auxiliary electrode positioned between the first electrodes, a barrier rib positioned on the auxiliary electrode and having a reversely tapered structure including at least two layers, a bank layer exposing portions of the first electrodes to define a light emission region, an organic layer positioned in the light emission region and patterned by the barrier rib, and a second electrode positioned on the organic layer and the barrier rib and disposed to be in contact with the auxiliary electrode.

Abstract: An organic light emitting diode (OLED) display device, and a method for manufacturing the OLED display device are discussed. The OLED display device according to one embodiment includes a substrate; a first bank pattern formed on the substrate and in an emission region and a non-emission region; a second bank pattern formed on the first bank pattern; an organic emission layer formed on the substrate in the emission region; and a planarization film formed on the substrate to include an opening under the first and second bank patterns in the non-emission region. The second bank pattern is on the first bank pattern in the non-emission region, and the first bank pattern is in the opening of the planarization film in the non-emission region.

Abstract: Provided is a light-emitting module from which light with uniform brightness can be extracted. Further, provided is a beautiful light-emitting module in which Newton's rings are not observed. The light-emitting module includes a first substrate, a light-emitting element formed on one surface side of the first substrate, a second substrate, a conductive spacer maintaining the gap between the first substrate and the second substrate, and a space in which the light-emitting element is sealed between the first substrate and the second substrate. Further, the pressure in the space is lower than or equal to the atmospheric pressure. Furthermore, the conductive spacer is electrically connected to the second electrode in a position overlapping with a partition provided over the first substrate so as to reduce a voltage drop occurring in the second electrode.

Abstract: Steps for manufacturing an organic electroluminescent display device that can form an electrode pattern with high precision include forming a first insulating layer on a substrate and forming a first patterning layer, and forming a second patterning layer. The steps for manufacturing the organic electroluminescent display device further include forming a trench portion and forming an electrode layer on the second patterning layer and in the trench portion. In the step of forming the trench portion, an end of the first patterning layer exposed within the trench portion is etched to an outside more than an end of the second patterning layer exposed within the trench portion in a plan view, and in the step of forming the electrode layer, the electrode layer formed within the trench portion is isolated from the electrode layer formed outside of the trench portion.

Abstract: The present disclosure provides a double-sided display OLED array substrate, its manufacturing method, and a display device. The double-sided display OLED array substrate includes a first base substrate, a second base substrate, a first OLED and a second OLED arranged between the first base substrate and the second base substrate, and a first TFT and a second TFT sharing an identical gate electrode and arranged between the first OLED and the second OLED, the first TFT being configured to drive the first OLED, and the second TFT being configured to drive the second OLED. According to the present disclosure, it is able to reduce a thickness of the double-sided display OLED array substrate, thereby to reduce the production cost thereof.

Abstract: A display device, display panel and manufacturing method thereof, where the display panel includes an array substrate including a plurality of thin film transistors, a pixel define layer disposed on the array substrate, and an organic light-emitting structure which is surrounded by the pixel define layer and of a top emission structure. The display panel further includes: a light blocking layer disposed between the array substrate and the pixel define layer and configured to prevent light passing through the pixel define layer from irradiating on the thin film transistor. By disposing the light blocking layer between the array substrate and the pixel define layer, light passing through the pixel define layer may be prevented from irradiating on the thin film transistor in the array substrate. Therefore, leakage current generated by the thin film transistor due to optical excitation may be reduced, thereby improving stability of the thin film transistor.

Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.

Abstract: An organic electroluminescence (EL) display panel includes an anode electrode formed above a bank and formed opposite to a plurality of cathode electrodes, and a charge functional layer commonly formed for each of the organic light-emitting layers across a plurality of aperture areas formed in the bank. An end portion of the anode electrode and an end portion of the charge functional layer are provided above the bank located adjacent to a boundary between a display region and a peripheral region of a display region.