Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: A through package vias (TPV), a package including a plurality of the TPVs, and a method of forming the through package via are provided. Embodiments of a through package via (TPV) for a package include a build-up film layer, a metal pad disposed over the build-up film layer, a polymer ring disposed over the metal pad, and a solder feature electrically coupled with the metal pad.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n?1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.

Abstract: Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

Abstract: A substrate can efficiently be manufactured by separating the alignment and the actual processing when an alignment mark is provided, which is fixed with respect to the substrate and when position information on a position of a process area on the substrate is retrieved with respect to the alignment mark before the substrate is processed. During the processing alignment can then be performed by redetermining the position of the alignment mark only once and by using the stored position information on the position of the process area.

Abstract: Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device. In an embodiment, each die may include a respective assignment device to operate on an input and generate, as an output, the respective one of the sequence of the unique device ID values. Each die may also include a respective evaluation device to detect a total number of dice in the stack. Additional apparatuses and methods are described.

Abstract: An integrated device with high insulation tolerance is provided. A groove having an inclined side surface is provided between adjacent devices. When a side where an electronic circuit or MEMS device is mounted is a front surface, the groove becomes narrower from the front surface to a back surface because of the inclined surface. A mold material (insulating material) is disposed inside the groove, so that the plurality of devices are mechanically joined together, being electrically insulated from one another. A line member that establishes an electrical conduction between the adjacent devices is formed to lie along the side surface and the bottom surface of the groove. To lead the line out to the backside, the bottom surface of the groove has a hole, so that the line member is exposed to the backside from the hole.

Abstract: Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.

Abstract: Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.

Abstract: An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer.

Abstract: A semiconductor structure having a semiconductor layer having an active device therein. A dielectric structure is disposed over the semiconductor layer, such dielectric structure having open ended trench therein. An electrical interconnect level is disposed in the trench and electrically connected to the active device. A plurality of stacked metal layers is disposed in the trench. The stacked metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.

Abstract: A semiconductor packaging structure includes a chip, a metal barrier layer, a dielectric layer and two metal seed layers. The chip has a top surface, connection pads on the top surface, and a passivation layer on the top surface and partly covering the connection pads. The metal barrier layer is disposed on each of the connection pads; the dielectric layer is disposed on the passivation layer and the metal barrier layer, and has through holes to expose the metal barrier layer. The first of the metal seed layers is disposed on the dielectric layer and the exposed metal barrier layer, while the second metal seed layer is disposed on the first metal seed layer. Therefore, the metal barrier layer can effectively prevent damage to the connection pads of the chip during the manufacturing process.

Abstract: A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection.

Abstract: Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

Abstract: A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the main substrate. The semiconductor package may include an interconnection member configured to connect the semiconductor chip to the sub-substrate and including twisted wires of a plurality of strands. The semiconductor package may include a main molding member covering the main substrate and the semiconductor chip, and a sub-molding member covering the sub-substrate. The semiconductor package may include a stress buffer layer configured to fill the gap between the main substrate and the sub-substrate, and surround the interconnection member.

Abstract: A method of operating a bonding machine for bonding semiconductor elements is provided. The method includes the steps of: (a) measuring a time based z-axis height measurement characteristic of a bond head assembly during a model bonding process; (b) determining a z-axis adjustment profile for a subsequent bonding process based on the measured time based z-axis height measurement characteristic; and (c) adjusting a z-axis position of the bond head assembly with a z-axis motion system during the subsequent bonding process using the z-axis adjustment profile.

Abstract: In one embodiment, an electronic device package structure includes an electronic die having conductive pads on one surface. The one surface is further attached to at least one lead. A conductive layer covers at least one conductive pad and at least portion of the lead thereby electrically connecting the lead to the conductive pad.

Abstract: A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.

Abstract: A device comprises a top package mounted on a bottom package through a joint structure, wherein the joint structure comprises a solder ball of the top package coupled to a metal structure embedded in the bottom package and an epoxy protection layer having a first edge in direct contact with a top surface of the bottom package and a second edge surrounding a lower portion of the solder ball.

Abstract: An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode configured to extend through the substrate and have a second opening size; a switching section configured to switch between connection of the first electrode to a first power line and connection of the second electrode to the first power line; and a third electrode configured to extend through the substrate and be connected to a second power line different in potential from the first power line, a capacitance between the first and third electrodes and a capacitance between the second and third electrodes being different.

Abstract: A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower semiconductor chip mounted thereon, and a lower mold layer provided on the lower package substrate. The upper package includes an upper package substrate and an upper semiconductor chip thereon. The lower mold layer includes a guide portion extending along a vertical direction from an edge of the lower package substrate toward the upper package.

Abstract: Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Abstract: One semiconductor device includes nine surface micro-bumps laid out in a 3×3 matrix on a semiconductor substrate, a transistor that contains first and second diffusion layers formed on the semiconductor substrate, and power-supply wiring laid out on the semiconductor substrate. The aforementioned first diffusion layer is connected to one of the surface micro-bumps, the second diffusion layer is connected to the power-supply wiring, and the transistor is laid out in the region between the surface micro-bumps located on one edge in an X direction and the surface micro-bumps located on the other edge in said X direction.

Abstract: Disclosed herein is a light emitting module. The light emitting module according to an exemplary embodiment includes a circuit board having a cavity and including a circuit pattern at a region which does not have the cavity, an insulation substrate disposed in the cavity while being formed, at an upper portion thereof, with at least one pad, and at least one light emitting device disposed on the pad, wherein a joining structure is disposed between a bottom surface of the cavity and a bottom surface of the insulation substrate.

Abstract: A light emitting device includes a substrate, a light emitting element mounted on the substrate, a light transmissive member placed on an upper surface of the light emitting element, and a sealing member which seals the light emitting element and the light transmissive member. The light transmissive member is a plate-shaped member not containing a phosphor and is larger than the light emitting element when viewed from above. The sealing member includes a first sealing member which is formed of a light reflecting member for reflecting light emitted from the light emitting element and covers side surfaces of the light emitting element, and a second sealing member which contains a phosphor for converting the light emitted from the light emitting element into light having wavelength different from wavelength of the light emitted from the light emitting element and covers at least an upper surface of the light transmissive member.

Abstract: Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a thickness that is sufficiently thin to allow an optical signal to traverse through the back side layer. The optical receiver is configured to receive several optical signals through the back side layer of the first die. In some implementations, each optical signal originates from a corresponding optical emitter coupled to a second die. In some implementations, the back side layer is a die substrate. In some implementations, the optical signal traverses a substrate portion of the back side layer. The first die further includes an active layer. The optical receiver is part of the active layer. In some implementations, the semiconductor device includes a second die that includes an optical emitter. The second die coupled to the back side of the first die.

Abstract: An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.

Abstract: An electro static discharge (ESD) protection circuit including a signal transmission line coupled to an external input terminal, the ESD protection circuit including: a first power line coupled to a high voltage power supply; a second power line coupled to a low voltage power supply; a plurality of first oxide thin film transistors coupled in parallel between the first power line and the signal transmission line, the first oxide thin film transistors being diode-connected; and a plurality of second oxide thin film transistors coupled in parallel between the signal transmission line and the second power line, the second oxide thin film transistors being diode-connected.

Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.

Abstract: A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.

Abstract: A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

Abstract: An AlGaN/GaN HEMT includes a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound semiconductor stack structure; a first insulating film which is formed on the element region and is not formed on the element isolation structure; a second insulating film which is formed on at least the element isolation structure and is higher in hydrogen content than the first insulating film; and a gate electrode which is formed on the element region of the compound semiconductor stack structure via the second insulating film.

Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract: A semiconductor device includes a substrate having a well region implanted with a first dopant by a first well implantation and a non-doped section blocked from the first well implantation. The semiconductor device includes a semiconductor fin formed on the substrate, in which the semiconductor fin has a channel stop region and a channel region above the channel stop region. The channel stop region has a portion of the non-doped section and a portion of the well region. The semiconductor fin has a planar channel formed at an interface between the non-doped section and the channel region for additional current flow between source and drain regions of the semiconductor fin. The semiconductor device includes an isolation layer disposed adjacent to and in contact with the well region and the channel stop region. The semiconductor device also includes a gate structure disposed on the isolation layer and around the channel region.

Abstract: A low side control circuit and a high side control circuit are disposed in first and second n type well regions, respectively. A third n? type well region is formed around the second n type well region. The first n? type well region is formed outside the second n? type well region. A p type well region is formed around the third n? type well region. The third n? type well region and the p type well region constitute an HVJT between the first and second n type well regions. A p+ type contact region and a first electrode supplied with GND potential are formed in the p type well region. In the p type well region, an n+ type contact region and a second electrode supplied with L-VDD potential higher than the GND potential are formed between the HVJT and the p+ type contact region.

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.

Abstract: A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer, and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.

Abstract: A lay-out arrangement for LC modules in 3D semiconductor memories is described that avoids large step height. The arrangement creates insulating/conducting layer pairs with adjacent pairs differing in height by no more than the thickness of two insulating/conducting layer pairs.