Patents Issued in November 17, 2016
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Publication number: 20160336049Abstract: An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Publication number: 20160336050Abstract: A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory elements to be used as local memories (including content addressable memories or random access memories), logic elements or interconnect elements. The ability to dynamically change the function of any of these tiles allows tight integration of memory and logic tailored to particular calculation problems reducing costs in data transfer.Type: ApplicationFiled: May 11, 2015Publication date: November 17, 2016Inventor: Jing Li
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Publication number: 20160336051Abstract: A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Shuhei NAGATSUKA, Yasuyuki TAKAHASHI
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Publication number: 20160336052Abstract: A multi-port memory cell including: first and second magnetoresistive elements, each of which is programmable so as to adopt at least two resistive states, in which: the first magnetoresistive element is coupled with a first output line and is programmable by the direction of a current which is passed through same; and the second magnetoresistive element is coupled with a second output line and is arranged so as to be magnetically coupled with the first magnetoresistive element, the second magnetoresistive element being programmable by a magnetic field generated by the first magnetoresistive element.Type: ApplicationFiled: December 15, 2014Publication date: November 17, 2016Inventors: Fabrice Bernard-Granger, Virgile Javerliac
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Publication number: 20160336053Abstract: A memory apparatus and a memory device are provided. The memory apparatus includes a memory device including a plurality of memory cells and a driving circuit configured to control the memory cells; wherein each of the memory cells includes a memory layer where a magnetization direction is changeable by a current, a magnetic fixed layer having a fixed magnetization, an intermediate layer including a non-magnetic material provided between the memory layer and the magnetic fixed layer, a top electrode provided over the memory layer, a bottom electrode provided over the magnetic fixed layer; wherein the current is configured to flow in a lamination direction between the top electrode and the bottom electrode.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Yutaka HIGO, Masanori HOSOMI, Hiroyuki OHMORI, Kazuhiro BESSHO, Tetsuya ASAYAMA, Kazutaka YAMANE, Hiroyuki UCHIDA
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Publication number: 20160336054Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Stephen FELIX, Hwong-Kwo LIN, Spencer GOLD, Jing GUO, Andreas GOTTERBA, Jason GOLBUS, Karthik NATARAJAN, Jun YANG, Zhenye JIANG, Ge YANG, Lei WANG, Yong LI, Hua CHEN, Haiyan GONG, Beibei REN, Eric VOELKEL
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Publication number: 20160336055Abstract: Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.Type: ApplicationFiled: May 9, 2016Publication date: November 17, 2016Inventor: Kiyoshi KATO
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Publication number: 20160336056Abstract: A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Lawrence T. Clark, Lucian Shifren, Richard S. Roy
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Publication number: 20160336057Abstract: A novel semiconductor device, a semiconductor device capable of storing multi-level data, a semiconductor device with low power consumption, a semiconductor device with a reduced area, or a highly reliable semiconductor device is provided. The semiconductor device includes a memory cell which includes a first transistor and a capacitor, and a second transistor. The first transistor includes an oxide semiconductor in a channel formation region. One of a source and a drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. The other of the electrodes of the capacitor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Inventors: Tatsuya ONUKI, Yutaka SHIONOIRI
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Publication number: 20160336058Abstract: A semiconductor device includes: a command decoding unit suitable for decoding external command signals to generate an internal command signal; and a pulse control unit suitable for controlling a pulse width of the internal command signal.Type: ApplicationFiled: September 23, 2015Publication date: November 17, 2016Inventor: Choung-Ki SONG
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Publication number: 20160336059Abstract: Provided is an electronic device including a circuit for reading data from a memory cell that can store multilevel data. The electronic device includes a memory cell array region, N sense amplifier regions, and switching elements. The memory cell array region includes memory cells that store, when (N+1)-level data is stored, the (N+1)-level data as different potentials. Each of the N sense amplifier regions compares a read potential, which depends on a charge released to a bit line and a wiring or the like connected thereto, with a reference potential and performs amplification. Each of the switching elements electrically isolates a sense amplifier region from the other sense amplifier regions after all of the N sense amplifier regions are electrically connected to the bit line. Each of the sense amplifier regions can output a write potential to the bit line.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Inventor: Takanori MATSUZAKI
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Publication number: 20160336060Abstract: A memory device includes a buffer memory configured to receive commands from a memory controller via first to Nth channels, wherein N denotes an integer which is equal to or greater than ‘2’; and first to Nth core memories each connected to the buffer memory via one of the first to Nth channels. The buffer memory may deconcentrate refresh commands corresponding to the first to Nth core memories, based on a number of commands input during a specific time.Type: ApplicationFiled: May 9, 2016Publication date: November 17, 2016Inventor: DONG HAK SHIN
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Publication number: 20160336061Abstract: A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation and changed when all the memory blocks are refreshed; a target address generator suitable for generating a target address used for a target refresh operation, wherein the target address corresponds to an address of a word line to be additionally refreshed in the memory blocks; and a refresh controller suitable for controlling the memory blocks to be refreshed at different times during a first normal refresh operation, controlling a memory block among the memory blocks, which is first refreshed in the first normal refresh operation, to be refreshed through the target refresh operation, and controlling the memory block, which is first refreshed in the first normal refresh operation, to be refreshed last during a second normal refresh operation, based on the refresh command.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventor: Yu-Ri LIM
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Publication number: 20160336062Abstract: A technique includes reading a row of memory cells of a memory cell array, where each of the memory cells includes comprising a resistive storage element and is associated with a column line. The technique includes, in association with the reading, coupling the column lines to a ground connection.Type: ApplicationFiled: January 31, 2014Publication date: November 17, 2016Inventor: Brent E. BUCHANAN
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Publication number: 20160336063Abstract: An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.Type: ApplicationFiled: January 31, 2014Publication date: November 17, 2016Inventors: Brent E. BUCHANAN, Martin FOLTIN, Jeffrey A. LUCAS, Clinton H. PARKER
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Publication number: 20160336064Abstract: Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.Type: ApplicationFiled: May 16, 2016Publication date: November 17, 2016Applicant: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Jae-sun Seo, Shimeng Yu, Yu Cao, Sarma Vrudhula
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Publication number: 20160336065Abstract: A method for switching a memory resistance, including: changing a memory resistance of an oxide thin film of a semiconductor device by irradiating a near-infrared laser beam onto the oxide thin film, the semiconductor device having the oxide thin film formed on a substrate and two terminals formed at both ends of the oxide thin film.Type: ApplicationFiled: July 17, 2015Publication date: November 17, 2016Inventors: Yongwook Lee, Jihoon Kim
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Publication number: 20160336066Abstract: Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program operation and a verify operation, and subsequent cycles. The initial cycle includes an initial instance of the program operation to establish a cell resistance of the programmable element, and an initial instance of the verify operation to determine whether the cell resistance of the memory cell is within the target resistance range. At least one of the subsequent cycles includes an additional pulse having a second polarity to the programmable element, and a subsequent instance of the verify operation. The first polarity of the initial program pulse and the second polarity of the additional pulse have opposite polarities. A subsequent instance of the program operation includes applying a subsequent program pulse having the first polarity to the programmable element.Type: ApplicationFiled: October 7, 2015Publication date: November 17, 2016Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: YU-YU LIN, FENG-MIN LEE
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Publication number: 20160336067Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.Type: ApplicationFiled: March 14, 2016Publication date: November 17, 2016Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
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Publication number: 20160336068Abstract: A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Shunpei YAMAZAKI, Jun KOYAMA
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Publication number: 20160336069Abstract: MLVM is a DRAM product that has the flexibility for certain performance characteristics to change based on programming characteristics made when writing the data and the ability to write multiple bits of data at the same time. At the simplest level, this means that depending on the type of operation(s) being executed, certain more favorable characteristics can be programmed into the DRAM to get benefits over the current state of the art. The most likely benefits would be in power utilization and heat.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Inventor: James Lin
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Publication number: 20160336070Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.Type: ApplicationFiled: December 28, 2015Publication date: November 17, 2016Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
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Publication number: 20160336071Abstract: A method of operating a semiconductor memory device including a plurality of cell strings coupled to dummy word lines and normal word lines includes performing a first sub-program operation on selected normal memory cells by sequentially applying first program pulses to a selected normal word line and performing a second sub-program operation on the selected normal memory cells by sequentially applying second program pulses greater than the first program pulses to the selected normal word line, wherein at least one of the dummy word lines is biased in a same manner as the selected normal word line whenever each of the first program pulses is applied to the selected normal word line.Type: ApplicationFiled: January 5, 2016Publication date: November 17, 2016Inventors: Kyoung Jin PARK, Sung Ho BAE, Byeong Il HAN
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Publication number: 20160336072Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.Type: ApplicationFiled: March 30, 2016Publication date: November 17, 2016Inventors: Xiaozhou Qian, Viktor Markov, Jong-Won Yoo, Xiao Yan Pi, Alexander Kotov
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Publication number: 20160336073Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verifyType: ApplicationFiled: February 23, 2016Publication date: November 17, 2016Applicant: Intel CorporationInventors: Krishna K. Parat, Pranav Kalavade, Koichi Kawai, Akira Goda
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Publication number: 20160336074Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: August 1, 2016Publication date: November 17, 2016Inventors: Toshihiro TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takashi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
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Publication number: 20160336075Abstract: A nonvolatile memory device includes a memory cell array and a voltage generator. The memory cell array includes a plurality of planes, and each plane receives one of a first ground selection voltage and a second ground selection voltage. The voltage generator is configured to provide selectively one of the first ground selection voltage and the second ground selection voltage independently to each of the planes based on a result of an erase verification operation on each of the plurality of planes.Type: ApplicationFiled: April 8, 2016Publication date: November 17, 2016Inventor: Chang-Hyun LEE
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Publication number: 20160336076Abstract: A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a first bit value (for example, bit value 1.) If the bitline voltage stays below a low threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a second bit value (for example, bit value 0).Type: ApplicationFiled: July 17, 2015Publication date: November 17, 2016Inventors: Sachin Taneja, Vaibhav Verma, Pritender Singh, Sanjeev Kumar Jain
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Publication number: 20160336077Abstract: A semiconductor system includes a controller configured to generate a boot-up signal; and a semiconductor device configured to, if addresses, which increase by a predetermined value, have the same combination of bits as fuse data, initialize fuse data in response to the boot-up signal or a reset signal, and generate the fuse data by using latched internal fuse data after the fuse data are initialized.Type: ApplicationFiled: July 24, 2015Publication date: November 17, 2016Inventor: Young Kyu NOH
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Publication number: 20160336078Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Inventors: Eyal Gurgi, Yoav Kasorla, Barak Rotbard, Shai Ojalvo
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Publication number: 20160336079Abstract: A fusion reactor includes a columnating panel disposed between the positive electrode and negative electrode for channeling deuterium ions along predetermined paths that are likely to lead to fusion-producing collisions with previous deuterium ions. Deuterium ions are introduced to the reactor adjacent to the positive electrode, and then pass from the columnating panel, through a reduced pressure chamber, and then proceed towards the negative electrode. Once the deuterium ions strike the negative electrode, they remain attached to the negative electrode so that subsequent deuterium ions following the same channels through the columnating panel are more likely to collide with them.Type: ApplicationFiled: December 28, 2015Publication date: November 17, 2016Inventor: Jonathan Mohler
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Publication number: 20160336080Abstract: A bottom nozzle includes a skirt, support blocks, transverse blades and longitudinal blades. The skirt is a hollow structure and a bottom thereof is provided with corner legs which are protruded downwards, a cavity is defined in the hollow structure, the transverse blades are configured in the cavity, the longitudinal blades are configured in the cavity, the transverse blades and longitudinal blades are firmly connected with the skirt, projections of the transverse blades and the longitudinal blades in a level plane are intersectant to form interleaved grids, and the support blocks run through and are fixed on the transverse blades and the longitudinal blades. In such a way, the bottom nozzle forms a three-dimensional gridded water passage, thereby improving the filter capacity and generating small water pressure drop.Type: ApplicationFiled: December 20, 2013Publication date: November 17, 2016Inventors: Wenchi Yu, Weical Li, Haixiang Hu, Jiayuan Wang
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Publication number: 20160336081Abstract: An embodiment of an operating floor confinement has: an operating floor, a sidewall that surrounds the operating floor, a ceiling that is provided on an upper portion of the sidewall, a reactor well, a fuel pool, a dryer and separator pit, an equipment hatch that is provided on the sidewall, an air lock that is provided on the sidewall, and an isolation valve that is provided in a penetration. The operating floor confinement forms a pressure boundary having pressure resistance and a leakage protection function, is in contact with the containment vessel via a containment vessel head and separated from an equipment area of the reactor building, and has no blowout panel.Type: ApplicationFiled: April 25, 2016Publication date: November 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takashi SATO, Keiji MATSUMOTO, Keisuke TAGUCHI
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Publication number: 20160336082Abstract: Steam generators are in the form of tubular heat exchangers in which molten lead coolant flows within the pipes, while the water-steam flows in a space between the pipes, the steam generators are arranged in separate boxes and communicate with the reactor cavity by means of circulation conduits for raising and discharging the lead coolant, the steam generators and most of the circulation conduits and are arranged higher than the level of the lead coolant within the reactor cavity, and the circulation pumps are arranged within the reactor cavity on the circulation conduits and for raising the “hot” lead coolant, and a technical means is provided for ensuring natural circulation of the lead coolant through the reactor core when the circulation pumps are switched off. The specific volume of lead coolant per unit of power of the reactor is reduced and the safety of the reactor is increased.Type: ApplicationFiled: November 27, 2014Publication date: November 17, 2016Applicant: STATE ATOMIC ENERGY CORPORATION "ROSATOM" ON BEHALF OF THE RUSSIAN FEDERATIONInventors: Boris Borisovich KUBINTSEV, Viktor Nikolaevich LEONOV, Aleksandr Viktorovich LOPATKIN, Yuriy Vasilievich CHERNOBROVKIN
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Publication number: 20160336083Abstract: A remote heat removal system that pumps a secondary fluid from a remote reservoir through a secondary side of a heat exchanger in heat exchange relationship with a primary fluid to be cooled. The secondary fluid drives a motive device that drives the primary fluid through the primary side of the heat exchanger.Type: ApplicationFiled: February 26, 2016Publication date: November 17, 2016Applicant: Westinghouse Electric Company LLCInventors: Francis P. Ferraraccio, Nirmal K. Jain, Martin L. Van Haltern, Daniel C. Flahive
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Publication number: 20160336084Abstract: Nuclear reactor vessel segmenting utilizing improved arc saw systems and methods.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Inventors: Thomas S. LaGuardia, Richard Simoneau
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Publication number: 20160336085Abstract: The present invention relates to a radiation protection arrangement, in particular for attachment to a support rail, which is attached to a side of a treatment table, comprising: a holder on which a radiation protection drape is arranged, wherein the holder is attachable to the support rail and comprises a fastening means with which the holder can be fastened to the support rail. The fastening means is formed on a side of the holder and comprises at least one first bracket part and at least one second bracket part. The first and the second bracket parts each have an L-shaped profile with a first leg and a second leg, wherein the first and the second bracket parts are arranged such that the first legs are aligned in parallel and the second legs face each other. The first bracket part is arranged at an upper edge of the holder and the second bracket part is arranged at the lower edge of the holder.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Applicant: MAVIG GMBHInventor: Markus BUCHMEYER
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Publication number: 20160336086Abstract: A copper alloy wire can be used as a conductor. The copper alloy wire is made of a copper alloy containing: not less than 0.4 mass % and not more than 1.5 mass % of Fe; not less than 0.1 mass % and not more than 0.7 mass % of Ti; not less than 0.02 mass % and not more than 0.15 mass % of Mg; not less than 10 mass ppm and not more than 500 mass ppm in total of C and at least one of Si and Mn; and the balance of Cu and impurities. The copper alloy wire has a wire diameter of not more than 0.5 mm. Preferably, a mass ratio Fe/Ti in the copper alloy is not less than 1.0 and not more than 5.5.Type: ApplicationFiled: August 3, 2015Publication date: November 17, 2016Inventors: Akiko Inoue, Tetsuya Kuwabara, Taichiro Nishikawa, Kiyotaka Utsunomiya, Hiroshi Fujita, Yasuyuki Ootsuka, Hiroyuki Kobayashi
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Publication number: 20160336087Abstract: Methods of preparing a dispersion of colloidal nanocrystals (NCs) for use as NC thin films are disclosed. A dispersion of NCs capped with ligands may be mixed with a solution containing chalcogenocyanate (xCN)-based ligands. The mixture may be separated into a supernatant and a flocculate. The flocculate may be dispersed with a solvent to form a subsequent dispersion of NCs capped with xCN-based ligands.Type: ApplicationFiled: May 10, 2016Publication date: November 17, 2016Inventors: Cherie R. Kagan, AARON T. FAFARMAN, JI-HYUK CHOI, WEON-KYU KOH, DAVID K. KIM, SOONG JU OH, YUMING LAI, SUNG-HOON HONG, SANGAMESHWAR RAO SAUDARI, CHRISTOPHER B. MURRAY
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Publication number: 20160336088Abstract: The present invention is directed to methods of transferring urea from an aqueous solution comprising urea to a MXene composition, the method comprising contacting the aqueous solution comprising urea with the MXene composition for a time sufficient to form an intercalated MXene composition comprising urea.Type: ApplicationFiled: July 8, 2016Publication date: November 17, 2016Inventors: MICHEL W. BARSOUM, YURY GOGOTSI, MICHAEL NAGUIB ABDELMALAK, OLHA MASHTALIR
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Publication number: 20160336089Abstract: Disclosed are a carbon fiber composite having high conductivity and a method for preparing the same. The carbon fiber composite may comprise a carbon fiber reinforcement material that includes a carbon fiber and a conductive metal-plated carbon fiber, such that the carbon fiber composite may be used when lightning occurs due to its high conductivity. Further, the carbon fiber composite may also achieve lightweight by using the carbon fiber.Type: ApplicationFiled: December 28, 2015Publication date: November 17, 2016Inventors: Young Ho Choi, Seok Hwan Kim
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Publication number: 20160336090Abstract: A high-voltage alternate current (HVAC) electric cable for power transmission or distribution in under-ground power lines has a reduced capacitance obtained by reducing the density of the insulating layer.Type: ApplicationFiled: January 21, 2014Publication date: November 17, 2016Applicant: PRYSMIAN S.P.A.Inventors: Gabriele PEREGO, Roberto CANDELA, Donald PARRIS
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Publication number: 20160336091Abstract: Aspects of the subject disclosure may include, for example, a transmission medium for propagating electromagnetic waves. The transmission medium can include a conductor for guiding electromagnetic waves longitudinally along the conductor, and a shell surrounding at least a portion of the conductor for reducing exposure of the electromagnetic waves to an adverse environment that increases propagation losses of the electromagnetic waves. Other embodiments are disclosed.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Paul Shala Henry, Robert Bennett, Farhad Barzegar, Irwin Gerszberg, William Scott Taylor, Donald J. Barnickel, Thomas M. Willis, III, Ed Guntin
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Publication number: 20160336092Abstract: Aspects of the subject disclosure may include, for example, a transmission medium for propagating electromagnetic waves. The transmission medium can include a conductor for guiding electromagnetic waves longitudinally along the conductor, and a shell surrounding at least a portion of the conductor for reducing exposure of the electromagnetic waves to an adverse environment that increases propagation losses of the electromagnetic waves. Other embodiments are disclosed.Type: ApplicationFiled: July 23, 2015Publication date: November 17, 2016Inventors: PAUL SHALA HENRY, ROBERT BENNETT, FARHAD BARZEGAR, IRWIN GERSZBERG, WILLIAM SCOTT TAYLOR, DONALD J. BARNICKEL, THOMAS M. WILLIS, III, ED GUNTIN
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Publication number: 20160336093Abstract: Disclosed is an elastic electric contact terminal including an elastic core provided with at least one or more channels which are recessed downwardly from the top surface thereof with a predetermined width and depth and extend in a lengthwise direction, a polymer film surrounding and adhering to the elastic core, and a solderable metal layer surrounding and adhering to the polymer film, wherein both side walls of the channels elastically support an object.Type: ApplicationFiled: February 5, 2016Publication date: November 17, 2016Applicants: JOINSET CO., LTD.Inventor: Sun-Ki KIM
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Publication number: 20160336094Abstract: A shielded electric wire includes an electric wire; a shielding member that forms a shielding layer by covering a periphery of the electric wire; a sheet-shaped member that covers a periphery of the shielding member; and a protective member spirally wound on a periphery of the sheet-shaped member. The sheet-shaped member includes a first sheet material and a second sheet material. One surface of the first and second sheet materials is formed with an adhesive layer. The first and second sheet materials have a width longer than a half circumferential distance of the shielding member provided on the periphery of the electric wire, and are stuck on the shielding member to sandwich the shielding member. The adhesive layers of the first and second sheet materials are opposingly stuck in extra length portions protruding the shielding member in a width direction.Type: ApplicationFiled: April 13, 2016Publication date: November 17, 2016Applicant: YAZAKI CORPORATIONInventors: Takeyuki OMURA, Hidenobu OKA
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Publication number: 20160336095Abstract: A cable arrangement of at least two cables which extend adjacently in a substantially parallel manner, a first cable and a second cable of which each having at least one stranding group which has two or more conductors that are twisted together. The length of lay of each of the stranding groups varies in the longitudinal direction of the individual cables. In addition, the length of lay of a stranding group winding of the stranding group of the first cable is smaller than the length of lay of a most directly adjacent stranding group winding of the stranding group of the second cable.Type: ApplicationFiled: December 16, 2014Publication date: November 17, 2016Inventors: Gunnar Armbrecht, Thomas Müller, Stephan Kunz
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Publication number: 20160336096Abstract: The present invention relates to a superconducting power system which is capable of effectively absorbing an axial force caused by the contraction of a superconducting cable when the superconducting cable is cooled and in which the superconducting cable is installed in the form of minimizing unnecessary waste of an installation space, and a method of installing a superconducting cable.Type: ApplicationFiled: March 30, 2015Publication date: November 17, 2016Applicant: LS CABLE & SYSTEM LTD.Inventors: Young Seok LIM, Yong Hee WON, Young Il CHO, Chang Youl CHOI
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Publication number: 20160336097Abstract: An electric wire protection member that prevents a connector or a terminal portion from coming into contact with water due to water intruding into a grommet. The electrical wire protection member disclosed by this specification includes a tube-shaped corrugated tube that protects electrical wires; a tube-shaped grommet that has a connection tube portion for connection to an opening end portion of the corrugated tube, and protects the electrical wires in place of the corrugated tube; a tube-shaped holder that has a mating tube portion that is fitted into the connection tube portion of the grommet, and abuts against the opening end portion of the corrugated tube; and a rubber stopper that has electrical wire sealing holes into which the electrical wires are inserted in a sealed state, and that comes into close contact with the inner peripheral surface of the holder.Type: ApplicationFiled: April 21, 2016Publication date: November 17, 2016Inventors: Noriyuki SAKAGAMI, Hirokazu NAKAI
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Publication number: 20160336098Abstract: The electrical resistance (10) includes a sealed housing (12) with a generally cylindrical shape defined along a longitudinal axis (X), a resistive element (16), extending along a spiral defined around the longitudinal axis (X), and a fluid guiding element (18), defining, with the sealed housing (12), a conduit for guiding a flow of fluid in contact with the resistive element (16). The guiding element (18) has a spiral shape defined around the longitudinal axis (X).Type: ApplicationFiled: January 13, 2015Publication date: November 17, 2016Inventor: Pierre KARCIAUSKAS