Abstract: The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures.

Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.

Abstract: Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism.

Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

Abstract: A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate. The insulated substrate comprising a silicon substrate, and an insulator layer deposited on the silicon substrate. The one or more fins in the first region comprising a first material layer deposited on the insulator layer. The one or more fins in the second region comprising a second material layer deposited on the insulator layer.

Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.

Abstract: A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.

Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

Abstract: A tungsten film forming method includes: supplying a tungsten chloride gas as a source material of tungsten and a reducing gas towards a substrate to be processed under a depressurized atmosphere to cause reaction between the tungsten chloride gas and the reducing gas while heating the substrate to be processed, such that a main tungsten film is directly formed on a surface of the substrate to be processed without forming an initial tungsten film for nucleus generation.

Abstract: Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

Abstract: A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.

Abstract: A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

Abstract: A wafer is formed with a plurality of division lines on a front surface of a single crystal substrate having an off angle and formed with devices in a plurality of regions partitioned by the division lines. The wafer is processed by setting a numerical aperture (NA) of a focusing lens for focusing a pulsed laser beam so that a value obtained by dividing the numerical aperture (NA) by a refractive index (N) of the single crystal substrate falls within the range from 0.05 to 0.2. The pulsed laser beam is applied along the division lines, with a focal point of the pulsed laser beam positioned at a desired position from a back surface of the single crystal substrate, so as to form shield tunnels each composed of a pore and a pore-shielding amorphous portion along the division lines from the focal point positioned inside the single crystal substrate.

Abstract: Disclosed herein is a wafer processing method for dividing a wafer into a plurality of individual devices along a plurality of crossing division lines. The wafer is composed of a substrate and a functional layer formed on the front side of the substrate. The division lines are formed on the front side of the functional layer. A laser beam having a transmission wavelength to the substrate is applied to the wafer from the back side thereof to detect the height of an interface between the functional layer and the substrate in an area corresponding to each division line. The depth of cut by a cutting blade for cutting the substrate is next set according to the height detected above.

Abstract: A complementary bipolar junction transistor (BJT) integrated structure and methods for fabricating and operating such. The structure includes a monolithic substrate and conductive first and second backplates electrically isolated from each other. An NPN lateral BJT is superposed over the first backplate, and a PNP lateral BJT is superposed over the second backplate. A buried oxide (BOX) layer is positioned between the NPN lateral BJT and the first backplate, and between the PNP lateral BJT and the second backplate.

Abstract: A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

Abstract: A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the source region by a first spacing. The semiconductor device also comprises a first heat conductive layer formed over couples the source region and the guard ring. The semiconductor device further comprises a first via over a first portion of the first heat conductive layer. The semiconductor device additionally comprises a second via separate from the first via over a second portion of the first conductive layer. The semiconductor device also comprises a second heat conductive layer over and coupling the first via and the second via. In use, the semiconductor device generates heat, and the heat dissipates, at least partially, from the source region through the first heat conductive layer to the guard ring and the substrate.

Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.

Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.

Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed.

Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

Abstract: A method of forming a multiple threshold voltage p-channel silicon germanium trigate device using (3D) condensation. The method may include forming a first and second fin in a single semiconductor layer, where the first and second fin have similar initial widths; thinning the second fin; performing a (3D) condensation process to condense the germanium within the first and second fin; and thinning the first fin to a similar width as the second fin.

Abstract: Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one or more manufacturing lines. The products include product macros placed on a chip. The method also includes establishing allowed parametric match from line to line. The method further includes determining that products from the one or more manufacturing lines meet the allowed parametric match.

Abstract: A substrate treatment apparatus includes a processing chamber configured to be capable of storing a substrate; a substrate holder disposed in the processing chamber and configured to be capable of holding the substrate; a sublimation removing unit configured to remove, by sublimation, a sublimating material filled between structures formed on a surface of a substrate held by the substrate holder, and a sublimation status detecting unit configured to detect a progress or an end point of sublimation removal of the sublimating material.

Abstract: The invention discloses a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a recess is formed in the device carrier and a conductive element is disposed on the substrate, wherein the substrate is disposed on the device carrier and the conductive element is located in the recess of the device carrier. The conductive pattern in the substrate is electrically connected to the device carrier and I/O terminals of the first conductive element. The invention also discloses a method for manufacturing a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a portion of the conductive pattern in the substrate can be modified.

Abstract: The present invention relates to a hot-meltable curable silicone composition for compression molding or laminating and a laminate provided with at least one layer comprising the composition, as well as a semiconductor device using these and a method of manufacturing the same. In accordance with the present invention, it is possible to efficiently manufacture a semiconductor device provided with a hemi-spheroidal lens- or dome-shaped seal. In the present invention, it is easy to control the shape of the seal, and the seal does not contain any bubbles. In the present invention, it is also easy to control the thickness of the coating layer of the semiconductor device apart from the seal.

Abstract: In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package.

Abstract: An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.

Abstract: A semiconductor device includes a semiconductor chip, a resin mold portion sealing a component in which the semiconductor chip is included, and a bonding layer disposed between the resin mold portion and the component. The bonding layer is made of an organic resin that is disposed at an obverse side of the component, and includes a first layer bonded to the component and a second layer bonded to the resin mold portion. A loss coefficient tan ? of the first layer is smaller than a loss coefficient tan ? of the second layer within a temperature range of 200° C. to 250° C.

Abstract: An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

Abstract: Provided is a method of manufacturing a heat conductive sheet that itself is imparted with stickiness and has reduced heat resistance due to improved adhesion to a heat generator and a heat dissipater and that may be fixed provisionally without the need for using an adhesive agent or the like. The method includes the steps of molding a heat conductive resin composition, which includes heat conductive fillers and a binder resin, into a predetermined shape and curing the heat conductive resin composition to obtain a molded product of the heat conductive resin composition, cutting the molded product into sheets to obtain a molded product sheet, and coating an entire surface of a sheet main body (7) with an uncured component (8) of the binder resin oozing from the sheet main body (7).

Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.

Abstract: The invention relates to a micro cooling element (1) with a mounting surface (2) for a component to be cooled, in particular a semiconductor component, which has within it a micro cooling structure (3) which is connected by connection channels (4) to at least one inflow opening (4a) and at least one outflow opening (4b) by means of which a cooling medium can be supplied to the micro cooling structure (3) or be discharged from the latter, and which is characterized in that it is formed from at least two different powdery and/or liquid, in particular metallic and/or ceramic, materials or material mixtures (10) while maintaining a monolithic structure, wherein regions of different stresses (I, II) of the micro cooling element (1) are built by a powdery and/or liquid, in particular metallic and/or ceramic materials or material mixtures (10) being adapted to the stress respectively. The invention further relates to an apparatus and a process for producing a micro cooling element according to the invention.

Abstract: A stack package may include a first chip, a second chip, a through silicon via (TSV) and an interface circuit unit. The first chip may include a first internal circuit unit driven by an internal voltage. The second chip may be stacked over the first chip. The second chip may include a second internal circuit unit driven by the internal voltage. The TSV may be electrically coupled between the first chip and the second chip. The interface circuit unit may be arranged in the first chip and the second chip. The interface circuit unit may be coupled to the TSV. A portion of the interface circuit unit may be received a variable voltage different from the internal voltage as a driving voltage.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.

Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.

Abstract: A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Abstract: A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

Abstract: A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group.

Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.

Abstract: A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is disposed within the through holes A plurality of discrete contact members are located in the plurality of the through holes, within the conductive structure. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. The conductive structure can be electrically coupled to circuit geometry. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to desired circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

Abstract: An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric connection structure mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment, and a mounting provision configured for mounting the electronic device at a periphery device.

Abstract: Disclosed are a foldable and spreadable electronic device and a method of manufacturing the electronic device. The electronic device may include a flexible chip, a protection film and a flexible substrate. The flexible chip may include a first wiring on a first face thereof. The flexible chip may have a foldable and spreadable structure by reducing a thickness from a second face thereof. The protection film may be disposed on the second face of the flexible chip for protecting the flexible chip. The flexible substrate may include a second wiring on one face thereof. The protection film on disposed on the second face of the flexible chip may make contact with the flexible substrate. The first wiring of the flexible chip may be electrically connected to the second wiring of the flexible substrate using a wire.

Abstract: A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.

Abstract: Provided are a transparent substrate having a nano pattern, and a method of manufacturing the same, which enables the nano pattern to be easily formed on the transparent substrate and has the nano pattern applicable to a large sized substrate by forming a resin layer made of transparent material on a transparent substrate; forming at least one or more unit pattern parts composed of a first pattern area and a second pattern area in which a plurality of grid patterns are formed, and a protrusion pattern formed between the first pattern area and the second pattern area, on the resin layer; and forming a nanoscale metal layer on the protrusion pattern.

Abstract: An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling capacitor mounted on the substrate, and a second decoupling capacitor formed in the integrated circuit. The package is formed by coupling a power supply pin to both the first and second capacitors by a low frequency path and a DC path, respectively, and the first and second capacitors are coupled by a high frequency path.