Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate comprises a gate layer, a gate insulating layer, an active layer, a source and drain layer, a scanning line and a signal line formed on a substrate, the signal line is provided in a same layer as the gate layer, the scanning line is provided in a same layer as the source and drain layer, the gate insulating layer is provided between the gate layer, the signal line and the active layer. The array substrate further comprises a first through hole and a second through hole penetrating through the gate insulating layer, the signal line is connected to the source and drain layer via the first through hole, and the scanning line is connected to the gate layer via the second through hole.

Abstract: A manufacturing method of an array substrate is disclosed. The manufacturing method includes a step of forming a pattern including a pixel electrode; and the manufacturing method further includes a step of forming a pattern including an active layer after the step of forming the pattern including the pixel electrode. Accordingly, an array substrate and a display device are also disclosed. In the manufacturing process of the array substrate, conductive material remained on the active layer is less, thereby producing less leak current, which in turn improves quality of the array substrate and display performance of the display device.

Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

Abstract: A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode.

Abstract: An array substrate includes a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer. In addition, the wiring patterns are separated from each other, and extend toward a side of the substrate. The array substrate further includes a recess pattern disposed adjacent the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of a top surface of the substrate, and an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.

Abstract: Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid crystal display (LCD) and organic light-emitting diode (OLED) displays.

Abstract: The present invention provides an array substrate, a method for manufacturing the same, and a display device including the same. In the manufacturing method of the present invention, photoresist is exposed and developed by using a mask to allow the first regions to retain photoresist with a first thickness and second regions to retain photoresist with a second thickness, wherein the first thickness is greater than the second thickness, and each of the first regions is at least partially connected with the second region, so that the contact area between the exposed photoresist and the substrate is large and the photoresist in the first regions is unlikely to peel off. The manufacturing method of the present invention is applicable to manufacturing various array substrates.

Abstract: An image sensor includes a first conductivity type first impurity region surrounded by a pixel isolation layer surrounds; a first conversion device isolation layer intersecting the first impurity region in a first direction; a second conductivity type second impurity region disposed on a first side surface of the first conversion device isolation layer; a second conductivity type third impurity region disposed on a second side surface of the first conversion device isolation layer opposite the first side surface; and a second conversion device isolation layer intersecting the first impurity region in a second direction perpendicular to the first direction. The second impurity region and the third impurity region are disposed inside the first impurity region.

Abstract: The present invention provides an invisible light flat plate detector and a manufacturing method thereof, an imaging apparatus, relates to the field of detection technology, can solve problems that the structure of the invisible light flat plate detector in the prior art is complex and the manufacturing method thereof is tedious. The invisible light flat plate detector of the present invention comprises a plurality of detection units and an invisible light conversion layer provided above the detection units for converting invisible light into visible light, each of the detection units comprising a thin film transistor provided on a substrate, and a first insulation layer, a first electrode, a semiconductor photoelectronic conversion module, a second electrode which are successively provided above the thin film transistor and of which projections on the substrate at least partially overlap with a projection of the thin film transistor on the substrate.

Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

Abstract: Optical modules are made using customizable spacers to reduce variations in the focal lengths of the optical channels, to reduce the occurrence of tilt of the optical channels, and/or prevent adhesive from migrating to active portions of an image sensor.

Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.

Abstract: A front-side illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode, transistor gate structures, shallow trench isolation structures, and other associated pixel circuits formed in a semiconductor substrate. Buried light shielding structures that are opaque to light may be formed over regions of the substrate to prevent the transistor gate structures, shallow trench isolation structures, and the other associated pixel circuits from being exposed to stray light. Buried light shielding structures formed in this way can help reduce optical pixel crosstalk.

Abstract: Provided are an infrared sensor, a near-infrared absorbing composition, a cured film, a near-infrared absorbing filter, an image sensor, a camera module, and a compound. An infrared sensor 100 which has an infrared transmitting filter 113 and a near-infrared absorbing filter 111 and detects objects by detecting light having wavelengths of 700 nm or longer and shorter than 900 nm, in which the near-infrared absorbing filter 111 includes a near-infrared absorbing substance having a maximum absorption wavelength at a wavelength of 700 nm or longer and shorter than 900 nm.

Abstract: There is provided a solid state imaging apparatus, including: an optical film layer on which a solid state image sensor is mounted; a multifunctional chip laminated at a periphery of the solid state image sensor in the optical film layer being electrically contacted with the optical film layer via a metal body; a sealing resin layer for sealing the periphery where the multifunctional chip is laminated on the optical film layer; and a concave structure for blocking a flow of the sealing resin in a liquid state when the sealing resin layer is formed at the periphery of the sealing resin layer. Also, a method of producing the solid state imaging apparatus is also provided.

Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate.

Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.

Abstract: The present application relates to a photodetector based on interband transition in quantum wells. The photodetector may include a first semiconductor layer having a first conduction type; a second semiconductor layer having a second conduction type different from the first conduction type; and a photon absorption layer arranged between the first semiconductor layer and the second semiconductor layer, the photon absorption layer including at least one quantum well layer and barrier layers arranged on both sides of each quantum well layer. The present application utilizes the modulating effect of a semiconductor PN junction on a photoelectric conversion process associated with quantum wells to significantly increase a current output of the photodetector based on the quantum well material.

Abstract: There is disclosed a substrate including at least one photodetector, the photodetector having a first active area on a first surface of the substrate and a second active area on a second surface of the substrate, wherein the photodetector is provided with a conductive via electrically isolated from the substrate, said conductive via extending through the photodetector from the first surface of the substrate to the second surface of the substrate for connecting the first active area to the second surface of the substrate, the second surface providing electrical connections for the first and second active areas of the photodetector.

Abstract: A method of manufacturing an image senor includes: preparing a sensor substrate including: a sensor layer including a photosensitive cell; and a signal line layer including lines to receive electric signals from the photosensitive cell; forming a first material layer having a first refractive index on the sensor substrate; and forming a nanopattern layer on the first material layer, the nanopattern layer including a material having a second refractive index different from the first refractive index.

Abstract: A method for manufacturing a BSI image sensor includes following steps: A substrate is provided. The substrate includes a front side and a back side opposite to the front side. The substrate further includes a plurality of isolation structures and a plurality of sensing elements formed therein. Next, the isolation structures are exposed from the back side of the substrate. Subsequently, a thermal treatment is performed to the back side of the substrate to form a plurality of cambered surfaces on the back side of the substrate. The cambered surfaces are formed correspondingly to the sensing elements, respectively.

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including an isolation region and a device region is provided. An overall amorphization process is performed on the substrate to form an amorphous region. Here, a minimum depth of the amorphous region is greater than a maximum depth of at least one of the isolation region and the device region, and the amorphous region covers at least one of the isolation region and the device region. A thermal treatment is performed on the amorphous region.

Abstract: A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

Abstract: A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refraction index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the interlayer film, and a layer which is provided in between the photoreceiving portion and the large refraction index region, and has a lower etching rate than the interlayer film, wherein the layer of the lower etching rate is formed so as to cover at least the whole surface of the photoreceiving portion. In addition, the layer of the lower etching rate has a refractive index in between the refractive indices of the large refraction index region and the substrate. Such a configuration can provide the photoelectric conversion device which inhibits the lowering of the sensitivity and the variation of the sensitivity among picture elements.

Abstract: Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.

Abstract: An organic EL device according to the present application includes a substrate, a plurality of organic EL elements arranged on the substrate, the plurality of organic EL elements including an organic light-emitting layer interposed between an anode and a cathode, a plurality of connection terminals disposed on the substrate, a sealing layer covering the plurality of organic EL elements such that the plurality of organic EL elements lie between the substrate and the sealing layer, and an organic layer formed above the sealing layer. The organic layer and the sealing layer have an opening portion that exposes at least one of the plurality of connection terminals.

Abstract: The present invention relates to an OLED display panel including: two substrates opposite to each other; a plurality of pixel regions disposed between inner sides of the two substrates and each comprising a blue sub-pixel sub-region, a green sub-pixel sub-region and a red sub-pixel sub-region; and a circularly polarizing plate disposed at an outer side of one of the substrates on a light outgoing side of the display panel; wherein, an opening zone is within a projection area where a projection of each of the pixel regions on the circularly polarizing plate in a thickness direction of the display panel is located, and through the opening zone the corresponding sub-pixel sub-regions are exposed. The present invention also relates to a method for manufacturing an OLED display panel and a display apparatus having the OLED display panel.

Abstract: An organic light-emitting diode display apparatus includes a substrate. An organic light-emitting device is disposed on the substrate and includes a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode. A reflectance of the first electrode is greater than a reflectance of the second electrode. A thin-film transistor is disposed between the substrate and the first electrode and is connected to the first electrode. A first light reflective layer is connected to the thin-film transistor that is disposed between the substrate and the first electrode. A photo sensor is disposed in an outer area of the substrate and is configured to sense light reflected from the first light reflective layer.

Abstract: An organic light-emitting display apparatus includes a display area including first and second pixels. A plurality of photo sensors is arranged in an outer area of the display area. The first pixel includes a first pixel electrode, an opposite electrode, and a first emission layer between the first pixel electrode and the opposite electrode. The first pixel electrode, the opposite electrode, and the first emission layer are arranged on a substrate. The second pixel includes a second pixel electrode, the opposite electrode having a reflectance less than a reflectance of the second pixel electrode, and a second emission layer between the second pixel electrode and the opposite electrode. The second pixel is closer to the plurality of photo sensors than the first pixel. The second pixel electrode includes a first portion in parallel with the substrate and a second portion having a slope with respect to the substrate.

Abstract: An object of the invention is to provide an organic electroluminescence module having light-emitting units capable of keeping power consumption low and to provide an information device having such a module. The organic electroluminescence module of the invention includes a plurality of light-emitting units that are electrically connected to one another and each have a light-emitting region corresponding to a design to be displayed by light emission.

Abstract: An electrode includes: a polymer layer including a non-conductive material; a conductive nanomaterial embedded in a top surface of the polymer layer; and a planarization layer on the polymer layer and on the conductive nanomaterial. The planarization layer includes a conductive material and a surfactant.

Abstract: The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other; a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.

Abstract: The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other; a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.

Abstract: A method of forming an organic light emitting diode (OLED) display device is discussed. The method according to an embodiment includes forming a first bank pattern on a substrate and in an emission region and a non-emission region; forming a second bank pattern on the first bank pattern; forming an organic emission layer on the substrate in the emission region; and forming a planarization film on the substrate to include an opening under the first and second bank patterns in the non-emission region. The second bank pattern is on the first bank pattern in the non-emission region, and the first bank pattern is in the opening of the planarization film in the non-emission region.

Abstract: An image display apparatus includes: a first pixel circuit including a driving transistor that drives a light emitting element and includes a gate electrode on a substrate, a semiconductor layer and a pair of source-drain electrodes; a second pixel circuit disposed adjacent to the first pixel circuit; a second pixel electrode that is formed above the second pixel circuit and is electrically connected to one of the pair of source-drain electrodes of the driving transistor of the first pixel circuit; and a top metal electrode that is electrically connected to one of the pair of source-drain electrodes and is formed to cover at least an entire channel region of the semiconductor layer from above.

Abstract: A thin film transistor array substrate having a pixel arrangement structure includes a first sub-pixel for displaying a first color and a second sub-pixel for displaying a second color alternately located in a first column, and a third sub-pixel for displaying a third color in a second column adjacent to the first column, and via holes of the first through third sub-pixels in a same row are at different positions.

Abstract: An electronic device display may have a color filter layer, a thin-film-transistor layer, and a layer of liquid crystal material. The display may have a display cover layer such as a layer of glass or plastic. Adhesive may be used to attach the upper polarizer to the display cover layer. The thin-film transistor layer may have a substrate with upper and lower surfaces. Thin-film-transistor circuitry may be formed on the upper surface. A display driver integrated circuit may be mounted to the lower surface or a flexible printed circuit and may be coupled to the thin-film-transistor circuitry using wire bonding wires. Through vias that are formed through the thin-film-transistor layer substrate may be used in coupling the thin-film-transistor circuitry to the display driver integrated circuit.

Abstract: Provided is a display device, including: a substrate; signal lines including a gate line, a data line, and a driving voltage line that collectively define an outer boundary of a pixel area; a transistor connected to the signal line; a first electrode extending across the pixel area and formed on the signal line and the transistor, and connected to the transistor, the first electrode having a first portion overlying only the signal line and the transistor, and a second portion comprising all of the first electrode not included in the first portion; a pixel defining layer formed on only the first portion of the first electrode; an organic emission layer formed on substantially the entire second portion but not on the first portion; and a second electrode formed on the pixel defining layer and the organic emission layer.

Abstract: Discussed is an organic light emitting display device that may include a first pixel on a substrate; a switching transistor with a first active layer provided inside the first pixel; a driving transistor with a second active layer provided inside the first pixel; a first light shielding layer overlapping the second active layer; and a second light shielding layer overlapping the first active layer, wherein the first light shielding layer is connected with the driving transistor, and the second light shielding layer is electrically insulated from the first light shielding layer.

Abstract: A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transf

Abstract: In one general aspect, an apparatus can include a semiconductor region having an active region, and an end trench defined within a termination region of the semiconductor region where the end trench has a curved shape.

Abstract: A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.

Abstract: An article includes a support substrate bonded to heterostructure epitaxial layers that include one or more electronic devices. The support substrate has a bonding surface and the heterostructure epitaxial layers have a surface with the epitaxial growth direction of the heterostructure epitaxial layers towards the surface. The surface of the heterostructure epitaxial layers is bonded at the bonding surface of the support substrate by ion exchange between the surface of the heterostructure epitaxial layers and the bonding surface of the support substrate.

Abstract: Disclosed is a method for forming a semiconductor device and a semiconductor device. The method includes: in a SiC semiconductor body, forming crystal defects in a first semiconductor region by introducing non-doping particles into the semiconductor body; and forming a second semiconductor region such that there is a pn junction between the first semiconductor region and the second semiconductor region.

Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.

Abstract: Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Abstract: In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.