Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.

Abstract: A method includes forming a first trench in a semiconductor body between two semiconductor fins, filling the first trench with a first filling material, partially removing the first filling material by forming a second trench such that the second trench has a lower aspect ratio than the first trench, and at least partially filling the second trench with a second filling material so as to form a continuous material layer on the first filling material. A semiconductor device includes a first trench in a semiconductor body between two semiconductor fins, the first trench being filled with a first filling material, and a second trench having a lower aspect ratio than the first trench and being at least partially filled with a second filling material which forms a continuous material layer on the first filling material.

Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Abstract: Provided is a method of manufacturing a thin-film transistor substrate, the method includes forming a semiconductor pattern layer on a substrate. A first insulating film is formed on the semiconductor pattern layer. A metal pattern layer including a gate electrode and first and second alignment electrodes respectively spaced apart from two sides of the gate electrode is formed on the first insulating film. A cover layer covering the gate electrode is formed. The first and second alignment electrodes are removed. A first doping process is performed by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask. The cover layer is removed. A second doping process is performed by doping the semiconductor pattern layer with a second impurity having a lower impurity concentration than the first impurity by using the gate electrode as a mask.

Abstract: The present invention suggests a substrate manufacturing method and a manufacturing method of a semiconductor device comprising: providing a SOI structure having an insulation layer and a silicon layer laminated on a substrate; laminating to form a silicon germanium layer and a capping silicon layer on the SOI structure; implementing oxidation process at two or more temperatures and heat treatment process at least once during the oxidation process to form a germanium cohesion layer and a silicon dioxide layer; and removing the silicon dioxide layer.

Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure.

Abstract: Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

Abstract: A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

Abstract: In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.

Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.

Abstract: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.

Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.

Abstract: A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract: A FinFET device includes a substrate and a fin structure having a semiconductor material layer over the substrate and recessed regions on side walls of the fin structure. The recessed regions have openings facing away from the fin structure. The fin structure has a bottom portion below the recessed regions that is wider than a top portion.

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Abstract: There is provided an oxide semiconductor film composed of nanocrystalline oxide or amorphous oxide, wherein the oxide semiconductor film includes indium, tungsten and zinc, a content rate of tungsten to a total of indium, tungsten and zinc in the oxide semiconductor film is higher than 0.5 atomic % and equal to or lower than 5 atomic %, and an electric resistivity is equal to or higher than 10?1 ?cm. There is also provided a semiconductor device including the oxide semiconductor film.

Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor layer on an insulating layer, a part of the insulating layer being exposed from the oxide semiconductor layer, performing a plasma process by use of chlorine-containing gas on the part of the insulating layer exposed from the oxide semiconductor layer, and removing chlorine impurities from a surface layer of the exposed part of the insulating layer. The chlorine impurities may be removed by a first etching process performed by use of fluorine-containing gas. The fluorine-containing gas may contain CF4 and CHF3. The plasma process may be a second etching process performed by use of chlorine-containing gas.

Abstract: Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2? of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.

Abstract: A terminal structure includes: a first trench extending along a depth direction from an upper surface of a semiconductor substrate; a plurality of second trenches, each of which extends along the depth direction from a bottom surface of the first trench and which are arranged at intervals in a direction away from an element portion; a plurality of first floating regions having a floating potential, each of which is exposed at the bottom surface of the first trench, is disposed between the second trenches, and forms a PN-junction with a surrounding region thereof; and a plurality of second floating regions having a floating potential, each of which is exposed at a bottom surface of the second trench and forms a PN-junction with a surrounding region thereof. The plurality of second floating regions is arranged to be separated from each other in the direction away from the element portion.

Abstract: A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to ?60° C., preferably with a dew point of lower than or equal to ?75° C. without exposing the first substrate after the heat treatment to the air; and then, the first substrate is bonded to a second substrate that serves as an opposite substrate.

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.

Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

Abstract: A solar cell includes: a first bus bar electrode disposed on a first end portion of the solar cell, and to which the wiring member is connected; a second bus bar electrode disposed on a second end portion of the solar cell, and to which the wiring member is connected; first finger electrodes disposed on the solar cell, electrically connected to the first bus bar electrode, and extending in a first direction toward the second bus bar electrode; second finger electrodes disposed on the solar cell, electrically connected to the second bus bar electrode, and extending in a second direction toward the first bus bar electrode. Each first finger electrode has a thickness which decreases as a distance to the second bus bar electrode decreases, and each second finger electrode has a thickness which decreases as a distance to the first bus bar electrode decreases.

Abstract: A Printed Circuit Board Assembly (PCBA) forming an enhanced fingerprint module is disclosed. The PCBA includes a Printed Circuit Board (PCB), an image sensing chip, at least one electrode and a protection layer. An opening in a first insulation layer and a second insulation layer of the PCB together form a sensor portion so that the image sensing chip can be packaged in the opening. Thus, the thickness of the enhanced fingerprint module can be thinner than other fingerprint modules provided by the conventional package methods.

Abstract: A germanium optical receiver in which a dark current is small is achieved. The germanium optical receiver is formed of a p-type germanium layer, a non-doped i-type germanium layer, and an n-type germanium layer that are sequentially stacked on an upper surface of a p-type silicon core layer, a first cap layer made of silicon is formed on the side surface of the i-type germanium layer, and a second cap layer made of silicon is formed on the upper surface and side surface of the n-type germanium layer. The n-type germanium layer is doped with such an element as phosphorus or boron having a covalent bonding radius smaller than a covalent bonding radius of germanium.

Abstract: A solar cell is provided with: a semiconductor substrate having a main surface; a plurality of first electrodes disposed so as to be aligned in one direction on the main surface of the semiconductor substrate, the first electrodes having obverse and side surfaces; a passivation layer disposed on the main surface of the semiconductor substrate and positioned in the gaps between the first electrodes; a conductive adhesive disposed on the obverse surfaces of the first electrodes; and lead members connected to adjacent first electrodes by the conductive adhesive so as to straddle the passivation layer. The solar cell is further provided with contact members, the contact members being positioned in gaps, being disposed on the obverse surface of the passivation layer or the main surface of the semiconductor substrate in alignment with the passivation layer in one direction, and being in contact with parts of the lead members from underneath.

Abstract: A method for roughening silicon substrate surface includes providing a silicon substrate having a waiting-for-etching surface, the waiting-for-etching surface has a plurality of first and second areas; forming a plurality of covering bumps on the first areas, and a gap is formed between each of the covering bumps and each of the first areas; and etching the waiting-for-etching solution by a anisotropic etching solution. The anisotropic etching solution permeates into each of the first areas through the gap to lead the etching time of the first areas is shorter than that of the second areas, so the waiting-for-etching surface becomes a undulate surface having a plurality of undulate structures because the etching depth of the first areas is smaller than that of the second areas.

Abstract: A solar cell module includes a plurality of solar cells each including a semiconductor substrate, an emitter region forming a p-n junction along with the semiconductor substrate, a first electrode connected to the emitter region, and a second electrode connected to a back surface of the semiconductor substrate; and a plurality of wiring members connected to the first electrode or the second electrode and configured to electrically connect the plurality of solar cells in series, wherein a number of wiring members connected to the first electrode or the second electrode of each solar cell is 6 to 30, and the wiring members have a circular cross-section.

Abstract: The present disclosure relates to a transparent electrode, and provides a method for manufacturing a transparent electrode, the method comprising forming a multi-layered transparent conductive film by sequentially laminating a first oxide layer, a metal layer, and a second oxide layer on a transparent substrate, forming a mask pattern on the second oxide layer, performing an etching process using the mask pattern as an etching mask to form, in the second oxide layer, a trench exposing the upper surface of the metal layer, and forming a metal pattern in the trench.

Abstract: Disclosed is method of manufacturing a solar cell including forming a barrier film over at least one surface of a semiconductor substrate or a semiconductor layer, forming a first conductive area on the at least one surface of the semiconductor substrate or the semiconductor layer via ion implantation of a first conductive dopant through the barrier film, and removing the barrier film.

Abstract: Embodiments of the present invention may include single crystal silicon solar cell structures with epitaxially deposited silicon device layers with deep junction(s). In some embodiments, the single crystal silicon solar cell structures may comprise a moderately doped, thick (greater than 10 microns), epitaxially deposited silicon emitter layer. In some embodiments, the single crystal silicon solar cell structures may comprise moderately doped, thick (greater than 10 microns), epitaxially deposited FSF layers. The moderate doping reduces electron-hole recombination within the FSF and emitter layers and causes smaller bandgap narrowing and reduced Auger recombination compared to prior art devices which typically have more heavily doped layers, and the thicker FSF and emitter layers than typically used in prior art devices assist in having a desirable sheet resistance for the solar cell front and back surface, as measured prior to front side and back side metallization.

Abstract: A substrate includes: a base member that has flexibility and insulation properties; an electrically conductive member that is disposed on a top surface of the base member and that has flexibility and electrical conductivity; an electronic component that is disposed over the base member and that includes a terminal joined to the electrically conductive member; and a reinforcing member that is disposed on a bottom surface of the base member at a portion corresponding to a portion of the top surface of the base member at which the electrically conductive member is disposed, wherein the reinforcing member is larger in size than an area over which the terminal and the electrically conductive member are joined together.

Abstract: A biaxially oriented multilayer transparent film including at least two layers of polyester, respectively a core layer and at least one outer layer, which can be identical or different, wherein: i) at least the core layer includes at least one biaxially oriented transparent polyester PE1, ii) at least one of the outer layers includes, on the one hand, at least one biaxially oriented polyester PE2, and, on the other hand, particles coming from the reaction between at least one metal compound and at least one monomeric or oligomeric unit of PE2, the particles having more preferably a d50—as ?m and following an order of preference—between 0.5 and 5; between 1.0 and 4, and between 1.5 and 3.0. Also relates to the manufacture of this film and its applications as a laminate in particular in the backsheets of photovoltaic cells.

Abstract: Solar cells are packaged by placing the solar cells between sheets of encapsulants. The encapsulants are exposed to ultraviolet (UV) light to cure the encapsulants and bond the encapsulants together to encapsulate the solar cells. The UV curing steps may be performed to bond one of the encapsulants to a transparent top cover and the solar cells, and to bond the other encapsulant to the solar cells and a backsheet. A protective package that includes the transparent top cover, encapsulated solar cells, and the backsheet is then optionally mounted on a frame.

Abstract: A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.

Abstract: Solar cells are obtained by singulating a non-rectangular solar cell wafer into a plurality of solar cells, in one embodiment a first solar cell having a surface area corresponding to at least 60% of the wafer surface area but less than 90% of the wafer surface area, and at least two second solar cells each having a surface area of less than 10% of the wafer surface area. Such a first solar cell can be connected in parallel with a plurality of the second solar cells, to establish a substantially rectangular subassembly, and such subassemblies can be combined into a larger solar cell assembly, which may be mounted on a support including other electrical components on the backside thereof, and attached to a small satellite (e.g., CubeSat) exterior surface, or deployable wing.

Abstract: An apparatus for generating electricity from solar radiation having a solar spectrum is provided. The apparatus includes a photovoltaic mirror comprising a plurality of photovoltaic cells, the photovoltaic mirror configured to separate the solar spectrum, absorb a first portion of the solar spectrum, and concentrate a second portion of the solar spectrum at a focus. The apparatus also includes an energy collector spaced from the photo-voltaic mirror and positioned at the focus, the energy collector configured for capturing the second portion of the solar spectrum.

Abstract: A solar cell module includes a plurality of solar cells, each solar cell including a semiconductor substrate, an emitter region, a back surface field region a first electrode connected to the emitter region, a second electrode connected to the back surface field region, and a conductive line connected to one electrode of the first and second electrodes using a conductive adhesive and insulated from the other electrode of the first and second electrodes through an insulating layer, the conductive line being used to connect a plurality of solar cells in series. A thickness of the conductive adhesive between the one electrode and the conductive line is greater than a thickness of the insulating layer between the other electrode and the conductive line.

Abstract: A light splitting optical module that converts incident light into electrical energy, the module including a solid optical element comprising an input end for receiving light, a first side, and a second side spaced from the first side, a first solar cell adjacent to the first side of the solid optical element, and a second solar cell adjacent to the second side of the solid optical element. The first solar cell is positioned to absorb a first subset of incident light and reflect a first remainder of the incident light to the second solar cell through the solid optical element, wherein the first solar cell has a lower band gap than the second cell.

Abstract: Described herein is a photovoltaic plant (1; 1?; 1?; 1??) including a plurality of photovoltaic modules (PV) arranged in arrays (2) spaced with respect to each other, and wherein the photovoltaic modules (PV) of each array (2) have a first assigned inclination (?-l) with respect to a reference direction. Each array (2) of photovoltaic modules (PV) is associated to an array (4; 4?; 4??) of mobile reflection devices (RF) set adjacent thereto, and at least one array (4; 4?; 4??) of mobile reflection devices (RF) is located in a space between successive arrays (2) of photovoltaic modules. The mobile reflection devices (RF) of each array have a second assigned inclination (a2) with respect to a reference direction.