Abstract: The technology described herein can be embodied in a method that includes receiving an audio signal encoding a portion of an utterance, and providing, to a first neural network, data corresponding to the audio signal. The method also includes generating, by a processor, data representing a transcription for the utterance based on an output of the first neural network. The first neural network is trained using features of multiple context-dependent states, the context-dependent states being derived from a plurality of context-independent states provided by a second neural network.

Abstract: A multi-mode speech communication system is described that has different operating modes for different speech applications. A speech service compartment contains multiple system users, multiple input microphones that develop microphone input signals from the system users to the system, and multiple output loudspeakers that develop loudspeaker output signals from the system to the system users. A signal processing module is in communication with the speech applications and includes an input processing module and an output processing module. The input processing module processes the microphone input signals to produce a set user input signals for each speech application that are limited to currently active system users for that speech application.

Abstract: Methods, systems, and computer program products for identifying one or more utterances that are likely to carry the intent of a speaker are provided herein. A method includes providing a transcript of utterances to a word weight scoring module to perform inverse document frequency based scoring on each word in the transcript, thereby generating a weight for each word; calculating a weight for each utterance in the transcript to generate weighted utterances by summing the weights or each constituent word in each utterance; comparing at least one weighted utterance to pre-existing example utterances carrying the intent of a speaker to determine a relevancy score for the at least one weighted utterance; and generating a ranked order of the at least one weighted utterance from highest to lowest intent relevancy score, wherein the highest intent relevancy score corresponds to the utterance which is most likely to carry intent of the speaker.

Abstract: Systems, vehicles, and methods for limiting speech-based access to an audio metadata database are described herein. Audio metadata databases described herein include a plurality of audio metadata entries. Each audio metadata entry includes metadata information associated with at least one audio file. Embodiments described herein determine when a size of the audio metadata database reaches a threshold size, and limit which of the plurality of audio metadata entries may be accessed in response to the speech input signal when the size of the audio metadata database reaches the threshold size.

Abstract: A communication device includes a memory, and a processor coupled to the memory, configured to extract a component of a voice signal that is input, detect a speech rate of the voice signal, adjust the extracted component, based on the detected speech rate, and add the adjusted component to the voice signal to expand a band of the voice signal.

Abstract: Devices that include a near field transducer (NFT); an amorphous gas barrier layer positioned on at least a portion of the NFT; and a wear resistance layer positioned on at least a portion of the gas barrier layer.

Abstract: A plasmon generator generates a surface plasmon, and generates a near-field light from the surface plasmon on a front end surface positioned on an air bearing surface opposing to a magnetic recording medium. The plasmon generator has a first surface that is adjacent to the front end surface and that faces a lower layer where the plasmon generator is deposited, and a second surface at the back side of the first surface relative to a down track direction. The first surface tilts toward a surface that is orthogonal to the down track direction, and, is parallel to across track direction, and the plasmon generator is deposited with a (111) orientation from the first surface toward the second surface.

Abstract: Methods of forming a NFT the methods including forming a hard mask positioned over at least a portion of the rod, the hard mask including at least one layer; patterning a resist mask over the hard mask, the resist mask having an edge positioned over at least a portion of the rod; etching a portion of the hard mask to expose a back edge of the rod and to form a back edge of the hard mask, wherein the back edge of the rod is equivalent to the back edge of the peg; and wherein a forward portion of the rod which is the portion of the rod forward of the back edge is covered by the hard mask; forming a disc mask including a void configured to form a disc of a NFT, the disc mask being formed over at least a portion of the hard mask so that the exposed back edge of the rod is within the void configured to form the disc; etching an area exposed in the void of the disc mask to remove both a rear portion of the rod and the surrounding dielectric up to the back edge of the hard mask edge; depositing a disc material in th

Abstract: A magnetic head includes a coil, a main pole, a write shield and first and second yokes. The first and second yokes are connected to the write shield. The coil includes a main coil portion for driving the main pole, a first sub-coil portion for driving the first yoke, and a second sub-coil portion for driving the second yoke. A magnetic field produced in the main pole by the main coil portion and a magnetic field produced in each of the first and second yokes by the first and second sub-coil portions are in directions opposite to each other.

Abstract: A method operates a digital measurement unit and an ambient temperature control unit as to a plurality of TMR sensors, each having a geometry including area Amr and tunnel barrier thickness tB. The method includes dividing the plurality of TMR sensors into test groups. For each test group, the method includes setting the ambient air temperature Tair, applying a voltage pulse at Vdeg and time ?p Npulse times until dielectric breakdown, and appending Npulse and ?p to a dataset. The method includes fitting a survival fraction of form: S ? ( t deg , ? db ) = ? - ( t deg ? db ) ? versus Npulse, wherein tdeg=Npulse·?p, to determine ? and ?db. The method includes determining a temperature rise based on ?p, determining, based on the temperature rise, ?mr(?db,Amr), and determining T mr = T air + P mr ? mr ? ( ? db , A mr ) based on ?mr(?db,Amr).

Abstract: Various aspects of the present disclosure are directed toward a disc drive actuator assembly including an e-block, a bearing, and a sleeve. The bearing includes an inner race, an outer race and a plurality of balls between the inner and outer races. The inner race being coupled to a pivot shaft of a disc drive, and the bearing being configured and arranged to facilitate rotation of the e-block around the pivot shaft. The sleeve coupling the outer race of the bearing to the e-block, and includes a groove along an inner diameter of the sleeve adjacent the outer race. The groove and outer race mitigate rotational torque changes due to thermal effects upon the disc drive actuator assembly by allowing the outer race of the bearing to deform into or away from the groove and therein mitigate or prevent the generation of certain forces in bearings.

Abstract: A magnetic head device with high joint strength in an arm and a suspension is provided. The magnetic head device comprises an arm, a suspension overlapping with a leading end part of the arm, a slider located at a leading end part of the suspension, and a joint part that is located between the leading end part of the arm and the suspension and that joins the arm and the suspension, while the joint part includes Sn.

Abstract: As disclosed herein a method for encoding information on tape using write offset gaps. The method includes receiving a request to write a dataset on a tape medium using a plurality of head groups, and identifying information to be encoded when writing the dataset. The method further includes determining a head group offset pattern that encodes the information, and writing the dataset using the head group offset pattern. Also disclosed herein is a method for decoding information on tape using write offset gaps. The method includes reading a dataset from a tape medium using a plurality of head groups, and determining a head group offset pattern used to read the dataset. The method further includes decoding information encoded in the head group offset pattern to provide decoded information. A computer program product corresponding to the above method is also disclosed herein.

Abstract: A tolerance ring includes: a base formed of a strip-like member substantially wound around into a shape; a plurality of projections provided along a winding direction of the base so as to protrude from an outer peripheral surface of the base in a radial direction of the base orthogonal to the outer peripheral surface; at least one extended portion extending from at least one of edge end portions in a width direction of the base, the width direction extending orthogonally to the winding direction and the radial direction. The extended portion extends from a region that includes at least one of a plurality of straight lines passing through respective contact points disposed between a section of the base and a circumscribed circle that circumscribes the section and extend in parallel with the width direction.

Abstract: Rotational latency is reduced in a standard conventional form factor HDD system by replacing, for example, the prior art rotary arm actuator of a conventional HDD, with one or more belts and pulleys and one or more read/write heads mounted on, or otherwise associated with the belts. Multiple scaled iterations facilitate energy savings and power optimized systems, without compromise to data access performance.

Abstract: A data storage device is disclosed comprising a disk, a head, a shock sensor, and an oscillator circuit responsive to the shock sensor and configured to generate an oscillating signal using positive feedback. A resonant frequency of the shock sensor is detected based on the oscillating signal. A physical shock affecting the head actuated over the disk is detected based on a response of the shock sensor to the physical shock and based on the detected resonant frequency of the shock sensor.

Abstract: Provided herein is an apparatus, including a first region of a substrate corresponding to a data region in a patterned recording medium; a first set of protrusions etched out of the first region of the substrate, wherein the protrusions of the first set of protrusions are rectangle shaped; a second region of the substrate corresponding to a servo region in a patterned recording medium; and a second set of protrusions etched out of the second region of the substrate, wherein the second set of protrusions includes radial lines etched into the substrate across chevrons etched out of the substrate.

Abstract: A data storage device is disclosed comprising a disk comprising a plurality of data sectors and a plurality of servo sectors, and a head actuated over the disk, wherein the head comprises a laser configured to heat the disk while writing data to the disk. When the head is over a first data sector not being written, a first prelase bias is applied to the laser, and when the head is over a servo sector, a second, lower prelase bias is applied to the laser. When the head is over a second data sector being written, a write bias higher than the first prelase bias is applied to the laser.

Abstract: A method comprises writing a waveform on a magnetic recording medium using a heat-assisted magnetic recording apparatus which includes a laser. The method also comprises reading back the waveform from the medium, and detecting one or more transition shifts in the readback waveform indicative of a mode hop of the laser. The method further comprises measuring a metric of the one or more transition shifts.

Abstract: Provided is a holographic data storage system characterized by including: a first polarizing beam splitter (PBS), wherein at least either of a first lens module and a second lens module transmits P-polarized light and reflects S-polarized light; a relay lens collecting light passing through the first PBS; a mirror reflecting the light collected through the relay lens back to the relay lens; and a quarter wave plate located between a second PBS beam splitter and the relay lens, converting transmitted linearly polarized light into circularly polarized light, and converting the circularly polarized light into linearly polarized light. By reducing the volume of the relay lens, it is possible to decrease the size of the holographic data storage system, and by decreasing the number of lenses, it is possible to lower manufacturing costs.

Abstract: A system, method, and computer program product for the banded allocation of storage device address ranges in distributed parity schemes is disclosed. A storage system with storage devices logically divides up the storage devices into bands of contiguous logical block address ranges. A storage controller provisions logical volumes in the bands. Upon unavailability of a storage device, the data pieces are reconstructed at the next available data extent within the same band on the other storage devices. The storage controller detects a replacement drive and logically divides the replacement storage device into the same number of bands as on the other storage devices. The storage controller transfers the reconstructed data pieces to the replacement drive and places the data pieces within the same bands on the replacement drive.

Abstract: The invention relates to devices, systems and methods for restoring optical discs, including CD's, DVD's and Blu-ray discs. The invention provides an easy to use device for user's to repair optical discs without having to clean or remove rotating pads in the device between uses for the life of the pads of about 84 cycles.

Abstract: Methods and systems for creating and playing out animated video scenes. An animated scene is created by first receiving a selection of an asset element to be used in the scene. Next, a first marker position is received, a first marker is displayed at the marker position, and an association between the asset element and the first marker is established. This process is repeated for a second marker displayed at a second marker position. Thereafter, a movement path from the first marker position to the second marker position is established. The movement path includes a sequence of coordinates and associated times. Finally, the instructions that cause the asset element to move along the movement path are generated.

Abstract: A system and method for determining video clips including interesting content from video data. The system may receive annotation data identifying time and positions corresponding to objects represented in the video data and the system may determine priority metrics associated with each of the objects. By associating the priority metrics with the time and positions corresponding to the objects, the system may generate a priority metric map indicating a time and position of interesting moments in the video data. The system may generate moments and/or video clips based on the priority metric map. The system may determine a time (e.g., video frames) and/or space (e.g., pixel coordinates) associated with the moments/video clips and may simulate camera motion such as panning and/or zooming with the moments/video clips. The system may generate a Master Clip Table including the moments, video clips and/or annotation data associated with the moments/video clips.

Abstract: Certain embodiments provide systems and method for creating a processed video stream. A method for creating a processed video stream includes receiving project instructions and media at a computing device executing a socially interactive application. The project instructions can include a project type. The method also includes uploading the project instructions and media to a server connected to the computing device. The method includes creating a project script based on the project type at a processor of the server. The method includes encoding, at the processor, a video stream based on the project script. The method also includes sharing the video stream at the socially interactive application.

Abstract: A television receiver may detect during a primary recording of particular programming degradation of a received signal quality associated with the particular programming to at or below a predetermined threshold value. The television receiver may instantiate a secondary recording of the particular programming during the primary recording when the particular programming is accessible over at least one terrestrial network. The television receiver may query a computing system to acquire content associated with at least one gap in content within the primary recording present due to received signal quality. The television receiver may output during playback of the primary recording a notification to enable access to the secondary recording when content associated with the at least one gap in content within the primary recording is unavailable over the at least one terrestrial network.

Abstract: A television receiver may detect at least one gap in content within an instance of recorded programming. The television receiver may send to a computer system a request to repair the at least one gap in content within the instance of recorded programming. The television receiver may receive one of content associated with the at least one gap in content, and a notification that indicates unavailability of content associated with the at least one gap in content. The television receiver may edit the instance of recorded programming to include content associated with the at least one gap in content when content associated with the at least one gap in content is received.

Abstract: Systems and methods for converting interactive multimedia content authored for distribution via a physical medium for electronic distribution are disclosed. One embodiment of the invention includes building an object model of interactive multimedia content authored for distribution via a physical medium using a content authoring system, automatically authoring a user interface based upon the object model using the content authoring system, and packing the transcoded multimedia content into at least one container.

Abstract: Embodiments of the invention relate to an automated, intelligent visualization of data through text and graphics for connecting a wide range of data sources to graphics visualization software and automating its presentation, including building on a standard template driven system for generating graphics from data. Some of these building mechanisms include: Service Handlers, which are plugin components with their own process for converting the data into something uniform, Input Behaviors, which define actions and data to deliver from a service, a system for matching templates to input behaviors by the set of variables in each and the rules for matching them, a Schedule Request mechanism, which connects the data from the service, via the input behavior mechanism, to the correct titles, and handles the assignment of data and then conducts the appropriate actions, and the use of handler defined queues for managing the order of things in parallel.

Abstract: Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F2 within an individual of the tiers. Also disclosed is an array of nonvolatile memory cells comprising a plurality of unit cells which individually comprise three elevational regions of programmable material, the three elevational regions comprising the programmable material of at least three different memory cells of the unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells. Other embodiments and aspects are disclosed.

Abstract: A semiconductor memory including a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair in which the sense amplifier includes; precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line.

Abstract: A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.

Abstract: An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit.

Abstract: According to one embodiment, there is provided a memory system including a 1st memory group, a 2nd memory group, a power supply voltage adjustment circuit, a 1st line, a 1st switch, a 2nd line, a 3rd line, and a 4th line. The power supply voltage adjustment circuit includes a 1st terminal and a 2nd terminal. The 1st line electrically connects the 1st terminal to the 1st memory group. The 1st switch includes a 3rd terminal, a 4th terminal, and a 5th terminal. The 1st switch electrically connects the 3rd terminal to the 4th terminal when turned on. The 2nd line electrically connects the 1st terminal to the 3rd terminal. The 3rd line electrically connects the 4th terminal to the 2nd memory group. The 4th line electrically connects the 2nd terminal to the 5th terminal.

Abstract: A sense amplifier for sensing a line of a semiconductor device comprises a p-channel pull-up transistor for charging the line, an inverter, and a pull-up controller. The p-channel pull-up transistor and the inverter are coupled to the line. The inverter inverts a line voltage of the line. The pull-up controller is coupled to the gate of the p-channel pull-up transistor and operates the p-channel pull-up transistor as a function of the inverted line voltage.

Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

Abstract: According to an example, a method for adaptive-granularity row buffer (AG-RB) caching may include determining whether to cache data to a RB cache, and adjusting, by a processor or a memory side logic, an amount of the data to cache to the RB cache for different memory accesses, such as dynamic random-access memory (DRAM) accesses. According to another example, an AG-RB cache apparatus may include a 3D stacked DRAM including a plurality of DRAM dies including one or more DRAM banks, and a logic die including a RB cache. The AG-RB cache apparatus may further include a processor die including a memory controller including a predictor module to determine whether to cache data to the RB cache, and to adjust an amount of the data to cache to the RB cache for different DRAM accesses.

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

Abstract: Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

Abstract: A voltage supply device includes a bias generator, a control signal generator and a cell switching circuit. The bias generator divides a first supply voltage to output a plurality of divided supply voltages. The control signal generator receives the plurality of divided supply voltages to generate a plurality of control signals. The cell switching circuit receives the plurality of control signals to provide nonvolatile memory cells with one or more of a ground voltage, the first supply voltage, or a second supply voltage different from the first supply voltage. Each of the bias generator, the control signal generator and the cell switching circuit is implemented with medium voltage MOS transistors having a breakdown voltage of from approximately 7 volts to approximately 15 volts.

Abstract: A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.

Abstract: Self-referenced magnetic random access memory (MRAM) cell including a magnetic tunnel junction including a sense layer; a storage layer having a storage magnetization; a tunnel barrier layer between the sense and the storage layers; and an antiferromagnetic layer exchange-coupling the storage layer such that the storage magnetization can be pinned when the antiferromagnetic layer is below a critical temperature and freely varied when the antiferromagnetic layer is heated at or above the critical temperature. The sense layer includes a first sense layer having a first sense magnetization, a second sense layer having a second sense magnetization and spacer layer between the first and second sense layers. The MRAM cell can be read with low power consumption.

Abstract: An apparatus is described having a select line and an interconnect with Spin Hall Effect (SHE) material. The interconnect is coupled to a write bit line. A transistor is coupled to the select line and the interconnect. The transistor is controllable by a word line. The apparatus also includes an MTJ device having a free magnetic layer coupled to the interconnect.

Abstract: A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer.

Abstract: A magnetic memory device can include a plurality of separately controllable magnetic memory segments configured to store data. A plurality of separately controllable source lines can each be coupled to a respective one of the plurality of separately controllable magnetic memory segments.

Abstract: A memory device may include a data region, a reference region, a resistor circuit, and a sense amplifier. The data region may include a plurality of data memory cells coupled between a first bit line and a first source line. The data region may provide a data voltage corresponding to data stored in each of the data memory cells. The reference region may include a plurality of reference memory cells coupled between a reference bit line and a reference source line. The reference region may provide a reference voltage. The resistor circuit may include one or more resistors, and is coupled between the reference source line and a power source line. The sense amplifier may provide an output voltage by comparing the data voltage and the reference voltage. The power source line may be either a ground voltage or a negative voltage.

Abstract: A semiconductor apparatus with a plurality of slices electrically coupled through through electrodes. Any one slice of the plurality of slices may be configured to generate a refresh cycle signal in response to a refresh command, and transmit the refresh cycle signal to the other slices through the through electrodes. The other slices may be configured to perform refresh operations in synchronization with the refresh cycle signal.

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract: Provided is a stacked memory device including a base die and a plurality of core dies. The base die may include: a weak cell address storage unit for storing weak cell addresses; a serialization unit for selecting at least one of the weak cell addresses as a target weak cell address, converting the selected target weak cell address into a serial weak cell address, and outputting a strobe signal synchronized with the serial weak cell address; a deserialization unit for storing the serial weak cell address based on the strobe signal, and converting the stored address into a parallel weak cell address based on a refresh end signal; and a refresh control unit for selecting the parallel weak cell address or a refresh address generated based on a refresh signal, and outputting a target address.