Abstract: A memory device may include a plurality of memory banks; a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied, wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

Abstract: A reception circuit includes a control signal generation circuit that generates a first enable signal based on a strobe signal and a second enable signal based on a core clock signal and a pointer control signal. A pattern data generation circuit generates determination pattern data from the first enable signal. An asynchronous transfer circuit latches the determination pattern data based on the first enable signal and the strobe signal and outputs determination data corresponding to the latched determination pattern data based on the second enable signal and the core clock signal. A determination circuit determines a timing for generating the pointer control signal based on the determination data. A set value calculation circuit calculates a transfer set value based on the determination result of the determination circuit. The control signal generation circuit updates the pointer control signal based on the transfer set value.

Abstract: A circuit for driving a sense amplifier of a semiconductor memory device is provided. The circuit includes a first driving circuit configured to supply a current from a power node to a first driving node of the sense amplifier based on a first driving control signal, a source control circuit configured to generate a control signal based on a second driving control signal and a voltage of the drain node, and a second driving circuit configured to draw current from a second driving node of the sense amplifier to a ground node based on the control signal.

Abstract: A semiconductor memory apparatus may precharge a plurality of word lines to first and/or second low voltages. The semiconductor memory apparatus may precharge an odd word line and an even word line to different levels, and accelerate passing GIDL occurring from a memory cell toward a word line to screen memory cells susceptible to GIDL.

Abstract: According to one embodiment, a semiconductor storage device includes a flip-flop circuit configured with two stages of inverters composed of TFETs. The flip-flop circuit includes first and second nodes. A first access transistor composed of a TFET is provided between the first node and a first write word-line. A second access transistor composed of a TFET is provided between the second node and a second write word-line. A MOS transistor which has a gate connected to the first node and responds to a voltage impressed on a read word-line to supply a voltage corresponding to a potential at the first node to a read bit-line is included. The first and second access transistors are configured with TFETs connected in a manner that a drain current flows from the first and second nodes to a write bit-line when turned on.

Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

Abstract: A storage system and method for using hybrid blocks with sub-block erase operations are provided. In one embodiment, a storage system is provided comprising a memory comprising a block, wherein the block comprises a first sub-block and a second sub-block; and a controller in communication with the memory. The controller is configured to erase the first sub-block, wherein the second sub-block is programmed; and program the first sub-block to fewer bits per cell than the second sub-block is programmed to. Other embodiments are provided.

Abstract: Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a memory cell including first and second electrodes and a resistance change film therebetween, and a control circuit controlling a potential difference between the first and second electrodes. The control circuit reversibly changes the memory cell to a first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode. The control circuit reversibly changes the memory cell to a second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode.

Abstract: A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces, and a first switching crossbar array disposed on a first side of the memory box. A plurality of vias connects the circuit layer to the first switching crossbar layer. The first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer. A method for addressing multilayer memory is also provided.

Abstract: A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer.

Abstract: A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.

Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.

Abstract: A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.

Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.

Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.

Abstract: A maintaining device and a maintenance method for maintaining the normal operation of a resistive random access memory are disclosed. The maintenance method can be executed by the maintaining device. Said memory includes first and second electrodes. The first electrode is not grounded. The maintaining device is connected to the first electrode so that the first electrode receives an operational signal and a restoring signal generated by the maintaining device. The operational signal transits from a zero voltage to a non-zero voltage and then to the zero voltage. If the operational signal has already transited from the non-zero voltage to the zero voltage, the maintenance method controls the restoring signal to transit from the zero voltage to a negative voltage, controls the restoring signal to remain the negative voltage for a period of restoring time, and controls the restoring signal to transit from the negative voltage to the zero voltage.

Abstract: A memory array including: a plurality of volatile memory cells, each including a latch; and a plurality of non-volatile memory cells, each including at least one resistive element that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states, each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.

Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A scheduling device according to one embodiment includes an access request accepting section and an access request selecting section. The access request accepting section is configured to accept access requests from requesters. The access request selecting section is configured to select a first access request as a reference for access request selection from among the accepted access requests, select an access request transferable in a bank interleave (BI) mode with respect to the first access request, and select an access request transferable in a continuous read/write (CN) mode in response to a determination that there is no access request transferable in the BI mode, or that the preceding access request was in the BI or the CN mode. The access request selecting section is configured to repeat the selections in response to a determination that there is no access request transferable in the BI mode and in the CN mode.

Abstract: The disclosed embodiments comprise a flash memory device that can be configured to operate as a read only memory device. In some embodiments, the flash memory device can be configured into a flash memory portion and a read only memory portion.

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.

Abstract: There may be provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array including a plurality of memory strings. The semiconductor memory device may include a peripheral circuit for performing a program operation on the plurality of memory strings, and a control logic for controlling the peripheral circuit to perform the program operation. The control logic may control the peripheral circuit to adjust potential levels of program permission voltages to be applied to the plurality of memory strings according to arrangement positions of the memory strings.

Abstract: The semiconductor device includes memory strings, word lines, bit lines and a circuit. The memory strings each include memory cells connected in series. The gate electrode surrounds the channel. The word lines are electrically connected to gate electrodes of memory cells. The bit lines are electrically connected to ends of current paths in the memory strings respectively. The circuit controls a program operation of information. The information includes at least three of a first, a second and a third levels or more corresponding to threshold voltages of the memory cells. When starting the program operation, the circuit applies a program selection voltage to channels of memory cells to be programmed at the second level, and a program suppression voltage to channels of memory cells maintaining the first level and channels of memory cells to be programmed at the third level.

Abstract: Disclosed herein is a regulator for a non-volatile memory is provided. The regulator comprises an operational amplifier for receiving a reference voltage and a feedback voltage to output a voltage amplifying the difference of the reference voltage and the feedback voltage, the feedback voltage being obtained by dividing an output voltage of the regulator; a first switching unit turning on in response to the amplified voltage; a second switching unit electrically connected between a first node and the first switching unit for protecting the first switching unit from the voltage of the first node; and a third switching unit providing the output voltage of the regulator to a second node in response to a voltage of the first node.

Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Abstract: A data storage device includes a solid-state memory including memory cells and a controller configured to perform a first programming scheme that programs a first subset of the cells to a first voltage state using a first target voltage, programs a second subset to a second voltage state using a second target voltage higher than the first target voltage, programs a third subset to a third voltage state using a third target voltage higher than the second target voltage, and programs a fourth subset to a fourth voltage state using a fourth target voltage higher than the third target voltage. A difference in voltage between the fourth target voltage and the third target voltage may be greater or less than a difference in voltage between the third target voltage and the second target voltage and/or a difference in voltage between the second target voltage and the first target voltage.

Abstract: A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.

Abstract: A monotonically increasing persistent counter is described that is persistent across reboots of a system in which it is incorporated. The described counter employs an event counter module that counts events that are generated by various event generators within the system. One type of event that can be counted by the described counter is a state change. In various implementations, the event counter module, when employed as a state change counter module, includes a state change counter that counts state changes, and a journal mode component which provides journaling functionality which makes it possible to accommodate large numbers of state changes while, at the same time, recover the counter in the event of a system failure. In at least some embodiments, one or both of the state change counter and the journal mode component are implemented using NOR flash memory.

Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.

Abstract: A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.

Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. In one aspect, a read pass voltage is discharged in a manner that purges residual electrons from a memory string channel after a sensing operation. A control circuit may begin to discharge the read pass voltage from memory cell control gates at different strategic times in order to provide a path for residual electrons to leave the channel. Because residual electrons have been purged from the channel, no or very few electrons will be trapped in shallow interface traps of the memory cell if the word line voltage does creep up following sensing. Thus, the word line voltage may still creep up after the sensing operation without changing a threshold voltage of the memory cell.

Abstract: Methods for reading data that was functionally stored include reading a pattern of threshold voltages from a particular group of memory cells, determining which pattern, of a plurality of patterns, matches the read pattern, and determining a group of decoded data associated with the pattern determined to match the read pattern.

Abstract: A self-timer for a sense amplifier in a memory device is disclosed.

Abstract: Some embodiments include apparatuses and methods having a compensation unit to provide a compensation value based at least in part on a threshold voltage value of a memory cell. At least one of such embodiments includes a controller to select a code during an operation of retrieving information from the memory cell to represent a value of information stored in the memory cell. Such a code can be associated with an address having an address value based at least in part on the compensation value. Additional apparatuses and methods are described.

Abstract: A semiconductor device and search circuit for and method of searching for a count of erasures in a semiconductor memory. The semiconductor device includes a semiconductor memory in which data erasure is performed in units of blocks. A block management memory stores, corresponding to each of the blocks, a piece of erasure count data representing a count of erasures of data performed in the block. An erasure count search circuit successively reads the pieces of erasure count data from the block management memory so as to search for a block corresponding to a piece of erasure count data representing an intended erasure count from among the pieces of erasure count data read from the block management memory. The circuit also outputs an address of the searched block as an erasure count address.

Abstract: Non-volatile storage systems, and methods for programming non-volatile storage elements of non-volatile storage systems, are described herein. A method for programming a non-volatile storage element, wherein a loop number is incremented with each program-verify iteration includes performing a plurality of program-verify iterations for the non-volatile storage element. This includes inhibiting programming of the non-volatile storage element when the loop number is less than a loop number threshold corresponding to a target data state that the storage element is being programmed to. This also includes enabling programming of the non-volatile storage element when the the loop number is greater than or equal to the loop number threshold corresponding to the target data state that the storage element is being programmed to.

Abstract: A method for operating a memory is provided. The memory has an array of memory cells arranged in a plurality of rows and columns. Each row includes a label storage unit. The method includes receiving a first to-be-programmed data set to be stored into a target row and determining whether a condition is satisfied. When the condition is satisfied, performing a first operation on the first to-be-programmed data set to obtain a second to-be-programmed data set, programming the second to-be-programmed data set into the target row of memory cells, and setting the value of the label storage, unit to be a first labeling value. When the condition is not satisfied, performing a second operation on the first to-be-programmed data set to program the first to-be-programmed data set into the target row of memory cells, and setting the value of the label storage unit to be a second labeling value.

Abstract: Disclosed is a shift register including stages for sequentially outputting output pulses including carry and scan pulses. Odd-numbered stages supply corresponding scan pulses to odd-numbered gate lines in a sequential manner, and even-numbered stages supply corresponding scan pulses to even-numbered gate lines in a sequential manner. Each stage includes a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse having a low-level voltage equal to the first discharge voltage, and supplying the carry pulse to at least one of upstream and downstream stages, and a scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage than the first discharge voltage and the clock pulse, and supplying the scan pulse to a corresponding gate line.

Abstract: According to an embodiment of the present disclosure, a shift register unit may include: a first control module, configured to transmit a start signal to a first node; a second control module, configured to pull a potential of a second node to a potential different from a potential of the first node, under a control of a first clock signal; a carry output module, configured to output a carry signal according to the potential of the first node and the potential of the second node; and a shift output module, configured to output a shift signal according to the potential of the first node and the potential of the second node.

Abstract: Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.

Abstract: Individual memory chips are simultaneously tested by a tester using selectively enabled stress modules that apply a corresponding stress test to memory cells, wherein each stress test is associated with a corresponding failure attribute for the memory cells. Built-in self-test (BIST)/built-in self-stress (BISS) circuitry is provided in each stress module and may configured to selectively apply one or more stress test(s) during the simultaneous testing of a plurality of memory chips.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.