Patents Issued in April 13, 2017
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Publication number: 20170104016Abstract: The present disclosure provides a method for fabricating an array substrate. The method includes providing a substrate; forming a first pattern on the substrate including a plurality of signal lines and a plurality of electrostatic discharge (ESD) lines, wherein an ESD line is configured to connect two signal lines; and removing a portion of each ESD line during a process for forming a second pattern over the first pattern to disconnect the two signal lines.Type: ApplicationFiled: September 17, 2015Publication date: April 13, 2017Inventor: XIAOLIN WANG
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Publication number: 20170104017Abstract: The present invention relates to a thin film transistor array substrate and a method of manufacturing the same.Type: ApplicationFiled: December 19, 2016Publication date: April 13, 2017Inventors: Seung Hyun PARK, Jun Ho SONG, Jean Ho SONG
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Publication number: 20170104018Abstract: In a semiconductor device including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. A miniaturized transistor including an oxide semiconductor is provided. A method for manufacturing a semiconductor device including an oxide semiconductor film includes the following steps: forming an oxide semiconductor film; forming an insulating film over the oxide semiconductor film; forming a conductive film over the insulating film; forming a first protective film over the conductive film; and forming a second protective film over the first protective film. The first protective film, the conductive film, and the insulating film are processed using the second protective film as a mask. After the second protective film is removed, the conductive film and the insulating film are processed using the first protective film as a mask to have a smaller area than that of the second protective film.Type: ApplicationFiled: October 10, 2016Publication date: April 13, 2017Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Takahiro SATO, Masami JINTYOU
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Publication number: 20170104019Abstract: An image sensor includes a substrate that further includes a sensor array and a heat spreading layer on a surface of the substrate. The heat spreading layer may include one or more of a synthetic diamond layer, a graphene layer, or a diamond-like carbon (DLC) layer. The heat spreading layer enables substantially uniform distribution of heat through at least a portion of the sensor array. Such substantially uniform heat distribution may enable substantially uniform dark current in the portion of the sensor array, thereby reducing a probability of dark shading in the portion of the sensor array. The portion of the sensor array may include an active pixel sensor area. The portion of the sensor array may include an optical black sensor area.Type: ApplicationFiled: October 10, 2016Publication date: April 13, 2017Applicant: Samsung Electronics Co., Ltd.Inventor: Young-woo Jung
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Publication number: 20170104020Abstract: An image sensor includes a semiconductor substrate, a first pair of photoelectric conversion regions in a first pixel region of the substrate and a first isolation structure between the photoelectric conversion regions of the first pair of photoelectric conversion regions. The sensor further includes a second pair of photoelectric conversion regions in a second pixel region of the substrate adjacent the first pixel region and a second isolation structure between the photoelectric conversion regions of the second pair of photoelectric conversion regions and having different optical properties than the first isolation structure. First and second different color filters (e.g.Type: ApplicationFiled: October 11, 2016Publication date: April 13, 2017Inventors: Kyungho Lee, Seounghyun Kim, Hyuk An, Yun Ki Lee, Hyuk Soon Choi
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Publication number: 20170104021Abstract: An image sensor includes a substrate including an active region defined by a device isolation layer, a photoelectric conversion layer in the substrate, a floating diffusion region in the substrate at an edge of the active region, and a transfer gate on the active region. The transfer gate is in contact with a portion of the device isolation layer adjacent the active region.Type: ApplicationFiled: October 11, 2016Publication date: April 13, 2017Inventors: Jongeun Park, Yitae Kim, Donghyuk Park, Jungchak Ahn
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Publication number: 20170104022Abstract: An image pickup element mounting substrate includes: a frame body composed of an insulating layer, a through hole being defined by an internal periphery of the frame body; an electronic component mounted on a lower surface side of the frame body; and a flat plate which is disposed on a lower surface of the frame body and covers an opening of the through hole while being partly kept in out-of-contact with the electronic component, the flat plate including an image pickup element mounting section at a part of an upper surface thereof which part is surrounded by the frame body, a lower surface of the electronic component being located above a level of a lower surface of the flat plate.Type: ApplicationFiled: June 24, 2015Publication date: April 13, 2017Applicant: KYOCERA CorporationInventors: Takuji OKAMURA, Akihiko FUNAHASHI
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Publication number: 20170104023Abstract: A method of manufacturing an optical apparatus is provided. The method includes arranging a photo device above a substrate with an adhesive located between the photo device and the substrate, forming a bonding member that bonds the substrate and the photo device by curing the adhesive, and arranging, above the photo device, a transparent plate and a sealing member. The sealing member covers the photo device and is located between the transparent plate and the substrate. An elastic modulus of the bonding member is 1 GPa or less.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventor: Takashi Miyake
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Publication number: 20170104024Abstract: Realization of an adequate hole accumulation layer and reduction in dark current are allowed to become mutually compatible. A solid-state imaging device 1 having a light-receiving portion 12 to photoelectrically convert incident light is characterized by including a film 21, which is disposed on a light-receiving surface 12s of the above-described light-receiving portion 12 and which lowers an interface state, and a film 22, which is disposed on the above-described film 21 to lower the interface state and which has a negative fixed charge, wherein a hole accumulation layer 23 is disposed on the light-receiving surface 12s side of the light-receiving portion 12.Type: ApplicationFiled: October 21, 2016Publication date: April 13, 2017Inventors: Tetsuji Yamaguchi, Yuko Ohgishi, Takashi Ando, Harumi Ikeda
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Publication number: 20170104025Abstract: An imaging device that has a structure where a transistor is used in common by a plurality of pixels and is capable of imaging with a global shutter system is provided. A transistor that resets the potential of a charge detection portion, a transistor that outputs a signal corresponding to the potential of the charge detection portion, and a transistor that selects a pixel are used in common by the plurality of pixels. A transistor is provided between a power supply line and a photoelectric conversion element. Exposure is performed by turning on the transistor. Imaging data is retained in a charge retention portion by turning off the transistor.Type: ApplicationFiled: September 29, 2016Publication date: April 13, 2017Inventor: Naoto KUSUMOTO
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Publication number: 20170104026Abstract: A method for manufacturing a multi-spectral photodiode array in a CdxHg1-xTe semiconductor layer constituted of pixels, the method including a step of producing a PN junction in each pixel and further includes producing a cadmium-rich structure on the semiconductor layer, structured so that all the pixels are not surmounted by a same quantity of cadmium atoms, this quantity being able to be zero; and inter-diffusion annealing, realising the diffusion of cadmium atoms from the cadmium-rich structure to the semiconductor layer. Pixels that do not all have the same cutoff wavelength are thereby obtained.Type: ApplicationFiled: October 10, 2016Publication date: April 13, 2017Applicant: Commissariat a L'Energie Atomique et aux Energies AlternativesInventor: Florent ROCHETTE
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Publication number: 20170104027Abstract: In an embodiment, a light emitting device comprises a light emitting diode chip and a spherical extending electrode. The light emitting diode chip includes a semiconductor epitaxial structure, a first electrode and a second electrode. The first electrode and the second electrode are disposed on two opposite sides of the semiconductor epitaxial structure, respectively. The first electrode is disposed between the semiconductor epitaxial structure and the spherical extending electrode, and the spherical extending electrode is electrically connected to the semiconductor epitaxial structure electrically through the first electrode. The volume of the spherical extending electrode is greater than that of the light emitting diode chip.Type: ApplicationFiled: December 28, 2015Publication date: April 13, 2017Inventors: Wei-Chung Lo, Yu-Wei Huang, Tao-Chih Chang, Chih-Ming Shen
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Publication number: 20170104028Abstract: Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventor: Daniel R. SHEPARD
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Publication number: 20170104029Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.Type: ApplicationFiled: October 7, 2016Publication date: April 13, 2017Inventors: Pinghui LI, Ming ZHU, Shunqiang GONG, Wanbing YI, Darin CHAN, Yiang Aun NGA
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Publication number: 20170104030Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.Type: ApplicationFiled: October 19, 2016Publication date: April 13, 2017Inventors: Andrea Redaelli, Agostino Pirovano
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Publication number: 20170104031Abstract: Provided are selector elements with active components comprising insulating matrices and mobile ions disposed within these insulating matrices. Also provided are methods of operating such selector elements. The insulating matrices and mobile ions may be formed from different combinations of materials. For example, the insulating matrix may comprise amorphous silicon or silicon oxide, while mobile ions may be silver ions. In another example, the active component comprises copper and germanium, selenium, or tellerium, e.g., Se61Cu39, Se67Cu33, or Se56Cu44. The active component may be a multilayered structure with a variable composition throughout the structure. For example, the concentration of mobile ions may be higher in a center of the structure, away from the electrode interfaces. In some embodiments, outer layers may be formed from Ge33Se24Cu47, while the middle layer may be formed from Ge47Se29Cu24.Type: ApplicationFiled: October 6, 2016Publication date: April 13, 2017Applicant: Intermolecular, Inc.Inventors: Mark Clark, Prashant Phatak, Charlene Chen, Ashish Bodke, Salil Mujumdar, Federico Nardi, Satbir Kahlon, Sergey V. Barabash, Feihu Wang
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Publication number: 20170104032Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yusuke KOBAYASHI, Yoshihisa IWATA, Takeshi SUGIMOTO
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Publication number: 20170104033Abstract: An array substrate and a manufacturing method for the same are disclosed. The manufacturing method includes a step of forming a top-gate type thin-film transistor including steps of forming a source electrode and a drain electrode on a substrate; sequentially and stackedly forming an organic semiconductor layer, a first insulation layer and a gate electrode on the source electrode and the drain electrode; and using the gate electrode as a hard mask, and utilizing an etching technology for patterning the first insulation layer and the organic semiconductor layer one by one. The top-gate type thin-film transistor which is manufactured by the above method and using the gate electrode as a hard mask for sequentially patterning the first insulation layer and the organic semiconductor layer is simple in the manufacturing process, and can prevent the organic semiconductor layer from damaging.Type: ApplicationFiled: October 22, 2015Publication date: April 13, 2017Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventors: Chang-i SU, Hongyuan XU
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Publication number: 20170104034Abstract: A display device includes a first substrate provided with at least one color filter layer that transmits light of a certain wavelength, a second substrate that is disposed opposed to the first substrate; and a fill layer disposed between the first substrate and the second substrate. The first substrate is provided with a display region in which the at least one color filter layer is disposed and which displays an image and a peripheral region that is positioned out of the display region. Wettability of a surface of the at least one color filter layer of the peripheral region is equal to or less than wettability of a surface of the at least one color filter layer of the display region.Type: ApplicationFiled: September 26, 2016Publication date: April 13, 2017Applicant: Japan Display Inc.Inventors: Tetsuya NAGATA, Naoya KUBOTA
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Publication number: 20170104035Abstract: An organic light emitting device, an organic light emitting display device, and a method of manufacturing a sub-organic light emitting device, the device including a first sub-organic light emitting device; and a second sub-organic light emitting device on the first sub-organic light emitting device, wherein the first sub-organic light emitting device includes a first lower electrode, a first organic light emitting layer on the first lower electrode, and a first upper electrode on the first organic light emitting layer, and the second sub-organic light emitting device includes a second lower electrode insulated from the first lower electrode, a second organic light emitting layer on the second lower electrode and entirely overlapped with the first organic light emitting layer when viewed in a plan view, and a second upper electrode on the second organic light emitting layer.Type: ApplicationFiled: June 21, 2016Publication date: April 13, 2017Inventors: Hyesog LEE, Yunseon DO, Byungchoon YANG
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Publication number: 20170104036Abstract: A display device includes a plurality of pixel electrodes that correspond to the plurality of unit pixels, respectively, and are formed of a plurality of groups defined for the plurality of colors, a self-light emitting element layer, a common electrode, a plurality of optical path length adjusting layers, and a semi-light transmitting film that is laminated so as to be electrically connected to the common electrode and is conductive and has both of light transmission characteristics and light reflection characteristics. The plurality of optical path length adjusting layers having different thicknesses depending on which of the plurality of groups each of the plurality of optical path length adjusting layers belongs to. The display device having a microcavity structure formed such that light having a wavelength corresponding to each of the thicknesses resonates between corresponding one of the plurality of pixel electrodes and the semi-light transmitting film.Type: ApplicationFiled: September 26, 2016Publication date: April 13, 2017Applicant: Japan Display Inc.Inventor: Norihisa MAEDA
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Publication number: 20170104037Abstract: An organic light emitting diode (OLED) display includes a substrate, a first electrode disposed on the substrate, first organic emission layers disposed on the first electrode, second organic emission layers disposed on the first organic emission layers, a second electrode disposed on the second organic emission layer, and a color filter layer disposed on the second electrode. The first electrode includes a first sub-electrode, a second sub-electrode, a third sub-electrode, and a fourth sub-electrode spaced apart from each other. The first organic emission layers overlap the first, second, third, and fourth sub-electrodes, the second organic emission layers overlap the first, second, and third sub-electrodes, and the second electrode overlaps the first, second, third, and fourth sub-electrodes. The color filter layer includes sub-color filters.Type: ApplicationFiled: April 18, 2016Publication date: April 13, 2017Inventor: Dong Gyu KIM
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Publication number: 20170104038Abstract: An organic light emitting element including a first electrode; an auxiliary layer disposed on the first electrode; a yellow emission layer disposed on the auxiliary layer; and a second electrode disposed on the yellow emission layer, wherein a distance between the first electrode and the yellow emission layer is within one among a first range of 20 nanometers to 30 nanometers, a second range of 170 nanometers to 220 nanometers, and a third range of 280 nanometers to 380 nanometers.Type: ApplicationFiled: August 9, 2016Publication date: April 13, 2017Inventors: Chang-Min LEE, Beom Joon KIM, Hyun Ju CHOI
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Publication number: 20170104039Abstract: The present application discloses a display panel comprising a light emitting region comprising a plurality of light emitting units. Each of the plurality of light emitting units comprising a first sub-pixel comprising a first emissive layer of a first light emitting material for emitting light of a first color; a second sub-pixel comprising a second emissive layer of a second light emitting material for emitting light of a second color; and a third sub-pixel comprising a third emissive layer comprising the first light emitting material and the second light emitting material in vertical stack.Type: ApplicationFiled: December 10, 2015Publication date: April 13, 2017Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Jiuxia Yang, Jiantao Liu, Feng Bai
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Publication number: 20170104040Abstract: The present disclosure provides a pixel structure, a display panel, and a display apparatus. The pixel structure includes a plurality of pixel cells having a first pixel cell and a first adjacent pixel cell. Each pixel cell includes a first pixel; and two second pixels and two third pixels, surrounding the first pixel. Each of the two second pixels and the two third pixels is arranged separately in a direction along a side of a virtual rectangular area, the first pixel corresponding to one portion of the virtual rectangular area. Each of the two second pixels and the two third pixels has a first portion arranged in the first pixel cell covered by a first virtual rectangular area, and a second portion arranged in the first adjacent pixel cell covered by a second virtual rectangular area.Type: ApplicationFiled: December 10, 2015Publication date: April 13, 2017Inventors: LUJIANG HUANGFU, YINAN LIANG, TUO SUN, ZHANJIE MA
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Publication number: 20170104041Abstract: The present disclosure discloses a display device, a method of manufacturing the same, a display method, and a wearable device. The display includes a first base substrate; a low-temperature polysilicon (LTPS) back plate formed on the first base substrate and provided with a switch control circuit; and a micro-electro-mechanical system (MEMS) microlens array formed at a non-display region of the first base substrate, wherein the MEMS microlens array is configured to reflect light emitted by a light-emitting structure at the display region, and the switch control circuit is configured to control the MEMS microlens array to be turned on and off; and the light-emitting structure formed at the display region of the first base substrate.Type: ApplicationFiled: July 11, 2016Publication date: April 13, 2017Applicants: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zhidong WANG, Jing YU, Yue LONG
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Publication number: 20170104042Abstract: An organic light emitting diode display panel and a fabrication method thereof, a display device are provided, and the method includes: forming an anode layer (41) a light-emitting layer and a cathode layer on a substrate (40) and the method further includes: depositing a first pixel defining layer thin film (51) on the anode layer (41); depositing a second pixel defining layer thin film on the first pixel defining layer thin film (51), and forming a second pixel defining layer (61) by patterning the second pixel defining layer thin film through patterning process; and forming a first pixel defining layer (71) through dry etching and removing the first pixel defining layer thin film that is exposed; wherein the first pixel defining layer (71) has a lyophilic property and the second pixel defining layer (61) has a lyophobic property. A double-layer pixel defining layer prepared in the method is capable of reducing a mask plate, reducing the production cost, and improving the production efficiency.Type: ApplicationFiled: July 22, 2015Publication date: April 13, 2017Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Huifeng WANG, Ze LIU
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Publication number: 20170104043Abstract: The present application discloses an organic light emitting diode array substrate comprising a base substrate; a first electrode; a second electrode; and a pixel definition layer. The pixel definition layer comprises a first insulating layer comprising a plurality of first insulating units; a second insulating layer comprising a plurality of second insulating units; and a conductive layer comprising a plurality of interconnected conductive units sandwiched by the first insulating layer and the second insulating layer.Type: ApplicationFiled: December 10, 2015Publication date: April 13, 2017Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Jing Gao
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Publication number: 20170104044Abstract: The present application discloses a substrate comprising a via and a lyophobic protrusion layer comprising a plurality of protrusions spaced apart in the via, each of the plurality of protrusions protruding from a bottom surface of the via.Type: ApplicationFiled: December 28, 2015Publication date: April 13, 2017Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yingying Song, Li Sun
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Publication number: 20170104045Abstract: Provided is an organic EL device including a first substrate, a first organic EL element and a second organic EL element which is provided on the first substrate, a sealing layer which covers the first organic EL element and the second organic EL element, and a color filter which is provided on the sealing layer. The color filter includes a coloring layer overlapping the first organic EL element in a planar view, and a resin layer overlapping the second organic EL element in a planar view.Type: ApplicationFiled: July 22, 2016Publication date: April 13, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Yuki HANAMURA, Koya SHIRATORI, Takeshi KOSHIHARA
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Publication number: 20170104046Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate having a flexible portion configured to bend or fold, a semiconductor positioned over the substrate, and a gate insulating layer positioned over the semiconductor and having an opening. The display also includes an interlayer insulating layer positioned over the gate insulating layer, a portion of the interlayer insulating layer positioned within the opening. The display further includes a gate electrode positioned between the gate insulating layer and the interlayer insulating layer and overlapping the semiconductor in the depth dimension of the OLED display. A source electrode and a drain electrode are positioned over the interlayer insulating layer and connected to the semiconductor.Type: ApplicationFiled: September 2, 2016Publication date: April 13, 2017Inventors: Tae An Seo, Ju Chan Park, Jin Hwan Choi, Tae Woong Kim, Bo Ik Park, Young Gug Seol
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Publication number: 20170104047Abstract: It is an object of the invention to provide a technique to manufacture a display device with high image quality and high reliability at low cost with high yield. The invention has spacers over a pixel electrode layer in a pixel region and over an insulating layer functioning as a partition which covers the periphery of the pixel electrode layer. When forming a light emitting material over a pixel electrode layer, a mask for selective formation is supported by the spacers, thereby preventing the mask from contacting the pixel electrode layer due to a twist and deflection thereof. Accordingly, such damage as a crack by the mask does not occur in the pixel electrode layer. Thus, the pixel electrode layer does not have a defect in shapes, thereby a display device which performs a high resolution display with high reliability can be manufactured.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventor: Shunpei YAMAZAKI
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Publication number: 20170104048Abstract: A substrate structure may be used in a display device. The substrate structure may include a base substrate, a transistor, and a silicon oxynitride layer. The transistor may include a semiconductor member and a gate electrode and may overlap the base substrate. The silicon oxynitride layer may directly contact at least one of the base substrate, the semiconductor member, and the gate electrode and may include (and/or contain) a hydrogen atom set. A hydrogen concentration in the silicon oxynitride layer may be greater than or equal to 1.52 atomic percent.Type: ApplicationFiled: July 14, 2016Publication date: April 13, 2017Inventors: Yung-Bin CHUNG, Bo-Geon JEON, Eun-Jeong CHO, Hye-Hyang PARK, Sung-Hoon YANG, Woo-Seok JEON, Joo-Hee JEON, Chaun-Gi CHOI
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Publication number: 20170104049Abstract: A novel display device that is highly convenient with low power consumption is provided. The display device includes a display element including a liquid crystal layer, a display element including a light-emitting layer, and a pixel circuit. Electrodes of the display element including the liquid crystal layer and the display element including the light-emitting layer are electrically connected to the pixel circuit. The electrode of the display element including the liquid crystal layer includes a reflective film including an opening. The pixel circuit includes a transistor including a semiconductor film. The number of insulating films in a region overlapping with the opening is smaller than that of insulating films overlapping with the semiconductor film. In addition, the display element including the light-emitting layer includes two light-emitting elements.Type: ApplicationFiled: October 11, 2016Publication date: April 13, 2017Inventors: Daiki NAKAMURA, Kohei YOKOYAMA, Yasuhiro JINBO, Toshiki SASAKI, Masataka NAKADA, Naoto GOTO, Takahiro IGUCHI
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Publication number: 20170104050Abstract: The present invention provides a light-emitting device comprising a first light-emitting element that emits red light, a second light-emitting element that emits green light, a third light-emitting element that emits blue light, and a color filter, where the color filter comprises a first coloring layer that selectively transmits red light, a second coloring layer that selectively transmits green light, and a third coloring layer that selectively transmits blue light, the first to third light-emitting elements respectively correspond to the first to third coloring layers, wherein each of the first to third light-emitting elements has a first electrode, an electroluminescent layer on the first electrode, and a second electrode on the electroluminescent layer, and wherein the electroluminescent layer includes a layer in contact with the second electrode, and a metal oxide or a benzoxazole derivative is included in the layer in contact with the second electrode.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hisao IKEDA, Yasuo NAKAMURA, Keiko SAITO
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Publication number: 20170104051Abstract: The present disclosure provides an organic light-emitting diode (OLED) array substrate. The OLED array substrate includes a display area with OLEDs arranged in arrays, electrostatic discharge lines, and peripheral electrostatic discharge areas with conductive areas electrically connected to a cathode of the OLEDs and electrically connected to the electrostatic discharge lines through switch modules.Type: ApplicationFiled: September 17, 2015Publication date: April 13, 2017Inventors: CUILI GAI, ZHONGYUAN WU, LONGYAN WANG, XINGDONG LIU
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Publication number: 20170104052Abstract: The present application discloses a light emitting diode packaging structure comprising a base substrate; a metal lead on the base substrate; a cover plate; and a seal frame sealing the cover plate and the base substrate together and forming an enclosure surrounding a display area of the base substrate. The metal lead extends from the display area outwardly and passes through below the seal frame to outside of the enclosure. The metal lead has a curved configuration in plan view of the base substrate within a region where the metal lead overlaps with the seal frame.Type: ApplicationFiled: December 10, 2015Publication date: April 13, 2017Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Yi Li
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Publication number: 20170104053Abstract: A method of manufacturing an organic light emitting display device can include sequentially forming first and second metal films on a substrate, forming a gate electrode, a first storage electrode and a pad in a thin film transistor region, a storage capacitor region and a pad region, respectively, forming a gate insulation film forming a channel layer opposite to the gate electrode, forming an insulation film, forming an etch stopper on the channel layer and first through third contact holes exposing the gate electrode, the first storage electrode and the pad, forming source and drain electrodes, and a second storage electrode on the gate insulation film opposite to the first storage electrode, forming a third storage electrode overlapping the second storage electrode with a passivation film therebetween, forming color filters in respective pixel regions, and forming an organic light emitting diode electrically connected to the third storage electrode.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Applicant: LG Display Co., Ltd.Inventor: Yi Sik JANG
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Publication number: 20170104054Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal
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Publication number: 20170104055Abstract: A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor.Type: ApplicationFiled: October 12, 2015Publication date: April 13, 2017Inventors: Peter J. Zampardi, Brian Moser
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Publication number: 20170104056Abstract: Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.Type: ApplicationFiled: October 7, 2016Publication date: April 13, 2017Applicant: APPLIED MATERIALS, INC.Inventors: Guan Huei SEE, Chin Hock TOH, Glen T. MORI, Arvind SUNDARRAJAN
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Publication number: 20170104057Abstract: A capacitor 3D-cell formed on a silicon substrate is designed for producing low equivalent serial resistance and high capacitor surface-density. It combines a trench capacitor structure, multiple contact pads to at least one of the electrodes and a track which connects the electrode through the multiple contact pads so as to bypass said electrode between trench portions which are located apart from each other.Type: ApplicationFiled: July 13, 2016Publication date: April 13, 2017Inventor: Frédéric VOIRON
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Publication number: 20170104058Abstract: Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.Type: ApplicationFiled: October 8, 2015Publication date: April 13, 2017Inventors: Mattias Borg, Kirsten Moselund, Heinz Schmid, Heike Riel
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Publication number: 20170104059Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: Zailong Bian, Janos Fucsko
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Publication number: 20170104060Abstract: A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first thickness and a layer of SiGe having a second thickness. The second set of fins includes a second stack of layer pairs where at least one layer pair contains a layer of Si having the first thickness and a layer of SiGe having a third thickness greater than the second thickness. The method further includes removing the layers of SiGe from the first stack leaving first stacked Si nanowires spaced apart by a first distance and from the second stack leaving second stacked Si nanowires spaced apart by a second distance corresponding to the third thickness. The method further includes forming a first dielectric layer on the first nanowires and a second, thicker dielectric layer on the second nanowires.Type: ApplicationFiled: October 12, 2015Publication date: April 13, 2017Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Publication number: 20170104061Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.Type: ApplicationFiled: November 6, 2015Publication date: April 13, 2017Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
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Publication number: 20170104062Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.Type: ApplicationFiled: October 12, 2015Publication date: April 13, 2017Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Xin Miao
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Publication number: 20170104063Abstract: A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Naiqian ZHANG, Feihang LIU, Yi PEI
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Publication number: 20170104064Abstract: Nitride semiconductor devices having interdigitated array source and drain electrodes arranged like crossed fingers are described. The electric fields extended at the tips of the array electrodes are relaxed. Desirably, the rounded source electrode tip ends have a larger effective diameter than the rounded tip ends of the drain electrodes. Devices constructed accordingly have higher withstand voltages.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Hironori Aoki, Shuichi KANEKO
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Publication number: 20170104065Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.Type: ApplicationFiled: November 23, 2015Publication date: April 13, 2017Inventors: Kangguo Cheng, Robert H. Dennard, Zhen Zhang