Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at ?4 V reverse bias. 3-dB bandwidth is 30 GHz.

Abstract: A photovoltaic module generates electrical power when installed on a roof. The module is constructed as a laminated sandwich having a transparent protective upper layer adhered to a photovoltaic layer. The photovoltaic layer is adhered to the top of a rigid layer, preferably formed from a fiber reinforced plastic. A tapered edge seal is disposed about the peripheral outer edge of the module, so that water and debris easily run off. Preferably, the tapered edge seal is disposed adjacent the photovoltaic layer, and above the rigid substrate layer. The tapered edge seal is thinner at the outer peripheral portion thereof than at a portion thereof adjacent the photovoltaic layer. The laminated module preferably has a layer of double sided tape on the bottom to adhere the module to the surface of a roof.

Abstract: A PV module framing and coupling system which enables the attachment of PV modules to a roof or other mounting surface without requiring the use of separate structural support members which attach directly to and span between multiple PV modules in a formed PV array and a cable management system that holds, directs, organizes, and otherwise manages cables, wires, cord, and similar components of and relating to a PV array.

Abstract: A solar cell module is discussed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and a plurality of first electrodes and a plurality of second electrodes, which are formed on a back surface of the semiconductor substrate and are separated from each other, the plurality of solar cells disposed in a first direction; a plurality of first conductive lines connected to the plurality of first electrodes included in a first solar cell of the plurality of solar cells, and the plurality of first conductive lines extended in the first direction; a plurality of second conductive lines connected to the plurality of second electrodes included in a second solar cell of the plurality of solar cells which is adjacent to the first solar cell, and the plurality of second conductive lines extended in the first direction.

Abstract: A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells (1) are provided with a large size of e.g. 156×156 mm2. Soldering pad arrangements (13, 15) applied on emitter contacts (5) and base contacts (7) are provided with one or more soldering pads (9, 11) arranged linearly. The soldering pad arrangements (13, 15) are arranged asymmetrically with respect to a longitudinal axis (17). Each solar cell (1) is then separated into first and second cell portions (19, 21) along a line (23) perpendicular to the longitudinal axis (17).

Abstract: A light redirecting film defining a longitudinal axis, and including a base layer, an ordered arrangement of a plurality of microstructures, and a reflective layer. The microstructures project from the base layer, and each extends across the base layer to define a corresponding primary axis. The primary axis of at least one of the microstructures is oblique with respect to the longitudinal axis. The reflective layer is disposed over the microstructures opposite the base layer. When employed, for example, to cover portions of a PV module tabbing ribbon, or areas free of PV cells, the films of the present disclosure uniquely reflect incident light.

Abstract: A back contact back junction thin-film solar cell is formed on a thin-film semiconductor solar cell. Preferably the thin film semiconductor material comprises crystalline silicon. Base regions, emitter regions, and front surface field regions are formed through ion implantation and annealing processes.

Abstract: MOSFET phototransistors, methods of operating the MOSFET phototransistors and methods of making the MOSFET phototransistors are provided. The phototransistors have a buried electrode configuration, which makes it possible to irradiate the entire surface areas of the radiation-receiving surfaces of the phototransistors.

Abstract: Disclosed is a method for attaching an interconnector of a solar cell panel. The method includes forming a flux layer by spraying flux over the interconnector via spraying, the interconnector including a core layer and a solder layer formed on a surface of the core layer, and attaching the interconnector to a solar cell via soldering of the solder layer by pressing the interconnector onto the solar cell while applying heat.

Abstract: Disclosed is a solar cell including a substrate, an electrode layer disposed on the substrate, a p-type light-absorption layer disposed on the electrode layer, an n-type ZnS layer disposed on the p-type light-absorption layer, and a transparent electrode layer disposed on the n-type ZnS layer. The substrate can be immersed into an acidic solution of zinc salt, chelate, and thioacetamide, thereby forming the n-type ZnS layer on the substrate.

Abstract: Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one embodiment, a method for manufacturing a light emitting device includes forming a first semiconductor material, an active region, and a second semiconductor material on a substrate material in sequence, the active region being configured to produce a first emission. A conversion material is then formed on the second semiconductor material. The conversion material has a crystalline structure and is configured to produce a second emission. The method further includes adjusting a characteristic of the conversion material such that a combination of the first and second emission has a chromaticity at least approximating a target chromaticity of the light emitting device.

Abstract: A method of manufacturing ZnO-containing semiconductor structure includes steps of: (a) forming a subsidiary lamination, including alternately laminating at least two periods of active oxygen layers and ZnO-containing semiconductor layers doped with at least one species of group 3B element; (b) alternately laminating said subsidiary lamination and AgO layer, sandwiching an active oxygen layer, to form lamination structure; and (c) carrying out annealing in atmosphere in which active oxygen exists and pressure is below 10?2 Pa, intermittently irradiating oxygen radical beam on a surface of said lamination structure, forming a p-type ZnO-containing semiconductor structure co-doped with said group 3B element and Ag.

Abstract: A III-nitride semiconductor light emitting device incorporating n-type III-nitride cladding layers, indium containing III-nitride light emitting region, and p-type III-nitride cladding layers. The light emitting region is sandwiched between n- and p-type III-nitride cladding layers and includes multiple sets of multi-quantum-wells (MQWs). The first MQW set formed on the n-type cladding layer comprises relatively lower indium concentration. The second MQW set comprising relatively moderate indium concentration. The third MQW set adjacent to the p-type cladding layer incorporating relatively highest indium concentration of the three MQW sets and is capable of emitting amber-to-red light. The first two MQW sets are utilized as pre-strain layers. Between the MQW sets, intermediate strain compensation layers (ISCLs) are added. The combination of the first two MQW sets and ISCLs prevent phase separation and enhance indium uptake in the third MQW set.

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract: A lighting device according to embodiments of the invention includes a substrate with a plurality of holes that extend from a surface of the substrate. A non-III-nitride material is disposed within the plurality of holes. The surface of the substrate is free of the non-III-nitride material. A semiconductor structure is grown on the surface of the substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region.

Abstract: A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The set of large roughness components can include a series of truncated shapes. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

Abstract: A light emitting device includes a semiconductor light emitting element including a semiconductor stacked-layer body and an electrode disposed on a first surface of the semiconductor stacked-layer body; a resin member disposed on a first surface side of the semiconductor stacked-layer body; and a metal layer disposed in the resin member and electrically connected to the electrode. A recess is defined in an upper surface of the resin member. The metal layer is projected from the upper surface of the resin member, and is disposed to surround at least a portion of the recess.

Abstract: The present invention relates to a light-emitting diode (LED), which comprises electrodes having a single metal reflective layer. The single metal reflective layer is thicker than the active layer of the LED. Thereby, at least a portion of light emitted from the active layer is reflected by the single metal reflective layer, and thus enhancing the light-emitting efficiency of the LED.

Abstract: A mounting structure for mounting a set of optoelectronic devices is provided. A mounting structure for a set of optoelectronic devices can include: a body formed of an insulating material; and a heatsink element embedded within the body. A heatsink can be located adjacent to the mounting structure. The set of optoelectronic devices can be mounted on a side of the mounting structure opposite of the heatsink.

Abstract: Embodiments of a light emitting device and a method for fabricating the same are provided. The light emitting device comprises a cavity and one or more light emitting elements. The cavity is formed to a depth of 450 ?m or less, and the light emitting elements are installed in the cavity. A fabricating method includes forming a package body having a cavity with a depth of 250 ?m to 450 ?m and at least one lead frame disposed at the bottom surface of the cavity, mounting at least one light emitting element on the lead frame, and molding a molding member in the cavity.

Abstract: A method is provided for making optical semiconductor devices collectively. LED chips are arranged on a material substrate, and the substrate is sandwiched by a common mold and a first cooperating mold formed with a cavity. A light-transmitting resin is injected into the cavity and solidified to form a light-transmitting resin member including body portions for sealing the LED chips and connecting portions each connecting adjacent body portions. Then, the substrate is sandwiched by the common mold and a second cooperating mold formed with another cavity. A light-shielding resin is injected into the cavity and solidified to form a light-shielding resin member filling the gaps between the body portions. The body portions are separated from each other by making cuts in the material substrate and the light-shielding resin member.

Abstract: A solution for packaging an optoelectronic device using an ultraviolet transparent polymer is provided. The ultraviolet transparent polymer material can be placed adjacent to the optoelectronic device and/or a device package on which the optoelectronic device is mounted. Subsequently, the ultraviolet transparent polymer material can be processed to cause the ultraviolet transparent polymer material to adhere to the optoelectronic device and/or the device package. The ultraviolet transparent polymer can be adhered in a manner that protects the optoelectronic device from the ambient environment.

Abstract: Exemplary embodiments of the present invention provide a wafer-level light emitting diode (LED) package and a method of fabricating the same. The LED package includes a semiconductor stack including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a plurality of contact holes arranged in the second conductive type semiconductor layer and the active layer, the contact holes exposing the first conductive type semiconductor layer; a first bump arranged on a first side of the semiconductor stack, the first bump being electrically connected to the first conductive type semiconductor layer via the plurality of contact holes; a second bump arranged on the first side of the semiconductor stack, the second bump being electrically connected to the second conductive type semiconductor layer; and a protective insulation layer covering a sidewall of the semiconductor stack.

Abstract: A composite material, which can be used as an encapsulant for an ultraviolet device, is provided. The composite material includes a matrix material and at least one filler material incorporated in the matrix material that are both at least partially transparent to ultraviolet radiation of a target wavelength. The filler material includes microparticles and/or nanoparticles and can have a thermal coefficient of expansion significantly smaller than a thermal coefficient of expansion of the matrix material for relevant atmospheric conditions. The relevant atmospheric conditions can include a temperature and a pressure present during each of: a curing and a cool down process for fabrication of a device package including the composite material and normal operation of the ultraviolet device within the device package.

Abstract: Disclosed is a semiconductor light emitting device, including: a body, which has a bottom part with at least one hole formed therein, a side wall, and a cavity defined by the bottom part and the side wall; a semiconductor light emitting chip, which is placed in each hole and includes plural semiconductor layers adapted to generate light by electron-hole recombination and electrodes electrically connected to the plural semiconductor layers; and an encapsulating member provided at least to the cavity to cover the semiconductor light emitting chip, in which the electrodes of the semiconductor light emitting chip are exposed towards the lower face of the bottom part of the body.

Abstract: A light emitting device package including a package body including a recess which is provided with a bottom face and a plurality of inner walls surrounding the bottom face, the plurality of inner walls including a first inner wall and a second inner wall, which are opposing walls; a lead frame including a first portion disposed on the bottom face of the package body and at least one second portion extending from the first portion, the first portion including a planar upper surface exposed at the bottom face and a planar lowermost surface positioned opposite to the planar upper surface; a light emitting element provided on the planar upper surface of the first portion; and a transparent material provided in the recess of the package body to cover the light emitting element.

Abstract: Flexible LED assemblies (300) are described. More particularly, flexible LED (320) assemblies having flexible substrates (302) with conductive features (304, 306) positioned on or in the substrate, and layers of ceramic (310) positioned over exposed portions of the substrate to protect against UV degradation, as well as methods of making such assembles, are described.

Abstract: A thermoelectric conversion element includes: a first film including a perovskite structure; a second film and a third film, including a perovskite structure, disposed in such a manner that the first film is interposed between the second film and the third film; a fourth film, including a perovskite structure, disposed so as to interpose the second film with the first film; and a fifth film, including a perovskite structure, disposed so as to interpose the third film with the first film, wherein an offset in conduction band between the first film and the second film and an offset in conduction band between the first film and the third film is less than 0.25 eV, and an offset in conduction band between the second film and the fourth film and an offset in conduction band between the third film and the fifth film is more than 1 eV.

Abstract: A thermoelectric conversion element includes a p-type film having a perovskite structure, the p-type film including Co; an n-type film having a perovskite structure, the n-type film including Ti; first and second i-type films configured to be arranged to face each other across the n-type film, the first and second i-type films having a perovskite structure and including Ti; and a barrier film configured to be interposed between a multilayer body and the p-type film, the barrier film having a perovskite structure and including Zr, the multilayer body including the n-type film and the first and second i-type films.

Abstract: Provided herein are alloy systems with enhanced Seebeck coefficient and processes for making the same. An alloy system and process for improving the Seebeck coefficient of such an alloy system is disclosed. The process relates to an innovative methodology to preserve Te stoichiometry in electroplated thin films under annealing at high temperatures.

Abstract: The present invention provides a technology for preventing the generation of a pyrochlore phase, which is an impurity phase, in forming a PZT thin film by sputtering, without using a conventional seed layer. The present invention provides a PZT thin film laminate including: a Si substrate 10; a TiOx layer 4 serving as a platinum-adhesion layer on the Si substrate 10; a Pt electrode layer 5 on the TiOx layer 4; a Ti thin film layer 6 on the Pt electrode layer 5; and a PZT thin film layer 7 on the Ti thin film layer 6. The Ti thin film layer 6 can have a thickness of 1 nm or more and 10 nm or less.

Abstract: An ultrasonic transducer includes a backing element, an active element overlying the backing layer, and a matching element overlying the active element, the matching element having an inner surface that contacts the active element and an outer surface with a non-homogeneous texture and/or material composition. The matching element may be formed by subtractive or deposition techniques.

Abstract: An integrated circuit package including an integrated circuit die including a first side and a second side opposite the first side, the first side including at least one magnetoresistive device formed thereon. The integrated circuit package also may include a first magnetic shield disposed on or adjacent the first side of the integrated circuit die, wherein the first magnetic shield is formed of a composite material.

Abstract: Pure spin current devices are provided. The devices include sandwich structures of metal/magnetic insulator/metal. A first current injected in a first metal layer generates a pure spin current. The spin current can be switched between “on” and “off” states by controlling an in-plane magnetization orientation of the magnetic insulator. In the “on” state, the pure spin current is transmitted from the first metal layer to the second metal layer, through the magnetic insulator layer. The pure spin current in the second metal layer induces generation of a second charge current. In the “off” state, the pure spin current is absorbed at the interface between the first metal layer and the metal insulator. Such structures can serve as pure spin current valve devices or provide analog functionality, as rotating the in-plane magnetization provides analog sinusoidal modulation of the spin current.

Abstract: A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional MOSFETs. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (PMA) ferromagnets. Each stack includes two non-magnetic layers separating the easy-plane ferromagnetic film from the PMA layers. Charge current flow through one of these stacks controls the current-voltage negative differential resistance characteristics of the second stack through collective magnetic interactions. This can be exploited in a variety of digital logic gates consuming less energy than conventional CMOS integrated circuits.

Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract: A variable resistive memory device may include a phase change region, a phase change layer, a gap-filling layer and an upper electrode. The phase change region may have a sidewall and a bottom surface. The phase change layer may have a linear shape extended along the bottom surface and the sidewall of the phase change region. The gap-filling layer may be formed in a portion of the phase change region surrounded by the phase change layer. The upper electrode may be formed on the phase change layer and the gap-filling layer.

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract: An object is to provide a new fluorene derivative as a good light-emitting material for organic EL elements. A fluorene derivative represented by General Formula (G1) is provided. In the formula, R1 to R8 separately represent a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, a substituted or unsubstituted phenyl group, or a substituted or unsubstituted biphenyl group. Further, ?1 to ?4 separately represent a substituted or unsubstituted phenylene group. Ar1 represents a substituted or unsubstituted condensed aromatic hydrocarbon having 14 to 18 carbon atoms forming a ring. Ar2 represents a substituted or unsubstituted aryl group having 6 to 13 carbon atoms forming a ring. Ar3 represents an alkyl group having 1 to 6 carbon atoms or a substituted or unsubstituted aryl group having 6 to 12 carbon atoms. Further, j, m, and n separately represent 0 or 1, and p represents 1 or 2.

Abstract: A vapor deposition apparatus includes: a vapor deposition source having a plurality of vapor deposition source apertures that emit vapor deposition particles; a restriction plate unit having a plurality of restriction apertures; and a vapor deposition mask in which a plurality of mask apertures are formed only within a plurality of vapor deposition regions at which vapor deposition particles passing through the plurality of restriction apertures arrive.

Abstract: Systems and arrangements of OVJP deposition devices are provided, in which one or more organic material crucibles are directly attached to an injection block and a print head without the need for external delivery components such as feedtubes. Each crucible may be hermetically sealed until it is attached to the injection block, allowing for a single device to provide for storage, transport, and deposition of the organic material.

Abstract: The present teachings relate to new organic semiconducting compounds and their use as active materials in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The present compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors. The present compounds can have good solubility in common solvents enabling device fabrication via solution processes.

Abstract: A charge-transporting thin film, which enables the achievement of an organic EL element having excellent durability in cases where the charge-transporting thin film is applied to a hole injection layer of the element, is obtained using a charge-transporting varnish that contains a charge-transporting substance, a nonionic fluorine-containing surfactant and an organic solvent, and wherein the nonionic fluorine-containing surfactant has, for example, a perfluoroalkenyl group-containing perfluorohydrocarbon structure represented by one of formulae (1)-(3) and an alkylene oxide structure.

Abstract: The present disclosure relates to perylene-based molecules and their use in photoelectric conversion layer(s) and/or an organic or hybrid image sensor. The present disclosure also relates to absorption layer(s) and photoelectric conversion layer(s) comprising a molecule according to the present disclosure. The present disclosure also relates to a device, comprising a photoelectric conversion layer comprising at least one perylene-based molecule. Moreover, the present disclosure relates to an organic image sensor or a hybrid Silicon-organic image sensor comprising photoelectric conversion layer(s) according to the present disclosure.

Abstract: The present invention relates to: a composition for an organic optoelectric diode, containing a first host compound represented by Chemical Formula I and a second host compound represented by Chemical Formula II; an organic optoelectric diode comprising the composition for an organic optoelectric diode; and a display device.

Abstract: A fused polycyclic heteroaromatic compound is represented by one of Chemical Formula 1, 2A and 2B.

Abstract: The present invention relates to compounds of the formula (I), to the use of compounds of the formula (I) in electronic devices and electronic devices comprising one or more compounds of the formula (I). The invention furthermore relates to the preparation of the compounds of the formula (I) and to formulations comprising one or more compounds of the formula (I).