Abstract: In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example.

Abstract: The present disclosure relates to a solid-state image sensor and an electronic device enabling prevention of entrance of incident light from adjacent pixels and suppression of color mixture, decrease in resolution, and decrease in sensitivity. In a solid-state image sensor according to one aspect of the present disclosure, each pixel includes: these different photoelectric conversion parts configured to perform photoelectric conversion of light of a first wavelength of light of a second wavelength and a third wavelength respectively. An electrode wiring provided at a boundary of adjacent pixels, horizontally connects an electrode of at least one of the photoelectric conversion parts in one of the adjacent pixels with an electrode of the corresponding one of the photoelectric conversion parts in another of the adjacent pixels and vertically connects with an electrode of at least one of the photoelectric conversion parts of each of the pixels.

Abstract: The present invention proposes an image sensor, a monitoring system and a method for designing an image sensor, the image sensor including: a color filter, wherein, for light in infrared wavebands, the color filter only allows particular-wavelength infrared light to pass, and the color filter includes multiple n-color filters, wherein each filter corresponds to one color, the multiple n-color filters are used for dividing visible light in incident light into n-color light; and a light-sensitive chip, including a signal processing circuit and multiple light-sensitive units, the multiple light-sensitive units are respectively used for sensing intensity of light transmitting through the multiple n-color filters and generating electric signals corresponding to the light transmitting through the multiple n-color filters, the signal processing circuit is used for processing the electric signals for imaging, wherein a gain ratio of the signal processing circuit to the electric signals is A1: A2: . . . : Ai: . . .

Abstract: An aim of the present invention is to improve the conversion efficiency of scintillation light into electric charge by a photoelectric conversion element in an imaging panel of an X-ray imaging system using an indirection conversion scheme. An imaging panel generates images based on scintillation light acquired from X-rays that have passed through a specimen. The imaging panel includes a substrate, thin film transistor, photoelectric conversion element, and reflective layer. The thin film transistor is formed on the substrate. The photoelectric conversion element is connected to the thin film transistor and converts incident scintillation light into electric charge. The entirety of a region of a light-receiving surface of the photoelectric conversion element where the scintillation light is incident overlaps the reflective layer as seen from the incident direction of the scintillation light. The reflective layer may be the drain electrode.

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.

Abstract: A light-emitting diode package including a body and leads. The body comprising a mounting surface. The light emitting diode package also includes a light emitting diode chip including a substrate and a plurality of light emitting cells disposed on the substrate and positioned to be spaced apart from each other, each of the plurality of light emitting cells comprising an active layer disposed between a first conductive-type semiconductor layer and a second conductive-type semiconductor layer. The light emitting diode package also includes a phosphor member disposed on the light-emitting diode chip and a distributed Bragg reflector disposed on the substrate and between the plurality of light emitting cells.

Abstract: A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.

Abstract: A semiconductor device may include: a substrate; a first mold layer formed over the substrate and comprising a plurality of bottom conductive patterns connected to the substrate; a second mold layer formed over the first mold layer, and defining a plurality of hole openings, wherein each of the hole openings overlaps each of the bottom conductive patterns; a third mold layer formed over the second mold layer, and defining a plurality of line openings, wherein each of the line openings overlaps two or more hole openings of the hole openings; and a conductive material layer buried in the hole openings and the line openings.

Abstract: An MRAM device includes a lower electrode on a substrate, an MTJ structure on the lower electrode, a metal oxide pattern on the MTJ structure, a conductive pattern on at least a portion of a sidewall of the metal oxide pattern, and an upper electrode on the metal oxide pattern and the conductive pattern. The conductive pattern has a thickness varying along the sidewall of the metal oxide pattern in a plan view.

Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) layer over the bottom electrode, a top electrode over the MTJ layer, and a (N+1)th metal layer over the top electrode. The top electrode includes material having an oxidation rate lower than that of Tantalum or Tantalum derivatives. N is an integer greater than or equal to 1.

Abstract: A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.

Abstract: Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a cell structure includes a word line, a selector layer, and a memory layer. The word line, the selector layer, and the memory layer form a vertical cell structure in which at least one of the selector layer and the memory layer are segmented to form a segment that blocks sneak path leakage current on the word line.

Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

Abstract: A process for fabricating an organic x-ray detector is presented. The process includes forming a layered structure that includes disposing a first electrode layer on a thin film transistor array, disposing an organic photoactive layer on the first electrode layer and disposing a second electrode layer on the organic photoactive layer. The organic photoactive layer includes a fullerene or a fullerene derivative having a carbon cluster of at least 70 carbon atoms. The process further includes disposing a scintillator layer on the layered structure at a temperature greater than 50 degrees Celsius. An organic x-ray detector fabricated by the process is further presented. An x-ray system including the organic x-ray detector is also presented.

Abstract: The present invention discloses an OLED display panel, which is achieved by providing an electron cushion layer between the blue sub-pixel light emitting layer and the electron transport layer to prevent the accumulation of electrons on the interface of the emitting layer, thus the lifetime of the blue sub-pixel of the OLED panel and the phenomenon of offset of white chromaticity coordinate of the OLED display panel caused by excessive attenuation of luminance of the blue sub-pixel are improved, so that the lifetime of the OLED display panel is increased; further the present invention uses different materials of the electron transport layer for RGB sub-pixels, by virtue of selecting the material of the electron transport layer which is most favorable to the lifetime of RGB sub-pixels according to the material of each sub-pixel light emitting layer, to improve the lifetime of the blue sub-pixel of the OLED panel.

Abstract: A display unit includes a display region, a peripheral region, an insulating layer, a separating groove, and a sealing section. A plurality of pixels are disposed in the display region. The peripheral region is provided on outer edge side of the display region. The insulating layer extends from the display region to the peripheral region. The separating groove is provided in the peripheral region and separates the insulating layer into an inner peripheral portion and an outer peripheral portion. The sealing section is provided in the outer peripheral portion of the insulating layer and seals the display region. The separating groove has a width that is narrower as a distance is larger from an outer end of the display region to an outer end of the sealing section, and is wider as the distance is smaller.

Abstract: An organic light-emitting display including a substrate, an insulating layer on the substrate, the substrate and the insulating layer having an opening therethrough penetrating, a pixel array on the insulating layer, the pixel array including a plurality of pixels that surround the opening, a first pixel adjacent to the opening from among the plurality of pixels includes a pixel electrode layer, an intermediate layer on the pixel electrode layer, and an opposite electrode layer on the intermediate layer, and a stepped portion on the substrate and adjacent to the opening, the stepped portion having an under-cut step, wherein the intermediate layer including an organic emission layer, and wherein at least one of the intermediate layer and the opposite electrode layer extends toward the opening and is disconnected by the stepped portion.

Abstract: A bent part is prevented from being damaged by preventing displacement of a bend. A display device includes a circuit substrate having a flat part and a bent part, a light emitting element layer disposed on each of unit pixels forming an image, a circuit layer stacked on an outside surface of the bent part, a sealing layer that covers and seals the light emitting element layer, and a double-sided tape that includes a base material having a first surface and a second surface, respectively provided with a first adhesive and a second adhesive, and is bent at an inside of the bent part of the circuit substrate with the first surface being outside. The first surface sticks to the circuit substrate, and the second surface is folded back and adhered together.

Abstract: The present invention relates to an array substrate and a display device. The array substrate comprises a first thin film transistor arranged on a non-display area of the array substrate and a second thin film transistor arranged on a display area of the array substrate, a part of a first active layer corresponding to a region between a first source and a first drain in the first thin film transistor forms a first trench, and a part of a second active layer corresponding to a region between a second source and a second drain in the second thin film transistor forms a second trench, the first trench has at least one first bent portion, the second trench has a second bent portion, and bending angles of the first bent portion and the second bent portion are the same or explementary angles.

Abstract: A display device includes a substrate that is formed of a plurality of layers stacked together and a circuit layer. A circuit layer includes a display element area in which a plurality of pixel electrodes corresponding to a plurality of unit pixels and a self-luminous element layer are provided, and a peripheral area that has a wiring to the display element area and a terminal and is at least partially bent. The substrate includes a first area that overlaps the display element area of the circuit layer and a second area that overlaps the peripheral area and is at least partially bent. The layers include at least one inorganic layer and a plurality of organic layers. The number of the organic layers in the first area is greater than the number of the organic layers in the second area.

Abstract: An organic light emitting display device including a substrate, a first semiconductor element, a first lower electrode, a protection member, a first light emitting layer, a second lower electrode, and a second light emitting layer. The substrate has a first pixel region in which a light is emitted in a first direction, and a second pixel region in which a light is emitted in a second direction that is opposite to the first direction.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate having a main surface and a pixel provided over the main surface of the substrate and defined by a first region configured to display an image and a second region configured to transmit external light. The pixel includes a first electrode electrically provided in the first region, and a pixel defining layer provided in at least the first region, wherein the pixel defining layer has a first opening exposing a part of the first electrode and a second opening disposed in the second region. The pixel also includes a second electrode facing the first electrode and an intermediate layer disposed between the first and second electrodes and comprising an organic emission layer. The first capacitor at least partially overlaps the second opening along a direction perpendicular to the main surface.

Abstract: An array substrate, a display device, and a method for manufacturing the array substrate are disclosed. The array substrate comprises a base substrate, a light-absorbing layer, and a bottom-gate thin film transistor unit arranged in sequence, wherein a projection of the light-absorbing layer covers a gate metal layer, a source metal layer, and a drain metal layer of the bottom-gate thin film transistor unit. According to the present disclosure, the ambient light can be prevented from irradiating the metal layers of the bottom-gate thin film transistor unit effectively in the case that the brightness of the display panel is not reduced.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate, an interlayer insulating layer arranged over the substrate and an OLED arranged over the interlayer insulating layer. The OLED display also includes a source electrode and a drain electrode arranged over the interlayer insulating layer and a via layer arranged over the interlayer insulating layer and having a via hole exposing the source electrode or the drain electrode. The interlayer insulating layer includes a projecting portion which projects toward the OLED in the via hole.

Abstract: An array substrate, a method for fabricating the array substrate, and a related display device are provided. The array substrate comprises: a base substrate with a plurality of first via holes; a plurality of first signal lines on a first side of the base substrate; and a plurality of first signal driver lines on a second side of the base substrate; wherein each first signal line is connected with at least one first signal driver line through at least one first via hole.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the display includes a plurality of pixel electrodes positioned over a substrate and separate from each other, a plurality of auxiliary wirings between the pixel electrodes, a pixel-defining layer over the pixel electrodes except for a central portion of the pixel electrodes and at least a portion of each of the auxiliary wirings, an intermediate layer over the pixel-defining layer and having a plurality of openings formed over the portion of each of the auxiliary wirings, and an opposite electrode positioned over the intermediate layer and facing the pixel electrodes, the opposite electrode electrically contacting the auxiliary wirings via the openings. The auxiliary wirings extend in a first direction and separate from each other by a first distance. The openings are aligned in a diagonal direction crossing the first direction.

Abstract: Display of a display device is made less likely to appear divided when a plurality of display panels are used as one screen. Provided is a display device including two display units and a foldable housing that includes a joint portion between the two display units and supports the two display units. Each display unit includes a display panel including a display region and a non-display region and a support having a first surface overlapped with the display region and a second surface that meets the first surface and is overlapped with the non-display region. The two display units are placed in the housing in an opened state such that the first surfaces of the supports face the same direction and the second surfaces of the supports face each other.

Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.

Abstract: Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

Abstract: The disclosed technology relates to a metal-insulator-metal capacitor (MIMCAP) integrated as part of a back-end-of-line of an integrated circuit (IC). In one aspect, a MIMCAP comprises a first planar electrode having perforations formed therethrough, and a metal-insulator-metal (MIM) stack lining inner surfaces of cavities formed in the perforations and extending into the substrate. The MIMCAP additionally comprises a second electrode having a planar portion and metal extensions extending from the planar portion into the cavities. The first electrode and the planar portion of the second electrode are formed of or comprise planar metal areas of the respective metallization levels, which can be formed by a damascene process, which allows for a reduction of the series resistance. A low aspect ratio can be obtained using one electrode having a 3D-structure (the electrode having extensions extending into the cavities).

Abstract: A power semiconductor device includes a substrate, a main body, and an electrode unit. The main body includes an active portion disposed on the substrate, an edge termination portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes first-type semiconductor region, a second-type semiconductor region and a top surface. The first-type semiconductor region is adjacent to the active portion and has a first-type doping concentration decreased from the top surface toward the substrate. The electrode unit includes a first electrode disposed on the insulating layer, and a second electrode disposed on the substrate.

Abstract: A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.

Abstract: A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity; an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration; and an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.

Abstract: A semiconductor structure formed based on selectively recessing a middle-of-line (MOL) oxide layer of the semiconductor structure including multiple gate stacks formed on a substrate. A cap layer of the multiple gate stacks is selectively recessed. An air-gap oxide layer introducing one or more air-gaps is deposited. Chemical-mechanical planarization (CMP) is performed on the deposited air-gap oxide layer.

Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.

Abstract: A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

Abstract: A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper surface of the active fin. The source/drain includes a first crystal growth portion and a second crystal growth portion sharing a plane with the first crystal growth portion and having a lower surface disposed at a lower level than a lower surface of the first crystal growth portion.

Abstract: The present invention discloses a bi-mode insulated gate transistor, belonging to the technical filed of IGBTs. The bi-mode insulated gate transistor includes a reverse conducting region and a pilot region, wherein the reverse conducting region and the pilot region each include P+ collector regions, a drift region and a MOS cell region, the drift regions are disposed over the P+ collector regions, and the MOS cell regions are disposed over the drift regions; the reverse conducting region further includes N+ collector regions, and the N+ collector regions and the P+ collector regions are distributed alternatively; the pilot region further includes a separation region or a low-doped region, the separation region isolates the P+ collector regions of the pilot region from the P+ collector regions and the N+ collector regions of the reverse conducting region, and the low doped region is disposed over the P+ collector regions of the pilot region.

Abstract: A method includes forming fin semiconductor features on a substrate. A dopant-containing dielectric material layer is formed on sidewalls of the fin semiconductor features and the substrate. A precise material modification (PMM) process is performed to the dopant-containing dielectric material layer. The PMM process includes forming a first dielectric material layer over the dopant-containing dielectric material layer; performing a tilted ion implantation to the first dielectric material layer so that a top portion of the first dielectric material layer is doped to have a modified etch characteristic different from an etch characteristic of a bottom portion of the first dielectric material layer; and performing an etch process to selectively remove the top portion of the first dielectric material layer and the top portion of the dopant-containing dielectric material layer.

Abstract: A laminated body includes: a substrate portion composed of silicon carbide; and a graphene film disposed on a first main surface of the substrate portion, the graphene film having an atomic arrangement oriented with respect to an atomic arrangement of the silicon carbide of the substrate portion. A region in which a value of G?/G in Raman spectrometry is not less than 1.2 is not less than 10% in an area ratio in an exposed surface of the graphene film, the exposed surface being a main surface of the graphene film opposite to the substrate portion.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer.

Abstract: A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.

Abstract: The present application discloses a thin film transistor comprising active layer on a base substrate; an insulating layer over fee active layer, the insulating layer comprising a source via and a drain via, each of which extending through the insulating layer; a source electrode within the source via in contact with the active layer; and a drain electrode within the drain via in contact with the active layer.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Abstract: A method of manufacturing a semiconductor device includes forming a first trench in a semiconductor substrate from a first side, forming a semiconductor layer adjoining the semiconductor substrate at the first side, the semiconductor layer capping the first trench at the first side, and forming a contact at a second side of the semiconductor substrate opposite to the first side.

Abstract: A semiconductor device containing a metal-insulator-semiconductor (MIS) contact and method of forming are described. The method includes providing a semiconductor substrate containing a contact region, depositing an insulator film on the contact region, the insulator film including a mixed oxide material containing TiO2 and at least one additional metal oxide. The method further includes depositing a metal-containing electrode layer abutting the insulator film to form a MIS structure, and heat-treating the MIS structure to scavenge oxygen from the TiO2 to the metal-containing electrode layer to form a MIS contact with oxygen vacancies in the TiO2. According to one embodiment the at least one additional metal oxide is selected from HfO2, ZrO2, Al2O3, and combinations thereof, and the metal-containing electrode layer is selected from the group consisting of Ti metal, Al metal, Hf metal, Zr metal, Ta metal, Nb metal, and a combination thereof.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) power device with multi gates connection includes a first-conductive type substrate, a first-conductive type epitaxial layer arranged on the first-conductive type substrate, a plurality of device trenches defined on an upper face of the first-conductive type epitaxial layer. Each of the device trenches has, from bottom of the trench to top of the trench, a bottom gate, a split gate and a trench gate. A bottom insulating layer is formed between the bottom gate and the bottom of the trench, an intermediate insulating layer is formed between the bottom gate and the split gate, an upper insulating layer is formed between the split gate and the trench gate.