Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. The bottom surface of the dielectric layer is in contact with a lower layer of the integrated circuit device. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with the lower layer and a top surface. A tungsten nitride layer is disposed on the top surface of the tungsten via to repair etch damage done to the tungsten via.

Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage.

Abstract: A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a semiconductor package and a display apparatus which include the semiconductor chip are described. The semiconductor chip includes a circuit region disposed in a central part of a rectangle that is elongated in a first direction. The circuit region includes a plurality of driving circuit cells disposed at predetermined intervals in the first direction. A plurality of electrode pads is disposed around the circuit region, and a process pattern is disposed at at least one of the four sides of the rectangle.

Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.

Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

Abstract: Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

Abstract: A semiconductor device package includes a conductive base, and a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth. A semiconductor die is disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface. The second surface of the semiconductor die is bonded to the bottom surface of the cavity. A distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity.

Abstract: Methods for compensating for warpage in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming a buffer layer on the epitaxial layer and forming a compensating layer on the buffer layer; forming a buffer layer on the semiconductor substrate and forming a compensating layer on the buffer layer; and forming grooves in the epitaxial layer.

Abstract: Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.

Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.

Abstract: Described is an apparatus which comprises: a substrate; a plurality of holes formed as vias (e.g., through-silicon-vias (TSVs)) in the substrate; and a metal loop formed in a metal layer positioned above the plurality of holes such that a plane of the metal loop is orthogonal to the plurality of holes.

Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

Abstract: A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and a conductive structure. The isolation layer is located on the substrate. The redistribution layer is located on the isolation layer. The passivation layer is located on the isolation layer and the redistribution layer. The passivation layer has an opening, a wall surface that surrounds the opening, and a surface that faces away from the isolation layer. A portion of the redistribution layer is exposed through the opening. The first conductive layer is located on the redistribution layer that is in the opening, and extends to the wall surface and the surface of the passivation layer. The second conductive layer covers the first conductive layer. The conductive structure is located on the second conductive layer and protrudes from the passivation layer.

Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

Abstract: A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a first semiconductor workpiece; depositing a first film on a first surface of the semiconductor workpiece; depositing a second film on a substrate that is transmissive to light within a predetermined wavelength range; and bonding the first film to the second film under a predetermined bonding temperature and a predetennined bonding pressure.

Abstract: A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin.

Abstract: Exemplary embodiments of the invention include a method and apparatus for assembling a semiconductor device. The method may include heating the semiconductor device, which comprises a printed circuit card and a packaging laminate, according to a device heating profile to melt solder material located between an array of contact points on the printed circuit card and an array of corresponding contact points on the packaging laminate; and cooling the semiconductor device to solidify the solder material, wherein during at least a portion of the cooling a temperature of the printed circuit card is kept at substantially a same temperature or a higher temperature than a temperature of an electronic module attached to the packaging laminate opposite the corresponding array of contact points.

Abstract: A bonding apparatus 10 includes: a bonding head 18 configured to move a top camera 24 facing toward a bonding surface and a collet 22 disposed with an offset from the top camera 24, while integrally holding the top camera 24 and the collet 22; a bottom camera 28 facing toward the collet 22 so as to detect a position of a semiconductor chip 100 held by the collet 22 with respect to the collet 22; a reference mark 32 disposed within a view field of the bottom camera 28; and a control unit 40. The control unit 40 moves the bonding head 18 based on a position of the mark 32 recognized by the top camera 24, and then calculates a value of the offset based on a position of the collet 22 with respect to the mark 32 recognized by the bottom camera 28. With this, it is possible to provide a bonding apparatus capable of easily detecting an offset between a bonding tool and a position detection camera without providing a dedicated camera.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

Abstract: Disclosed are processes and apparatuses for semiconductor die removal and rework, including thin dies. In one aspect the process involves the use of a localized induction heating system to melt targeted solder joints, thereby minimizing the degradation of the thermal performance of the assembly undergoing the rework. Use of a vacuum-based die removal head, optionally in combination with the induction heating system, allows for the removal of thin dies of 150 micrometers thick or less.

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

Abstract: A microelectronic assembly includes a dielectric element having bumps projecting from a first surface thereof, the bumps having end surfaces flush with a planarized encapsulation. A circuit structure having a thickness less than or equal to 10 microns, formed by depositing two or more dielectric layers and conductive layers on the respective dielectric layers, has electrically conductive features thereon which electrically contact the bumps. The circuit structure can be formed separately on a carrier and then joined with the bumps on the dielectric element, or the circuit structure can be formed by a build up process on the planarized surface of the encapsulation and the planarized surfaces of the bumps.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending laterally beyond a respective edge of the first die. The package further includes a first Thermal Interface Material (TIM) over and contacting a top surface of the first die, a heat dissipating lid having a first bottom surface contacting the first TIM, a second TIM over and contacting the second portion of the second die, and a heat dissipating ring having a portion over and contacting the second TIM. The heat dissipating lid and the heat dissipating ring are discrete components, and at least one of the heat dissipating lid or the heat dissipating ring has a plurality of fins and a plurality of recesses separating the plurality of fins from each other.

Abstract: Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first package may include: a first encapsulant; a first via structure within the first encapsulant; a first die within the first encapsulant, at least a portion of the first encapsulant being interposed between a sidewall of the first die and a sidewall of the first via structure; a second die within the first encapsulant, an active side of the second die facing an active side of the first die; and a first via chip within the first encapsulant, the first via chip comprising one or more through vias, wherein the first via chip is disposed at the active side of the first die, and between the second die and the first via structure.

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Abstract: A semiconductor module includes upper arms and lower arms for three phases, heat sinks, a main circuit side bus bar, an output terminal side bus bar, a control terminal, and a resin mold portion. The output terminal side bus bar includes U-phase to W-phase wiring layers disposed opposite to each other via an insulating layer and U to W terminals electrically connecting each of the U-phase to W-phase wiring layer and a load. A stacked layer number of the U-phase to W-phase wiring layer is set to be an even number.

Abstract: A light source module includes a circuit board having a plurality of chip mounting regions, the plurality of chip mounting regions respectively having at least one connection pad; at least one alignment component respectively disposed on the plurality of chip mounting regions, and having a convex or concave shape; and a plurality of LED chips respectively mounted on the plurality of chip mounting regions, respectively having at least one electrode electrically connected to the at least one connection pad, and respectively coupled to the at least one alignment component.

Abstract: A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.

Abstract: Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.

Abstract: Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.

Abstract: Disclosed are an LED light emitting device and its manufacturing method. A blue LED chip specification is selected, a green phosphor and the blue LED chip are used to determine a green light frame on the CIE1931 chromaticity coordinates and a red phosphor together with a blue LED chip are used to determine a red light frame on the CIE1931 chromaticity coordinates, and a predetermined straight line passing through the color temperature target frame is selected, and both end points of the predetermined straight line fall within the green light frame and the red light frame, so as to determine the concentration of the green phosphor and the red phosphor, and the green and red phosphors and a blue LED chip are packaged to form a first LED and a second LED, and at least one first LED and at least one second LED are installed on a substrate.

Abstract: An LED lighting apparatus includes an LED substrate, a LED chip, a sealing resin member, and a reflecting face. The LED substrate has a main surface. The LED chip is mounted on the main surface of the LED substrate. The sealing resin member is made of a material that transmits light from the LED chip. The sealing resin member covers the LED chip. The sealing resin member has a shape bulging in the direction in which the main surface faces. The reflecting face surrounds the sealing resin member.

Abstract: The invention relates to an optoelectronic device (1) comprising light-emitting diodes produced in a material mostly comprising a same semiconductor compound and arranged such that: a plurality of N light-emitting diodes (40), N>2, are connected in series and capable of being forward-biased; at least one light-emitting diode (50) is connected in parallel to the plurality of the N light-emitting diodes (40), and capable of being reverse-biased thus forming a Zener diode; the number N of said light-emitting diodes (40) connected in series being adapted such that the sum of the N threshold voltages (Vs) is lower than the breakdown voltage (Vc) of the Zener diode.

Abstract: Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first die, and a redistribution structure on the first die and the first encapsulant. The second die is attached by an external electrical connector to the redistribution structure. The second die is on an opposite side of the redistribution structure from the first die. A second encapsulant is on the redistribution structure and at least laterally encapsulates the second die. The second encapsulant has a surface distal from the redistribution structure. A conductive feature extends from the redistribution structure through the second encapsulant to the surface of the second encapsulant. A conductive pillar is on the conductive feature, and the conductive pillar protrudes from the surface of the second encapsulant.

Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.

Abstract: Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver circuit. Further provided are a driver circuit provided with a protection circuit with low leakage current, and a method of manufacturing the driver circuit. By providing a protection circuit in a driver circuit to be electrically connected to a semiconductor element in the driver circuit, and by forming, at the same time, a transistor which serves as the semiconductor element in the driver circuit and a transistor included in the protection circuit in the driver circuit, damage of the semiconductor element due to ESD is suppressed in the process of manufacturing the driver circuit. Further, by using an oxide semiconductor film for the transistor included in the protection circuit in the driver circuit, leakage current in the protection circuit is reduced.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

Abstract: A semiconductor device includes a semiconductor substrate including, on a first surface, first trenches and a second trench linked to each of the first trenches. The semiconductor substrate includes: a p-type end layer extending from the first surface to a position closer to a second surface of the semiconductor substrate than an end of each of the first trenches on a second surface side and including a longitudinal end of each of the first trenches in a plan view of the first surface; a first p-type layer provided in a region between adjacent first trenches, and contacting the first electrode provided on the first surface; an n-type barrier layer; a second p-type layer. The second trench separates the p-type end layer from the first p-type layer and the second p-type layer.

Abstract: A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a hicher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.

Abstract: A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.

Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.

Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.