Abstract: This invention relates to a solar-cell module backing layer obtained by co-extruding obtained by melt co-extruding (i) a first polymer composition comprising (a) a polyamide, (b) an elastomer and (c) an elastomer that contains groups that bond chemically and/or interact physically with the polyamide, and wherein the first polymer composition comprises from 10 to 90 wt. % of the polyamide (a) and from 10 to 90 wt. % of the elastomer (b) and (c) (of the total weight of polyamide (a) and elastomer (b) and (c) present in the first polymer composition) and (ii) a second polymer composition comprising from 50-98 wt. % of elastomer and from 0.15-5 wt. % of groups (based on the total weight of the second polymer composition) that bond chemically and/or interact physically with the solar cell and optionally with the first polymer composition.

Abstract: Embodiments include an exemplary method for manufacturing a solar cell module that includes: a front surface-side transparent protective member having a curved shape; a back surface-side protective member having a curved shape corresponding to the curved shape of the front surface-side transparent protective member; and a filler layer disposed between the front surface-side transparent protective member and the back surface-side protective member, and seals a solar cell inside. The exemplary method may comprise: preparing the front surface-side transparent protective member having the curved shape and the back surface-side protective member having the curved shape; and manufacturing the solar cell module by disposing the solar cell and the filler layer between the front surface-side transparent protective member and the back surface-side protective member, and by pressing the front surface-side transparent protective member, the back surface-side protective member, the solar cell, and the filler layer.

Abstract: A solar panel (1) includes: a plurality of semiconductor substrate based solar cells (2), a transparent front side plate (4), and a rear side plate (6). The transparent front side plate (4) is stacked on top of the rear side plate (6) and the plurality of solar cells (2) are arranged in an array in between the rear side (6) plate and the front side plate (4). Each solar cell (2) has a light receiving surface facing (8) towards the front side plate (4); the solar cells (2) being embedded in an encapsulant layer (10) between the front side plate (4) and the rear side plate (6), wherein the solar panel includes an internal light redirection unit (12; 20) for guiding light received on the solar panel (1) but not captured by the solar cells (2), towards the solar cells (2).

Abstract: One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

Abstract: A method of forming a fired multilayer stack are described. The method involves the steps of a) applying a wet metal particle layer on at least a portion of a surface of a substrate, b) drying the wet metal particle layer to form a dried metal particle layer, c) applying a wet intercalation layer directly on at least a portion of the dried metal particle layer to form a multilayer stack, d) drying the multilayer stack, and e) co-firing the multilayer stack to form the fired multilayer stack. The intercalating layer may include one or more of low temperature base metal particles, crystalline metal oxide particles, and glass frit particles. The wet metal particle layer may include aluminum, copper, iron, nickel, molybdenum, tungsten, tantalum, titanium, steel or combinations thereof.

Abstract: A method for manufacturing a light emitting element includes: a GaN layer is formed on an AlN-deposited plain or patterned substrate, and the stress between different materials is changed and buffered through thermal treatment of annealing under H2 atmosphere or under H2 and NH3 mixed atmosphere, thus eliminating epitaxial wafer warp caused by such stress and improving epitaxial quality and light-emitting efficiency of the light-emitting element.

Abstract: In one embodiment, a light emitting device comprises a first light emitting part including at least one light emitting cell; a second light emitting part including a plurality of light emitting cells, wherein each of the light emitting cells include a light emitting structure and a first electrode layer disposed under the light emitting structure; a plurality of pads disposed on the light emitting cell of the first light emitting part, wherein the pads are electrically connected to each of the light emitting cells of the first and second light emitting parts; a plurality of connection layers, each connection layer extending from a region under the light emitting cell of the first light emitting part to a region under the plurality of light emitting cells of the second light emitting part; a second electrode layer disposed under the light emitting cells of the first and second light emitting parts; an insulating layer disposed between the first and second electrode layers; and at least one gap part disposed be

Abstract: Provided are a light emitting device having a nitride quantum dot and a method of manufacturing the same. The light emitting device may include: a substrate; a nitride-based buffer layer arranged on the substrate; a plurality of nanorod layers arranged on the nitride-based buffer layer in a vertical direction and spaced apart from each other; a nitride quantum dot arranged on each of the plurality of nanorod layers; and a top contact layer covering the plurality of nanorod layers and the nitride quantum dots. A pyramid-shaped material layer may be further included between each of the plurality of nanorod layers and each of the nitride quantum dots. One or the plurality of nitride quantum dots may be arranged on each of the nanorod layers.

Abstract: A nitride light emitting diode includes: an n-type nitride layer, a light emitting layer and a p-type nitride layer in sequence, wherein, the light emitting layer is a MQW structure composed of a barrier layer and a well layer, in which, an AlGaN electron tunneling layer is inserted into at least one well layer closing to the n-type nitride layer with barrier height greater than that of the barrier layer; in addition, the barriers of the AlGaN electron tunneling layer and the well layer are high enough so that electrons are difficult to transit towards thermionic emission direction, but mainly transit through tunneling in the InGaN well layers, which confines electron mobility and adjusts electron distribution. Hence, electrons have less chance to spill over into the P-type nitride layer.

Abstract: A nitride light-emitting diode (LED) structure includes a substrate, a buffer layer, an N-type layer, a stress release layer, a quantum well light-emitting layer and a P-type layer, wherein, between the N-type layer and the stress release layer, an electric field distribution layer is inserted, which is an n-doped multi-layer GaN structure with growth temperature equaling to or lower than that of the quantum well light-emitting layer; and GaN layers of different doping concentrations are applied to gradually reduce electric field concentration and make uniform spreading of current, thus enhancing electrostatic voltage endurance, reducing failure rate during usage, improving operational reliability and extending service life of the nitride semiconductor component.

Abstract: An optoelectronic device including a substrate having a surface, openings which extend in the substrate from the surface, and semiconductor elements, each semiconductor element partially extending into one of the openings and partially outside said opening, the height of each opening being at least 25 nm and at most 5 ?m and the ratio of the height to the smallest diameter of each opening being at least 0.5 and at most 15.

Abstract: An epitaxial structure includes a substrate, a first epitaxial layer and a second epitaxial layer. The substrate has a surface, and the first epitaxial layer is disposed over the substrate and defines a plurality of stepped air voids and an opening over each of the stepped air voids. The second epitaxial layer is disposed on the first epitaxial layer and collectively defines the stepped air voids with the first epitaxial layer.

Abstract: A thin-film flip-chip light emitting diode (LED) having a roughened surface and a method for manufacturing the same are provided. First, a substrate having a patterned structure on a surface of the substrate is provided, and the surface is roughened. A first semiconductor layer is then formed on the surface; a light emitting structure layer is then formed on the first semiconductor layer; a second semiconductor layer is then formed on the light emitting structure layer. The first and second semiconductor layers possess opposite electrical characteristics. A first contact electrode and a second contact electrode are then formed on the first semiconductor layer and the second semiconductor layer, respectively. Finally, a sub-mount is formed on the first and second contact electrodes, and the substrate is removed to form the thin-film flip-chip LED having the roughened surface. Here, the light emitting efficiency of the thin-film flip-chip LED is improved.

Abstract: An opto-electronic element according to an exemplary embodiment of the present disclosure includes a transparent conductive layer including a first material made of a metal and a second material made of a metal halide.

Abstract: A light emitting device including a light emitting structure disposed on one surface of a substrate and a transflective portion disposed on the other surface of the substrate. The transflective portion and the substrate have different indexes of refraction from one another.

Abstract: The method of a wafer level packaging includes preparing a substrate, assembling a system on a first side of the substrate, and placing solder balls on a second side of the substrate. The soldering balls s fixed on to the second side of the substrate after the module has been assembled.

Abstract: A light emitting layer including a plurality of light emitting particles embedded within a host matrix material. Each of said light emitting particles includes a population of semiconductor nanoparticles embedded within a polymeric encapsulation medium. A method of fabricating a light emitting layer comprising a plurality of light emitting particles embedded within a host matrix material, each of said light emitting particles comprising a population of semiconductor nanoparticles embedded within a polymeric encapsulation medium. The method comprises providing a dispersion containing said light emitting particles, depositing said dispersion to form a film, and processing said film to produce said light emitting layer.

Abstract: A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.

Abstract: A light emitting device includes a light emitting device on a substrate; an encapsulation layer covering the light emitting device; and a texture layer on the encapsulation layer. A surface of the texture layer has a ridge structure. A radial cross section of the ridge structure has a triangular shape with a distal vertex relative to the encapsulation layer surface. The distal vertex has one or more altitude angles, and the one or more altitude angles are less than or equal to 40 degrees.

Abstract: An optoelectronic component includes a housing, wherein a cavity is formed on an upper side of the housing, which is delimited by a wall, the housing has an empty space, the wall is arranged between the cavity and the empty space, the housing has a surface, the empty space is arranged between the surface of the housing and the wall, the wall and the surface are arranged at least partially parallel to each other, the wall includes an optically transparent material, and the wall has a wall thickness of 1 ?m to 100 ?m.

Abstract: An optoelectronic device including a semiconductor substrate having a face, light-emitting diodes arranged on the face and including wired conical or frustoconical semiconductor elements, and an at least partially transparent dielectric layer covering the light-emitting diodes, the refractive index of the dielectric layer being between 1.6 et 1.8.

Abstract: A light emitting diode (LED) package includes a light element, a light transferring layer disposed on the light element, a packaging layer enclosing the light transferring layer, a white wall surrounding the packaging layer and a diffusion film disposed on the packaging layer. The light transferring layer has a light outlet face, a light inlet face opposite to the light outlet face and a peripheral side. The light inlet face faces the light element. The white wall surrounds the peripheral side that is enclosed by the packaging layer.

Abstract: A light emitting diode chip includes a semiconductor layer sequence having an active layer that generates electromagnetic radiation, wherein the light emitting diode chip has a radiation exit area at a front side and a mirror layer at least in regions at a rear side situated opposite the radiation exit area, a protective layer is arranged on the mirror layer, the protective layer includes a transparent conductive oxide, the mirror layer adjoins the semiconductor layer sequence at an interface situated opposite the protective layer, first and second layers, the first and second electrical connection layers face the rear side of the semiconductor layer sequence and are electrically insulated from one another, and a partial region of the second electrical connection layer extends from the rear side of the semiconductor layer sequence through at least one perforation of the active layer in a direction toward the front side.

Abstract: Provided is a bonding wire for a semiconductor package and a semiconductor package including the same. The bonding wire for the semiconductor package may include a core portion including silver (Ag), and a shell layer surrounding the core portion, having a thickness of 2 nm to 23 nm, and including gold (Au). The semiconductor package may include a package body having a first electrode structure and a second electrode structure, a semiconductor light emitting device comprising a first electrode portion and a second electrode portion electrically connected to the first electrode structure and the second electrode structure, and a bonding wire connecting at least one of the first electrode structure and the second electrode structure to the semiconductor light emitting device.

Abstract: A light-emitting assembly includes a first substrate, a first electrode layer, a light-emitting layer, a second electrode layer, a second substrate, a first conductive member and a second conductive member. The first electrode layer, the light-emitting layer and the second electrode layer are sequentially disposed on the first substrate. An area of the second electrode layer is entirely located within an area of the light emitting layer. The second electrode layer is located between the second substrate and the light-emitting layer. The first and second conductive members are disposed between the first and second substrates. The first electrode layer is electrically connected to a first circuit on the second substrate through the first conductive member. The second electrode layer is electrically connected to a second circuit on the second substrate through the second conductive member. The second conductive member is located within the area of the second electrode layer.

Abstract: Object: To provide a light emitting element mounting substrate capable of exhibiting high brightness and high light emission efficiency over an extended period of time, and a light emitting device constituted by mounting a light emitting element on this light emitting element mounting substrate. Resolution means: A light emitting element mounting substrate, including a substrate made from a ceramic; a metal layer provided on the substrate that includes gold or silver as a primary component; and a resin layer provided covering at least a portion of the metal layer. The resin layer includes platinum, and at least one type of oxide of magnesium, calcium, and copper is present on a surface of the metal layer.

Abstract: A surface-mountable semiconductor component and a method for producing the same are disclosed. In an embodiment the component includes an optoelectronic semiconductor chip, first and second contact elements and a molded body, wherein the chip includes a semiconductor body having a semiconductor layer sequence with an active region provided for producing and/or receiving electromagnetic radiation and arranged between a first semiconductor layer and a second semiconductor layer, wherein the first contact elements are electrically conductively connected to the first semiconductor layer and the second contact elements are electrically conductively connected to the second semiconductor layer, wherein the molded body at least partially encloses the optoelectronic semiconductor chip, wherein the semiconductor component includes a mounting face formed by a surface of the molded body, and wherein the first and second contact elements protrudes through the molded body in a region of the mounting face.

Abstract: Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.

Abstract: Disclosed herein is a light emitting device. The light emitting device is provided to include a light emitting structure, a first electrode pad, a second electrode pad and a heat dissipation pad, and a substrate on which the light emitting diode is mounted. The substrate includes a base; an insulation pattern formed on the base; and a conductive pattern disposed on the insulation pattern. The base includes a post and a groove separating the post from the conductive pattern. An upper surface of the post is placed lower than an upper surface of the conductive pattern, the heat dissipation pad contacts the upper surface of the post, and the first electrode pad and the second electrode pad contact the conductive pattern. With this structure, the light emitting device has excellent properties in terms of electrical stability and heat dissipation efficiency.

Abstract: A method of fabricating and using of flexible elastic photo-thermoelectric or thermoelectric cells is being presented, where the thermoelectric materials have been used in nanohybrid (pristine form). The casing of the cells is made up of flexible elastic materials (plastic, rubber). The casing may have different shapes as rod, semi-circular, wave-form, spiral etc., that makes them easy for practical applications and the thermoelectric cells can potentially provide high efficiency. The flexible thermoelectric cells based on carbon nano-tubes (CNT) and its blend with cobalt oxide/graphene oxide nanohybrid have been made and tested.

Abstract: Embodiments of the invention are directed to conducting polymers are used to produce polymer composites through the addition of graphitic carbon. The concentration of graphitic carbons such as carbon nanotubes is low enough to produce many non-percolated networks of graphitic carbons. Potential commercial applications include self-powered energy harvesting units operated by any type and grade heat including body heat and waste heat. Embodiments of the invention are also directed to a process for a thermoelectric nanocomposite thin film comprising organic conducting polymers and organic conducting nanomaterials.

Abstract: A thermoelectric conversion device includes at least one thermoelectric conversion unit. The thermoelectric conversion unit includes at least one first electrode, at least one second electrode, a P-type thermoelectric material, and an N-type thermoelectric material. The first electrode includes a first fluid channel, such that the first electrode has a first hollow structure. The second electrode includes a second fluid channel, such that the second electrode has a second hollow structure. The P-type thermoelectric material is located between the first electrode and the second electrode, and the second electrode is located between the P-type thermoelectric material and the N-type thermoelectric material.

Abstract: In some aspects, a quantum information processing circuit includes a lumped-element device on the surface of a dielectric substrate. The lumped-element device can include a capacitor pad and an inductive transmission line. The capacitor pad can be capacitively coupled to another capacitor pad. The inductive transmission line can reside in an interior clearance area defined by an inner boundary of the capacitor pad. The lumped-element device can be, for example, a resonator device or a filter device. The inductive transmission line can be, for example, a meander inductor.

Abstract: A power generating device is provided. The power generating device includes an element having flexibility and a support to support at least one portion of the element. The element is capable of undergoing a deformation when receiving a vibration and capable of generating power when undergoing the deformation. The deformation includes at least one of a bending deformation, a torsional deformation, and a bending-torsional complex deformation.

Abstract: A piezoelectric element in which a first electrode, a piezoelectric body layer comprised of a composite oxide having a perovskite structure that includes at least Pb, Nb and Ti, and a second electrode are sequentially laminated on a substrate, in which a crystal that configures the piezoelectric body layer has a tetragonal structure, and the crystal is {100} oriented to the substrate, and in which a region having a (100) plane and a region having a (001) plane that are perpendicular with respect to a direction of lamination, are mixed inside a lattice of the crystal.

Abstract: A multi-layered film includes an electroconductive layer made of platinum (Pt), a seed layer including lanthanum (La), nickel (Ni), and oxygen (O), and a dielectric layer being preferentially oriented in a c-axis direction, which are at least sequentially disposed on a main surface of a substrate made of silicon.

Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

Abstract: A seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a seed layer such as Mg where the seed layer has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed layer is a template layer that is NiCr or NiFeCr. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited. The seed layer stack may include a bottommost Ta or TaN buffer layer.

Abstract: A magnetic memory cell includes: a first spin-orbit interaction active layer; a first magnetic free layer on the first spin-orbit interaction active layer, the first magnetic free layer having a changeable magnetization; a first nonmagnetic spacer layer on the first magnetic free layer; a reference layer having a fixed magnetization on the first nonmagnetic spacer layer; a second nonmagnetic spacer layer on the reference layer; a second magnetic free layer on the second nonmagnetic spacer layer, the second magnetic free layer having a changeable magnetization; and a second spin-orbit interaction active layer on the second magnetic free layer.

Abstract: A composition for cleaning a magnetic pattern, a method of manufacturing a magnetic memory device, a method of forming a magnetic pattern, and a magnetic memory device, the composition including a glycol ether-based organic solvent; a decomposing agent that includes an aliphatic amine; and at least one of a chelating agent, or a cleaning accelerator that includes an organic alkaline compound, wherein the composition is devoid of water.

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.

Abstract: In one embodiment, a method of forming a current sensor device includes forming a device region comprising a magnetic sensor within and/or over a semiconductor substrate. The device region is formed adjacent a front side of the semiconductor substrate. The back side of the semiconductor substrate is attached over an insulating substrate, where the back side is opposite the front side. Sidewalls of the semiconductor substrate are exposed by dicing the semiconductor substrate from the front side without completely dicing the insulating substrate. An isolation liner is formed over all of the exposed sidewalls of the semiconductor substrate. The isolation liner and the insulating substrate include a different material. The method further includes separating the insulating substrate to form diced chips, removing at least a portion of the isolation liner from over a top surface of the device region, and forming contacts over the top surface of the device region.

Abstract: Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.

Abstract: A threshold switching device includes a first electrode layer, a second electrode layer, and an insulating layer interposed between the first and second electrode layers and including a plurality of neutral defects. The threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

Abstract: A resistive memory element is provided having a layer structure. The layer structure includes two layers forming two electrically conductive electrodes, respectively, a resistively switchable material sandwiched between the two layers forming the two electrodes, and in electrical connection therewith, and a confining material. The resistively switchable material is laterally confined within the confining material, between the two layers forming the electrodes. The confining material is sufficiently electrically insulating for an electric signal applied between the two conductive electrodes to change a resistance state of the memory element in operation. The confining material has a thermal conductivity greater than 0.5 W/(m·K), and preferably greater than or equal to 30 W/(m·K). The resistively switchable material is an amorphous compound comprising carbon, which has a maximal lateral dimension, along a direction parallel to an average plane of the two layers forming the electrodes, that is less than 60 nm.

Abstract: A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.

Abstract: A method for fabricating a semiconductor apparatus includes providing a semiconductor substrate, stacking a conductive layer, a variable resistance layer, and a sacrificial layer on the semiconductor substrate, etching the conductive layer, the variable resistance layer, and the sacrificial layer to form a pillar structure including a lower electrode, a variable resistor device, and a sacrificial layer pattern, removing the sacrificial layer pattern, and forming an upper electrode over the variable resistor device in a hole which is formed by removing the sacrificial layer pattern.

Abstract: The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.

Abstract: This invention discloses metal complexes containing carborane moiety. The metal complexes showed desired properties in term of EQE, LT, and CIE.

Abstract: A vapor deposition mask capable of correctly performing confirmation of whether a shape pattern of openings formed in a resin mask is normal or similar confirmation while satisfying both high definition and lightweight, a vapor deposition mask preparation body for obtaining the vapor deposition mask, a frame-equipped vapor deposition mask including the vapor deposition mask, and a method for producing an organic semiconductor element using the frame-equipped vapor deposition mask. The aforementioned problem is solved by using, in a vapor deposition mask including a metal mask in which a slit is formed and a resin mask in which an opening corresponding to a pattern to be produced by vapor deposition is formed at a position overlapping with the slit, the metal mask and the resin mask being stacked, the resin mask which has about 40% or less of light ray transmittance at a wavelength of about 550 nm.