Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

Abstract: A semiconductor structure formed based on forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity. The first low-k spacer portion and the second low-k spacer portion are etched. A poly pull process is performed on the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.

Abstract: A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

Abstract: A method for producing a semiconductor device includes forming a first insulating film around a fin-shaped semiconductor layer and forming a pillar-shaped semiconductor layer and forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer. A metal-semiconductor compound is formed on the second diffusion layer. A first metal is deposited to form a gate electrode and a gate line. Second and third metal films are deposited to form a first contact in which the second metal film surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second contact connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer. A third contact is formed on the gate line.

Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region; a drain region aligned substantially vertically to the source region; a channel structure bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.

Abstract: A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a substrate. After formation of a first dielectric isolation layer around the patterned stack, a disposable gate structure can be formed. End portions of the second silicon-germanium alloy nanowire are removed to form first cavities underlying end portions of the silicon-containing nanowire. Dielectric nanowires are formed in cavities concurrently with formation of a gate spacer. After recessing the first dielectric isolation layer, a second cavity is formed by removing the first silicon-germanium alloy nanowire. The second cavity is filled with a second dielectric isolation layer, and raised active regions can be formed by a selective epitaxy process. After formation of a planarization dielectric layer, the disposable gate structure and the remaining portion of the second silicon-germanium alloy nanowire with a replacement gate structure.

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

Abstract: A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.

Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.

Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

Abstract: A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.

Abstract: The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

Abstract: The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.

Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.

Abstract: A semiconductor device includes a pillar-shaped semiconductor layer and a first gate insulating film around the pillar-shaped semiconductor layer. A metal gate electrode is around the first gate insulating film and a metal gate line is connected to the gate electrode. A second gate insulating film is around a sidewall of an upper portion of the pillar-shaped semiconductor layer and a first contact made of a second metal surrounds the second gate insulating film. An upper portion of the first contact is electrically connected to an upper portion of the pillar-shaped semiconductor layer, and a third contact resides on the metal gate line. A lower portion of the third contact is made of the second metal.

Abstract: A semiconductor device includes an active pattern having sidewalls defined by a device isolation pattern disposed on a substrate and an upper portion protruding from a top surface of the device isolation pattern, a liner insulating layer on the sidewalls of the active pattern, a gate structure on the active pattern, and source/drain regions at both sides of the gate structure. The liner insulating layer includes a first liner insulating layer and a second liner insulating layer having a top surface higher than a top surface of the first liner insulating layer. Each of the source/drain regions includes a first portion defined by the second liner insulating layer, and a second portion protruding upward from the second liner insulating layer and covering the top surface of the first liner insulating layer.

Abstract: A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate. The method further includes epitaxially growing a semiconductor material on the fin. The method further includes depositing oxide covering the fin and the epitaxially grown semiconductor material. The method further includes recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin. The method further includes removing the fin. In another embodiment, the method further includes epitaxially growing another fin in a respective trench formed by removing the first set of fins.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: The present disclosure generally relate to methods for forming an epitaxial layer on a semiconductor device, including a method of forming a tensile-stressed germanium arsenic layer. The method includes heating a substrate disposed within a processing chamber, wherein the substrate comprises silicon, and exposing a surface of the substrate to a germanium-containing gas and an arsenic-containing gas to form a germanium arsenic alloy having an arsenic concentration of 4.5×1020 atoms per cubic centimeter or greater on the surface.

Abstract: A semiconductor circuit element includes a first semiconductor device positioned in and above a first active region of a semiconductor substrate and a second semiconductor device positioned in and above a second active region of the semiconductor substrate. The first semiconductor device includes a first gate structure having a first gate dielectric layer that includes a first high-k material, and the second semiconductor device includes a second gate structure having a second gate dielectric layer that includes a ferroelectric material that is different from the first high-k material.

Abstract: A thin film transistor (TFT), a method for fabricating the TFT, and a display device are provided. The TFT comprises a first gate electrode and a second gate electrode; and an active layer located in between of the first gate electrode and the second gate electrode and being insulated from the first gate electrode and the second gate electrode; wherein the first gate electrode is connected with the second gate electrode through a via hole; and the first gate electrode is made of a light-shielding material for blocking light from irradiating on the active layer.

Abstract: The present invention proposes a TFT, an array substrate, and a method of forming a TFT. The TFT includes a substrate, a buffer layer, a patterned poly-si layer, an isolation layer, a gate layer, and a source/drain pattern layer. The poly-si layer includes a heavily doped source and a heavily doped drain, and a channel. The gate layer includes a first gate area and a second gate area. The source/drain pattern layer includes a source pattern, a drain pattern and a bridge pattern, with the source pattern electrically connecting the heavily doped source, the drain pattern electrically connecting the heavily doped drain, and one end of the bridge pattern connecting the first gate area and the second gate area. The driving ability of the present inventive TFT is enhanced without affecting the leakage current.

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

Abstract: A fin stack structure is provided on an insulator layer. The fin stack structure comprises, from bottom to top, a first semiconductor fin portion, a dielectric fin portion, a second semiconductor fin portion and a hard mask fin portion. A sacrificial gate structure is formed on a portion of the fin stack structure. The hard mask fin portion and the dielectric fin portion not located beneath the sacrificial gate structure are removed. An epitaxial semiconductor material structure is then formed from exposed surfaces of each semiconductor fin portion. The sacrificial gate structure is then removed. Next, remaining portions of the hard mask fin portion and the dielectric fin portion are removed. The insulating layer is then recessed. After recessing the insulator layer, the first and second semiconductor fin portions are suspended and are stacked one atop the other.

Abstract: A thin film transistor includes: a gate electrode; a gate insulating layer above the gate electrode; an oxide semiconductor layer disposed above the gate insulating layer; and a source electrode and a drain electrode disposed above the oxide semiconductor layer and electrically connected to the oxide semiconductor layer, wherein metallic elements included in the oxide semiconductor layer include at least indium (In), fluorine is included in a region which is an internal region in the oxide semiconductor layer and is close to the gate insulating layer, and a fluorine concentration of the region close to the gate insulating layer in the oxide semiconductor layer is higher than a fluorine of a contact region for the source electrode or the drain electrode in the oxide semiconductor layer.

Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

Abstract: A diode device and manufacturing method thereof are provided. The diode device includes a substrate, an epitaxial layer, a trench gate structure, a Schottky diode structure and a termination structure. An active region and a termination region are defined in the epitaxial layer. The Schottky diode structure and the trench gate structure are located in the active region and the termination structure is located in the termination region. The termination structure includes a termination trench formed in the epitaxial layer, a termination insulating layer, a first spacer, a second spacer and a first doped region. The termination insulating layer is conformingly formed on inner walls of the termination trench. The first and second spacers are disposed on two sidewalls of the termination trench. The first doped region formed beneath the termination trench has a conductive type reverse to that of the epitaxial layer.

Abstract: A Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer. In this case, the Schottky junction region and the LOCOS layer are in contact.

Abstract: A solar cell module includes: a solar cell group including a plurality of solar cell strings arranged in a second direction, the plurality of solar cell strings each including a plurality of solar cells arranged in a first direction; a terminal box that outputs power from the solar cell group out of the solar cell module; and an interconnect tab that connects the terminal box to a first end solar cell located at an end in the first direction in one of the plurality of solar cell strings that is located at an end in the second direction, and the interconnect tab does not overlap with the first end solar cell.

Abstract: An optoelectronic device having a textured layer is described. In an aspect, a method may be used to produce the optoelectronic device, where the method includes epitaxially growing a semiconductor layer of the optoelectronic device on a growth substrate, and exposing the semiconductor layer to an etching process to create at least one textured surface in the semiconductor layer. The textured semiconductor layer can be referred to as a textured layer. The etching process is performed without the use of a template layer, or similar layer, configured as a mask to generate the texturing. The etching process can be done by one or more of a liquid or solution-based chemical etchant, gas etching, laser etching, plasma etching, or ion etching. The method can also include lifting the semiconductor layer of the optoelectronic device from the growth substrate by, for example, the use of an epitaxial lift off (ELO) process.

Abstract: A method of manufacturing a transparent pane, in particular a glass pane, which includes on at least one of its main surfaces a surface structure including an assembly of specified individual motifs in relief, in particular pyramids, cones, or truncated cones, created by embossing or by rolling. A structure is created on the surface of the pane constituted by individual motifs, based on one or more basic motifs but which are distinguished from each other by their depth, their height, and/or the perimeter of their base area, and/or by the position of their peak with respect to their base. With this variation, formation of intensity peaks of the reflected light is prevented and at the same time a high quality of light trapping is obtained by panes suitable, for example, for solar applications.

Abstract: Provided in one embodiment is a method of making, comprising: exposing a raw material having a first viscosity to a first pressure and a first temperature such that the raw material after the exposure has a second viscosity, wherein the raw material comprises particles comprising at least one electrically conductive material, and wherein the second viscosity is sufficiently low for the raw material to be adapted for a hydrodynamic cavitation process; and subjecting the raw material having the second viscosity to the hydrodynamic cavitation process to make a product material having a third viscosity. Apparatus employed to apply the method and the exemplary compositions made in accordance with the method are also provided.

Abstract: Intercalation pastes for use with semiconductor devices are disclosed. The pastes contain precious metal particles, intercalating particles, and an organic vehicle and can be used to improve the material properties of metal particle layers. Specific formulations have been developed to be screen-printed directly onto a dried metal particle layer and fired to make a fired multilayer stack. The fired multilayer stack can be tailored to create a solderable surface, high mechanical strength, and low contact resistance. In some embodiments, the fired multilayer stack can etch through a dielectric layer to improve adhesion to a substrate. Such pastes can be used to increase the efficiency of silicon solar cells, specifically multi- and mono-crystalline silicon back-surface field (BSF), and passivated emitter and rear contact (PERC) photovoltaic cells. Other applications include integrated circuits and more broadly, electronic devices.

Abstract: A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a paste, a first metal, and a first conductive portion that includes a conductive alloy formed from the first metal at an interface of the substrate and the semiconductor region.

Abstract: In the solar cell module including a plurality of solar cells interconnected with wiring members, each of the solar cells includes a plurality of front-side finger electrodes that are disposed on a light-receiving surface of the solar cell and connected with tabs and a plurality of rear-side finger electrodes that are disposed on a rear surface of the solar cell and connected with tabs. Rear-side auxiliary electrode sections are arranged in regions, which is wider than the front-side finger electrodes, on the rear surface opposite to regions where the front-side finger electrodes are present.

Abstract: The invention discloses an all-aluminum back surface field aluminum paste for a crystalline silicon solar cell and a preparation method thereof. The all-aluminum back surface field paste mainly comprises 60-70% aluminum powder, 5-10% nanometer metal oily solution, 1-10% inorganic binder, 10-20% organic binder, 5-30% organic solvent and 1-5% accessory ingredient. According to the aluminum paste prepared by the present invention, the back surface preparing process of an all-aluminum back surface field can be implemented preferably; moreover, the paste has great adhesive force, is easy to be better adhered to silver paste printed afterwards; meanwhile, the paste can be in good contact with a silicon chip through the nanometer metal oily solution added into the paste, the aluminum back surface is prevented from falling off, and good ohm contact can be formed, so that the photoelectric conversion efficiency is increased, and the economic benefits of enterprises are increased.

Abstract: Intercalation pastes for use with semiconductor devices are disclosed. The pastes contain precious metal particles, intercalating particles, and an organic vehicle and can be used to improve the material properties of metal particle layers. Specific formulations have been developed to be screen-printed directly onto a dried metal particle layer and fired to make a fired multilayer stack. The fired multilayer stack can be tailored to create a solderable surface, high mechanical strength, and low contact resistance. In some embodiments, the fired multilayer stack can etch through a dielectric layer to improve adhesion to a substrate. Such pastes can be used to increase the efficiency of silicon solar cells, specifically multi- and mono-crystalline silicon back-surface field (BSF), and passivated emitter and rear contact (PERC) photovoltaic cells. Other applications include integrated circuits and more broadly, electronic devices.

Abstract: This disclosure provides systems, methods, and apparatus related to photodetectors. In one aspect, a photodetector device comprises a substrate, a polycrystalline layer disposed on the substrate, and a first electrode and a second electrode disposed on the polycrystalline layer. The polycrystalline layer comprises nanograins with grain boundaries between the nanograins. The nanograins comprise a semiconductor material. A doping element comprising a halogen is segregated at the grain boundaries. A length of the polycrystalline layer is between and separating the first electrode and the second electrode.

Abstract: The present invention relates to a substrate for a thin film photovoltaic module, characterized in that it is a cementitious product with average surface roughness Ra not higher than 500 nm. The invention also relates to the cementitious product as such, the thin film photovoltaic module comprising it, and a method of moulding both of them.