Abstract: A first plasmonic-nanostructure sensor pixel includes a semiconductor substrate and a plurality of metal pillars. The semiconductor substrate has a top surface and a photodiode region therebeneath. The plurality of metal pillars is at least partially embedded in the substrate and extends from the top surface in a direction substantially perpendicular to the top surface. A second plasmonic-nanostructure sensor pixel includes (a) a semiconductor substrate having a top surface, (b) an oxide layer on the top surface, (c) a thin-film coating between the top surface and the oxide layer, and (d) a plurality of metal nanoparticles (i) at least partially between the top surface and the oxide layer and (ii) at least partially embedded in at least one of the thin-film coating and the oxide layer. A third plasmonic-nanostructure sensor pixel includes features of both the first and second plasmonic-nanostructure sensor pixels.

Abstract: The present invention provides an image sensor. An image sensor include a pixel array. The pixel array includes: a plurality of pixels; and an isolation structure suitable for insulating between the plurality of pixels. The isolation structure includes: a first conductivity-type conductive layer formed over a substrate; and a second conductivity-type pickup region formed in the first conductivity-type conductive layer and disposed between each plurality of pixels.

Abstract: Curved, flexible arrays of radiation detectors are formed by using standard silicon semiconductor processing materials and techniques and additional functionalization through integration of conversion and shielding materials. The resulting flexible arrays can be handled, integrated, further functionalized and deployed for a wide variety of applications where conventional sensors do not provide the desired functionality, form factors and/or reliability. The arrays can be stacked and include multiple types and thicknesses of conversion layers, enabling the detector to simultaneously detect multiple radiation types, and perform complex, simultaneous functions such as energy discrimination, spectroscopy, directionality detection, and particle trajectory tracking of incident radiation.

Abstract: Methods for forming image sensor structures are provided. The method includes forming an isolation structure in a substrate and forming a first light sensing region and a second light sensing region. The method further includes forming a first gate structure and a second gate structure, and the first gate structure and the second gate structure are positioned at a front side of the substrate. The method further includes forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure and forming an interlayer dielectric layer over the front side of the substrate. The method further includes forming a contact trench through the interlayer dielectric layer and forming a contact in the contact trench.

Abstract: The present disclosure is to provide an optoelectronic device. The optoelectronic device comprises a heat dispersion substrate; a first connecting layer on the heat dispersion substrate; a diode stack structure comprising a protection layer and a second connecting layer on the protection layer, wherein the protection layer is on the first connecting layer; a light-emitting structure on the diode stack structure, wherein the light-emitting structure comprises a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a first electrode electrically connected to the diode stack structure and the light-emitting structure.

Abstract: A display device include a substrate including a wiring electrode; an adhesive layer disposed on the substrate; a plurality of semiconductor light emitting devices adhered to the adhesive layer, and electrically connected to the wiring electrode; and a phosphor layer disposed to cover the plurality of semiconductor light emitting devices. Further, the phosphor layer includes a plurality of phosphor portions for converting a wavelength of light, and a plurality of partition wall portions formed between the plurality of phosphor portions, and the plurality of partition wall portions are sequentially disposed between the phosphor portions along a first direction and a second direction crossing each other, respectively, and at least one of the sequentially disposed partition wall portions overlaps with at least one of the plurality of semiconductor light emitting devices.

Abstract: A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack structure includes alternating magnetic layers and diode structures formed on the substrate. Each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by a diode structure.

Abstract: There is provided a magnetic element including a reference layer made of a ferromagnetic material and having a fixed or pinned magnetization direction, a free layer made of a ferromagnetic material and having a switchable magnetization direction based spin transfer torque, and a spacer layer disposed between the reference layer and the free layer. In particular, the free layer includes a surface facing away from the spacer layer, and the magnetic element further includes a current confined layer disposed on the above-mentioned surface of the free layer. The current confined layer including at least one conductive channel extending through the current confined layer for concentrating current to flow through the at least one conductive channel. There is also provided a corresponding method of fabricating such a magnetic element and a magnetic memory device including an array of such magnetic elements.

Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes first and second conductive lines, and a variable resistance material and a switching element between the first and second conductive lines. The switching element includes first and second portions that extend and/or face in different first and second directions, respectively. Methods of manufacturing a variable resistance memory device are also provided.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: A tandem organic light-emitting diode, an array substrate and a display device are provided. The tandem organic light-emitting diode includes an anode, a hole transport layer, a first light-emitting layer, a first charge generation layer, a second charge generation layer, a third charge generation layer, a fourth charge generation layer, a second light-emitting layer, an electron transport layer and a cathode which are sequentially laminated, wherein the first charge generation layer is an N-type bulk heterojunction, the second charge generation layer and the third charge generation layer are both PN junction type bulk heterojunctions, a proportion of the P-type organic material in the second charge generation layer is greater than that of the N-type organic material, a proportion of the P-type organic material in the third charge generation layer is less than that of the N-type organic material, and the fourth charge generation layer is a P-type bulk heterojunction.

Abstract: A display apparatus includes a unit pixel comprising a red sub pixel, a green sub pixel, a first blue sub pixel, and a second blue sub pixel. Each of the sub pixels include a first electrode, an intermediate layer comprising an organic emission layer disposed on the first electrode, and a second electrode disposed on the intermediate layer. The first blue sub pixel includes a first intermediate layer including a first blue organic emission layer, the second blue sub pixel includes a second intermediate layer including a second blue organic emission layer, the green sub pixel includes a third intermediate layer including a green organic emission layer, and the red sub pixel includes a fourth intermediate layer including a red organic emission layer. The first intermediate layer and the second intermediate layer have different thicknesses, and the third intermediate layer and the fourth intermediate layer have different thicknesses.

Abstract: A substrate includes: a first panel region which includes a plurality of first cells disposed on the substrate which is a single substrate; a second panel region which includes a plurality of second cells disposed on the substrate and is different in size from the first panel region; a first dummy cell which has a same shape as a shape of the plurality of second cells and is disposed at a portion of an external surrounding area of the first panel region; and a second dummy cell which has a same shape as a shape of the plurality of first cells and is disposed at a portion of an external surrounding area of the second panel region.

Abstract: A method for manufacturing a display substrate, a display substrate and a display device are disclosed. The method includes: forming a thin-film transistor (TFT) array on a base substrate to form an array substrate; and forming a pixel define layer (PDL) on a non-pixel region of the array substrate by a patterning process. A photochromic material is uniformly distributed in the PDL; the PDL provided with the photochromic material can be converted from light-transmitting to light-shielding under action of light illumination; and the process that the PDL is converted from light-transmitting to light-shielding is irreversible.

Abstract: A display device may include a light-emitting element and a controllable element. The light-emitting element may emit a light. The controllable element may neighbor the light-emitting element in a plan view of the display device and may include a fluid set. The fluid set may include at least one of a light-reflecting element set and a black element set. The controllable element may have a first average reflectance value in a first direction if the controllable element receives no voltage or receives a first voltage. The controllable element may have a second average reflectance value in the first direction if the controllable element receives a second voltage. The second voltage may be unequal to the first voltage. The second average reflectance value may be unequal to the first average reflectance value.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area and a peripheral area adjacent to the display area. The display device also includes a plurality of display elements disposed in the display area. The display device also includes an insulating layer disposed in the display area and the peripheral area, wherein the insulating layer has a non-continuous area disposed in the peripheral area of the substrate.

Abstract: An organic light emitting diode display according to an exemplary embodiment of the present disclosure includes: a substrate; a first electrode disposed on the substrate; an auxiliary electrode formed at the same layer as the first electrode; a pixel defining layer having a first contact hole overlapping a part of the auxiliary electrode; an organic light emitting member disposed on the pixel defining layer and having a second contact hole enclosing the first contact hole; and a second electrode disposed on the organic light emitting member and inside the first contact hole and the second contact hole, wherein the second electrode is in contact with the auxiliary electrode through the first contact hole and the second contact hole.

Abstract: The present invention belongs to the field of display technology, and particularly relates to an array substrate, a display panel and a display device. The array substrate comprises a light-emitting unit, a driving unit for driving the light-emitting unit, and a driving signal unit for providing a driving signal to the driving unit, the driving unit being provided in a central area of the array substrate, the driving signal unit being provided on at least one side of a marginal area surrounding the central area, wherein the light-emitting unit covers the driving unit and extends into the at least one side of the marginal area on which the driving signal unit is provided. The array substrate can have not only enlarged display area but also decreased bezel width, and also have improved aperture ratio of a pixel.

Abstract: An organic light emitting display device includes a substrate including a sub-pixel region and a transparent region, a first semiconductor element in the sub-pixel region on the substrate, a second semiconductor element overlapping at least a portion of the sub-pixel region on the substrate, and is spaced apart from the first semiconductor element, a first lower electrode disposed in the sub-pixel region on the first semiconductor element and electrically connected to the first semiconductor element, a second lower electrode disposed in the transparent region on the substrate and electrically connected to the second semiconductor element, a first light emitting layer on the first lower electrode, a second light emitting layer on the second lower electrode, and an upper electrode on the first and second light emitting layers where second lower electrode has a thickness that is less than a thickness of the first lower electrode, and transmits a light.

Abstract: A display device includes a stretchable display panel including a first display area and a second display area, the second display area extending from the first display area in a horizontal direction substantially parallel to the first display area, and a frame including a first coupling part and a second coupling part spaced apart from the first coupling part in the horizontal direction, the second coupling part being moveable in a vertical direction normal to the horizontal direction, wherein the first and second display areas are respectively coupled to the first and second coupling parts, and the second display area is elongated in the vertical direction when the second coupling part moves in the vertical direction.

Abstract: The present invention relates to a circular display device including: a substrate (21) having a circular shape; a plurality of data lines (15) formed on the substrate; a plurality of gate lines (16) extending in a direction orthogonal to the plurality of data lines; a plurality of pixels (14) respectively formed at areas in which the plurality of data lines and the plurality of gate lines intersect; and a circular cover (25) that is air-tightly adhered to the substrate and covers the pixels. The cover has a driving integrated circuit (27) and a plurality of wiring patterns formed thereon, wherein the driving integrated circuit supplies scan signals and data signals to the plurality of pixels, and the wiring patterns extend and are drawn out from from the driving integrated circuit. The respective plurality of wiring patterns are electrically connected to each of the plurality of data lines and the plurality of gate lines through connection wires (29).

Abstract: An organic light emitting diode (OLED) display including: a substrate; a semiconductor layer disposed on the substrate and including a switching semiconductor layer and a driving semiconductor layer connected to the switching semiconductor layer; a first gate insulating layer disposed on the semiconductor layer; a switching gate electrode and a driving gate electrode disposed on the first gate insulating layer and respectively overlapping with the switching semiconductor layer and the driving semiconductor layer; a second gate insulating layer disposed on the switching gate electrode and the driving gate electrode; a driving voltage line configured to transmit a driving voltage and disposed on the second gate insulating layer; an interlayer insulating layer disposed on the driving voltage line and the second gate insulating layer; and a data line configured to transmit a data signal and disposed on the interlayer insulating layer.

Abstract: Provided are a capacitor of a semiconductor integrated circuit and a method for manufacturing the same, for example a metal-insulator-metal (MIM) type capacitor of a semiconductor integrated circuit, which is capable of improving adhesive force between an electrode layer and a dielectric layer of a capacitor, and a method for manufacturing the same. For example, the present disclosure provides a capacitor for a semiconductor integrated circuit having a new structure, which is capable of preventing a delamination phenomenon on an interface between a lower electrode layer and a dielectric layer by further forming a buffer layer, which is capable of decreasing or compensating for a difference in a coefficient of thermal expansion, between a metal electrode layer and a dielectric layer, particularly, between the lower electrode layer and the dielectric layer, and a method for manufacturing the same.

Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.

Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

Abstract: In one embodiment, a semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Dielectric isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent dielectric isolation regions.

Abstract: Shaped mandrels are used to form closed-loop spacer(s) around the shaped mandrels, after which the shaped mandrels are removed, leaving a closed-loop fin. A transistor includes U-shaped portion(s) of a closed-loop fin, and a gate across channel region(s) of the U-shaped portion(s) of a closed-loop fin. A semiconductor structure includes portion(s) of closed-loop fin(s), and transistors formed from the portion(s) of closed-loop fin(s).

Abstract: A semiconductor device according to an embodiment includes an n-type SiC region, an electrode in contact with the SiC region, and a region including oxygen, the region provided in the SiC region, the region being provided on an electrode side of the SiC region.

Abstract: A silicon carbide semiconductor switching device having a planar metal oxide semiconductor insulated gate structure. The silicon carbide semiconductor switching device includes a silicon carbide semiconductor substrate having a bandgap wider than that of silicon, a drift layer formed on the silicon carbide semiconductor substrate, a base region selectively formed in the drift layer at a top surface thereof, a source contact region selectively formed in the base region at a top surface thereof, a trench formed in the drift layer at the top surface thereof, the trench having a depth that is shallower than a depth of the source contact region, a gate electrode embedded in the trench, a top surface of the gate electrode being substantially flush with a top surface of the source contact region, and an interlayer insulating film formed on the top surfaces of the source contact region and the gate electrode.

Abstract: The main purpose of the present invention is to provide: a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a technique required for the production of the substrate. This invention provides: a method for manufacturing an M-plane GaN substrate comprising; forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonotharmal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.

Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

Abstract: A semiconductor device includes a transistor cell area with active transistor cells including source zones electrically connected to a first load electrode. The source zones have a first conductivity type. An edge area surrounds the active transistor cell area and includes an edge construction that includes straight sections and a corner section connecting neighboring straight sections. A second dopant ratio between a mean concentration of dopants of a complementary second conductivity type and a mean concentration of dopants of the first conductivity type in the corner section exceeds a first dopant ratio between a mean concentration of dopants of the second conductivity type and a mean concentration of dopants of the first conductivity type in the straight sections by at least 0.2% in relation to the first dopant ratio.

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

Abstract: A method for forming a steeped oxide on a substrate is described: successively forming a first pad oxide layer, a nitride layer, a second pad oxide layer and a poly layer on the substrate; etching the poly layer to have an opening for the stepped oxide region; isotropically etching the second pad oxide layer to the nitride layer through the opening to form a stepped trench; isotropically etching the nitride layer to the first pad oxide layer through the opening to expand the stepped trench; filling the stepped trench with dielectric material to form a dielectric layer; planarizing the dielectric layer; removing the poly layer; removing the second pad oxide layer; removing the nitride layer; removing the portion of the first pad oxide layer uncovered by the dielectric layer such that the remaining first pad oxide layer together the remaining dielectric layer forms the stepped oxide.

Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.

Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.

Abstract: Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.

Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins.

Abstract: A method of fabricating a semiconductor device includes forming a first, a second and a third trenches extending through a dielectric layer over a substrate, forming a material layer in the first, the second and the third trenches, forming a sacrificial layer to fully fill in the remaining first and the second trenches, recessing the sacrificial layer in the first trench and the second trench, recessing the material layer in the first trench and in the second trench. After recessing the material layer, a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the first trench and a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the second trench. The method also includes removing the remaining sacrificial layer in the first trench and the second trench.

Abstract: A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first portion and a second portion under the first portion, where the first portion of the source trench is wider than the gate trench, and extends to a depth of the gate trench. The semiconductor device also includes a gate electrode and a gate trench dielectric liner in the gate trench, and a conductive filler and a source trench dielectric liner in the source trench. The semiconductor device further includes a source region between the gate trench and the source trench, a base region between the gate trench and the source trench, and a source contact coupled to the source region and the base region.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.

Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: A semiconductor device is provided. The Semiconductor device includes a first active fin and a second active fin disposed on a substrate. A first gate electrode intersects the first active fin. A second gate electrode intersects the second active fin. A first gate insulation layer includes a first high dielectric constant insulation layer. The first gate insulation layer is disposed between the first gate electrode and the first active fin. A second gate insulation layer includes a second high dielectric constant insulation layer. The second gate insulation layer is disposed between the second gate electrode and the second active fin. A thickness of the first high dielectric constant insulation layer is thicker than a thickness of the second high dielectric constant insulation layer.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.

Abstract: Provided is a group 13 nitride epitaxial substrate with which the HEMT device having superior characteristics can be manufactured. This epitaxial substrate is provided with: a base substrate composed of SiC and having a main surface with a (0001) plane orientation; a nucleation layer formed on one main surface of the base substrate and composed of AlN; an electron transit layer formed on the nucleation layer and composed of a group 13 nitride with the composition AlyGa1?yN (0?y<1); and a barrier layer formed on the electron transit layer and composed of a group 13 nitride with the composition InzAl1?zN (0.13?z?0.23) or AlwGa1?wN (0.15?w?0.35). The (0001) plane of the base substrate has an off angle of 0.1° or more and 0.5° or less, and an intermediate layer composed of a group 13 nitride with the composition AlxGa1?xN (0.01?x?0.4) is further provided between the nucleation layer and the electron transit layer.

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

Abstract: A semiconductor device may include the following elements: a fin member including a first doped portion, a second doped portion, and a semiconductor portion positioned between the first doped portion and the second doped portion; a composite structure including a conductor and an insulator positioned between the conductor and the semiconductor portion in a first direction; a first spacer having a first dielectric constant and positioned close to the second doped portion; a second spacer having a second dielectric constant and positioned close to the first doped portion; and a third spacer having a third dielectric constant. The second spacer is positioned between the third spacer and the fin member in the first direction. The composite structure is positioned between the first spacer and the second spacer. The first dielectric constant is less than at least one of the second dielectric constant and the third dielectric constant.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure comprising a substrate, a plurality of fins on the substrate and a hardmask on the fins, forming an insulating layer on the substrate structure covering the fins and the hardmask, removing a portion of the insulating layer by etching to expose the hardmask, removing the hardmask, and performing a fluorine ion implantation into a top portion of the fins. The implanted fluorine ions passivate dangling bonds in the top portion of the fins, thereby improving the reliability of the semiconductor device.