Abstract: The present disclosure provides fin field-effect transistors and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a first region and a second region; forming first fins in the first region and second fins in the second region; forming a liner oxide layer on side surfaces of the first fins, the second fins and a surface of the substrate; forming an insulating barrier layer on the liner oxide layer in the first region; forming a precursor material layer on the insulating barrier layer in the first region and on the liner oxide layer in the second region; performing a curing annealing process to convert the precursor material into an insulation layer; and removing a top portion of the insulation layer to form an isolating layer and removing portions of the liner oxide layer, the insulating barrier layer, the first oxide layer and the second oxide layer.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Abstract: A method of manufacturing a pixel structure is provided. A gate and a gate insulating layer are formed on a substrate. A channel layer is formed on the gate insulating layer, and the material of the channel layer includes a first metal oxide semiconductor material. A source and a drain are formed on opposite sides of the channel layer. An insulating layer has an opening exposing the drain. First and second transparent electrode material layers are formed on the substrate sequentially, the material of the first transparent electrode material layer includes a second metal oxide semiconductor material, and the material of the second transparent electrode material layer includes a metal oxide conductive material. The first and second transparent electrode material layers are patterned using the same mask to form first and second transparent electrode layers, wherein the first transparent electrode layer is in contact with the drain through the opening.

Abstract: A manufacturing method of a metal oxide semiconductor thin film transistor is provided. The manufacturing method includes following steps. A gate, a gate insulating layer, a patterned metal oxide semiconductor layer and a conductive layer are formed on a substrate first. Next, a first patterned photoresist layer and two second patterned photoresist layers are formed on the conductive layer. Next, a first etching process is performed and the first patterned photoresist layer is then removed. Next, a second etching process is performed to form a source and a drain, and the second patterned photoresist layers are then removed. The source and the drain of the present invention are formed by performing two etching processes to different portions of the conductive layer respectively. Thus, the metal oxide semiconductor layer is prevented from being influenced by the processes of forming the source and the drain, and the process stability is maintained.

Abstract: A method of controlling a Casimir-effect device includes applying a voltage to a field-effect gate of the Casimir-effect device. The Casimir-effect device includes a conducting material and a semiconductor. The conducting material and semiconductor are separated by a gap to form the field-effect gate over at least a portion of the semiconductor facing the gap. The method further includes altering, in response to the applied voltage, a density of free charge carriers in the portion of the semiconductor facing the gap to control a nanoscale Casimir force between the conducting material and the portion of the semiconductor facing the gap.

Abstract: An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that are capable of further reducing a turn-on voltage are provided. An epitaxial wafer for a heterojunction bipolar transistor includes a collector layer made of GaAs, a base layer formed on the collector layer and made of InGaAs, and an emitter layer formed on the base layer and made of InGaP, and the base layer has an In composition that decreases from the emitter layer side toward the collector layer side.

Abstract: A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for controlling the channel on the heterostructure body, the gate structure having a doped semiconductor region disposed on the heterostructure body, an interlayer disposed on the doped semiconductor region, and a gate electrode disposed on the interlayer. Forming the gate structure includes controlling a doping concentration of the doped semiconductor region such that a portion of the channel adjacent the gate structure is non-conductive at zero gate bias, and controlling electrical and geometrical characteristics of the interlayer based upon a relationship between the electrical and geometrical characteristics of the interlayer and corresponding effects on a static threshold voltage and a dynamic threshold voltage shift of the semiconductor device.

Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer on the first nitride semiconductor layer and having a larger band gap than that of the first nitride semiconductor layer, a gate electrode on the second nitride semiconductor layer, drain and source electrodes on the second nitride semiconductor layer with the gate electrode interposed therebetween, interlayer insulating films on the second nitride semiconductor layer in a layer shape, and field plates including a first field plate at a greater distance from the second nitride semiconductor layer than the gate electrode and closer to the drain electrode than the gate electrode, and a second field plate at a larger distance from the second nitride semiconductor layer than the first field plate and nearer to drain electrode than the first field plate. The first and second field plates extend inwardly of the same interlayer insulating film.

Abstract: A switching device includes first-third semiconductor layers, a gate insulating film, and a gate electrode. The first semiconductor layer is of a first conductivity type, The second semiconductor layer is of a second conductivity type and in contact with the first semiconductor layer. The third semiconductor layer is of the first conductivity type, in contact with the second semiconductor layer. The gate insulating film covers a surface of the second semiconductor layer in a range in which the second semiconductor layer separates the first semiconductor layer from the third semiconductor layer. The gate electrode faces the second semiconductor layer via the gate insulating film. The gate electrode includes a fourth semiconductor layer covering a surface of the gate insulating film; and a fifth semiconductor layer having a bandgap different from a bandgap of the fourth semiconductor layer and covering a surface of the fourth semiconductor layer.

Abstract: According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

Abstract: A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.

Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a feature comprising germanium over a substrate; (ii) removing a portion of the feature such that an interior portion of the feature is exposed; (iii) exposing a surface of the exposed interior portion to a surrounding containing oxygen; and (iv) treating the germanium oxide on the surface of the exposed interior portion with a liquid containing water.

Abstract: The present disclosure provides PMOS transistors and fabrication methods thereof. An exemplary fabrication process of a PMOS transistor includes providing a semiconductor substrate having a surface; forming a gate structure on the surface of the semiconductor substrate; forming SiGe regions in the surface of the semiconductor substrate at two sides of the gate structure by implanting Ge ions into the semiconductor substrate; forming sidewalls on side surfaces of the gate structure and portions of surfaces of the SiGe regions close to the gate structure; removing portions of the SiGe regions at two sides of the gate structure to expose portions of the semiconductor substrate; forming trenches in the semiconductor substrate by etching the exposed portions of the semiconductor substrate at the two sides of the sidewalls; and forming source/drain regions by filling the trenches with a compressive stress material.

Abstract: A semiconductor device (100) includes a thin film transistor (5) provided on a substrate and including a gate electrode (12), a gate insulating layer (20) in contact with the gate electrode, an oxide semiconductor layer (18) located so as to partially overlap the gate electrode with the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a source electrode (14), and a drain electrode (16). The oxide semiconductor layer (18) includes a gate facing region (18g) overlapping the gate electrode as seen in a direction of normal to the substrate; and offset regions (18os, 18od) provided adjacent to the gate facing region, the offset regions not overlapping the gate electrode, the source electrode or the drain electrode as seen in the direction of normal to the substrate. The gate facing region has a carrier concentration in the range of 1×1017/cm3 or greater and 1×1019/cm3 or less.

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

Abstract: According to one embodiment, a thin-film transistor includes a first insulating film, an oxide semiconductor layer provided on the first insulating film and a second insulating film provided on the oxide semiconductor layer, and at least one of the first insulating film and the second insulating film includes a first region in contact with the oxide semiconductor layer and a second region further distant from the oxide semiconductor layer than the first region, and the second region has an argon concentration higher than that of the first region.

Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate and a display device. The method for manufacturing a TFT includes forming a source electrode and a drain electrode, forming a metal layer on the source and drain electrodes, and forming a metal oxynitride semiconductor layer on the metal layer or on the source and drain electrodes and the metal layer. The metal layer is capable of being oxidized by oxygen ions in the metal oxynitride semiconductor layer.

Abstract: The present disclosure provides a thin-film transistor. The thin-film transistor includes a substrate including at least one trench; at least one electrode in each of the at least one trench, the at least one electrode being one or more of a gate electrode, a source electrode, and a drain electrode; and an active layer over the at least one electrode.

Abstract: A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.

Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

Abstract: Each of varicaps 50A to 50C configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicaps 50A to 50C has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicaps 50A to 50C is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

Abstract: A method of fabricating an optoelectronic device includes the steps of providing a semiconductor unit and forming a plurality of metal contacts on a surface of the semiconductor unit for electrical conduction. The method further includes the step of forming a plurality of color coating regions on top of the plurality of metal contacts, the plurality of color coating regions imparting a color different than a color of the plurality of metal contacts.

Abstract: This wiring module includes: a wiring substrate; a base portion at which the wiring substrate is placed; and an adhesive layer configured to adhere the wiring substrate to the base portion, wherein the wiring substrate includes: a land portion configured to have a power generating element mounted thereto; and a wire portion configured to be electrically connected to the power generating element, the adhesive layer has: a land adhesion region configured to adhere the land portion to the base portion; and a wire adhesion region configured to adhere the wire portion to the base portion, and a width of the wire adhesion region is smaller than a width of the land adhesion region.

Abstract: The invention relates to a passivated emitter rear solar cell, comprising a silicon substrate having a front and back surface, a rear passivation layer on the back surface of the silicon substrate having a plurality of open holes formed therein, an aluminum back contact layer formed in the open holes of the rear passivation layer, and at least one backside soldering tab on the back surface of the silicon substrate. The backside soldering tab is formed from an electroconductive paste composition comprising conductive metallic particles, at least one lead-free glass frit, and an organic vehicle comprising at least one silicone oil.

Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate. A plurality of patterned antireflective coatings is located on the front side surface to provide a grid pattern including a busbar region and finger regions. The busbar region includes at least a real line interposed between at least two dummy lines. A material stack including at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.

Abstract: A solar cell is provided with an electrode layer on a photovoltaic conversion section including a crystalline silicon substrate. Deposition of the electrode layer is performed by a deposit-up method with a substrate being mounted in such a manner that an opening edge portion of a mask plate having an opening is in contact with the substrate. The opening edge portion of the mask plate has a tapered surface at a part that is in contact with first principal surface of the substrate, the tapered surface conforming to a deflection angle at a peripheral end of the substrate. A solar cell having a large effective area can be prepared by suppressing deposition of electrode layer on mask-covered region due to penetration.

Abstract: A composition of matter and method of forming copper indium gallium sulfide (CIGS), copper indium gallium selenide (CIGSe), or copper indium gallium telluride thin film via conversion of layer-by-layer (LbL) assembled Cu—In—Ga oxide (CIGO) nanoparticles and polyelectrolytes. CIGO nanoparticles are created via a flame-spray pyrolysis method using metal nitrate precursors, subsequently coated with polyallylamine (PAH), and dispersed in aqueous solution. Multilayer films are assembled by alternately dipping a substrate into a solution of either polydopamine (PDA) or polystyrenesulfonate (PSS) and then in the CIGO-PAH dispersion to fabricate films as thick as 1-2 microns. After LbL deposition, films are oxidized to remove polymer and sulfurized, selenized, or tellurinized to convert CIGO to CIGS, CIGSe, or copper indium gallium telluride.

Abstract: A photoelectric conversion element includes a photoelectric conversion layer having the quantum structure and utilizes intersubband transition in a conduction band. The photoelectric conversion element includes a superlattice semiconductor layer in which a barrier layer and a quantum dot layer as a quantum layer are alternately and repeatedly stacked. The barrier layer includes an indirect transition semiconductor material, and the quantum dot layer has a nano-structure including a direct transition semiconductor material. The indirect transition semiconductor material constituting the barrier layer has a bandgap of more than 1.42 eV at room temperature.

Abstract: PV modules with improved volume resistivity comprise an encapsulant film and a polyolefin backsheet at least one of which comprises organoclay.

Abstract: A solar cell module includes solar cells. encapsulants are layered on surfaces of the solar cells. A glass substrate is layered on the encapsulants. The solar cell module further includes an epoxy resin-containing member. Each encapsulant includes the ultraviolet ray-absorbing member. The ultraviolet ray-absorbing member sets the transmittance to 1% or less at the wavelengths ranging from 300 to 360 nm.

Abstract: The disclosure relates to solar cell, and especially to a method for manufacturing a crystalline silicon solar cell module. The method includes: a) providing a solar cell module to be laminated, including a back plate, a first bonding layer, a crystalline silicon solar cell component, a second bonding layer and a top plate in contact in sequence, where the crystalline silicon solar cell component is a crystalline silicon solar cell or a cell string formed by connecting multiple crystalline silicon solar cells; b) laminating the solar cell module to be laminated under current injection, to obtain a laminated solar cell module; and c) installing a frame and a junction box on the laminated solar cell module, to obtain a crystalline silicon solar cell module. The crystalline silicon solar cell module is under the current injection during the laminating process, improving the performance against light-induced degradation.

Abstract: The present disclosure generally relates to a solar cell device that a first Bragg reflector disposed below a first solar cell and a second Bragg reflector disposed below the first Bragg reflector, wherein the first solar cell comprises a dilute nitride composition and has a first bandgap, wherein the first Bragg reflector is operable to reflect a first range of radiation wavelengths back into the first solar cell and the second Bragg reflector is operable to reflect a third range of wavelengths back into the first solar cell, and the first Bragg reflector and the second Bragg reflector are operable to cool the solar cell device by reflecting a second range of radiation wavelengths that are outside the photogeneration wavelength range of the first solar cell or that are weakly absorbed by the first solar cell.

Abstract: A photovoltaic module comprises a back substrate having a plurality of conductive interconnects on top thereof. A conductive interconnect includes a first contact region and a second contact region. The photovoltaic module further comprises a plurality of photovoltaic cells comprising front electrodes disposed on a front surface of a photovoltaic layer on top of back electrodes on top of a support substrate. A plurality of back vias extending through the support substrate of a first cell form an electrical contact between the back electrodes and the second contact region, and a plurality of front vias extending through the support substrate, the back electrodes and the photovoltaic layer of a second cell form an electrical contact between the front electrodes and the first contact region, and is insulated from an electrical contact with the back electrodes and a P side of the photovoltaic layer.

Abstract: A photovoltaic device and display equipment are provided. The photovoltaic device includes at least one photoelectric conversion sheet and a light guide plate, the at least one photoelectric conversion sheet arranged at a light exiting face side of the light guide plate.

Abstract: A high concentration photovoltaic device has a Fresnel lens having a front side and a back side, which may be mounted on a cover plate, and a mirror behind the Fresnel lens and facing the Fresnel lens. A secondary lens is unitary with the Fresnel lens and facing the mirror, and is typically on the inside of the cover plate in the center of the Fresnel lens. A photovoltaic cell in front of the secondary lens faces the mirror through the secondary lens. An additional focusing lens may be provided in front of the mirror. Two optical elements of said device form a Köhler integrator between a remote source, usually the sun, in front of the device and the photovoltaic cell as a target. The mirror may be spectrally selective, with a secondary photovoltaic cell behind the mirror. Additional photovoltaic cells to collect unfocused light may surround the mirror.

Abstract: The present disclosure generally relates to a solar cell device that includes a substrate comprising a front side surface and a backside surface; an epitaxial region overlying the substrate, wherein the epitaxial region comprises a first Bragg reflector disposed below a first solar cell, wherein the first solar cell has a first bandgap, wherein the first Bragg reflector is operable to reflect a first range of radiation wavelengths back into the first solar cell, and is operable to cool the solar cell device by reflecting a second range of radiation wavelengths that are outside the photogeneration wavelength range of the first solar cell or that are weakly absorbed by the first solar cell, and may additionally comprise a second Bragg reflector operable to reflect a third range of radiation wavelengths back into the first solar cell.

Abstract: Disclosed is a solar cell including a semiconductor substrate, a protective-film layer formed over one surface of the semiconductor substrate, a first conductive area disposed over the protective-film layer, the first conductive area being of a first conductive type and including a crystalline semiconductor, and a first electrode electrically connected to the first conductive area. The first conductive area includes a first portion disposed over the protective-film layer and having a first crystal grain size, and a second portion disposed over the first portion and having a second crystal grain size, which is greater than the first crystal grain size.

Abstract: A device and a method of forming a device. The method comprises forming an oxide material film; forming two metal electrodes on the oxide material film, the two metal electrodes laterally spaced from each other such that an electric path between the two electrodes comprises at least a portion of the oxide material film; configuring the oxide material film such that a current-voltage characteristic of the device as measured via the two metal electrodes exhibits nonlinearity and rectification.

Abstract: A manufacturing method includes steps of forming a texture on a surface of a single-crystalline silicon substrate, cleaning the surface of the single-crystalline silicon substrate using ozone, depositing an intrinsic silicon-based layer on the texture on the single-crystalline silicon substrate, and depositing a conductive silicon-based layer on the intrinsic silicon-based layer, in this order. The single-crystalline silicon substrate before deposition of the intrinsic silicon-based layer has a texture size of less than 5 ?m. A recess portion of the texture has a curvature radius of less than 5 nm. After deposition of at least a part of the intrinsic silicon-based layer and before deposition of the conductive silicon-based layer, the intrinsic silicon-based layer is subjected to a plasma treatment in an atmosphere of a gas mainly composed of hydrogen.

Abstract: In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer's characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates.

Abstract: The disclosed invention relates to a semiconductor light-emitting element comprising: a plurality of semiconductor layers which are provided with a growth substrate eliminating surface on the side where a first semiconductor layer is located; a support substrate which is provided with a first electrical pathway and a second electrical pathway; a joining layer which joins a first surface side of the support substrate with a second semiconductor layer side of the plurality of semiconductor layers, and is electrically linked with the first electrical pathway; a joining layer eliminating surface which is formed on the first surface, and in which the second electrical pathway is exposed, and which is open towards the plurality of semiconductor layers; and an electrical link for electrically linking the plurality of semiconductor layers with the second electrical pathway exposed in the joining layer eliminating surface.

Abstract: A method for manufacturing a light emitting element that includes preparing a wafer having a substrate and a semiconductor structure, the substrate including a plurality of protrusions at positions corresponding to lattice points on a regular triangular lattice. The method includes forming a plurality of first modified parts in the substrate by irradiating the substrate with a laser beam along first dividing lines, forming a plurality of second modified parts in the substrate by irradiating the substrate with a laser beam along second dividing lines, and dividing the wafer along the first modified parts and the second modified parts to obtain a plurality of light emitting elements.

Abstract: Provided is an optical device including an active layer, which includes two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. The second quantum well layer is between the first quantum well layer and the third quantum well layer. An energy band gap of the second quantum well layer is less than an energy band gap of the first quantum well layer, and an energy band gap of the third quantum well layer is equal to or less than the energy band gap of the second quantum well layer.

Abstract: A method of fabricating a light emitting diode (LED) includes: sequentially stacking a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a substrate; and separating the substrate into unit chips, and at the same time, forming a concavo-convex structure having the shape of irregular vertical lines in a side surface of the unit chip.

Abstract: Disclosed are a light emitting diode and a light emitting diode module. The light emitting diode module includes a printed circuit board and a light emitting diode joined thereto through a solder paste. The light emitting diode includes a first electrode pad electrically connected to a first conductive type semiconductor layer and a second electrode pad connected to a second conductive type semiconductor layer, wherein each of the first electrode pad and the second electrode pad includes at least five pairs of Ti/Ni layers or at least five pairs of Ti/Cr layers and the uppermost layer of Au. Thus a metal element such as Sn in the solder paste is prevented from diffusion so as to provide a reliable light emitting diode module.

Abstract: The present disclosure relates to a method for manufacturing a self-assembled nano-scale LED electrode assembly and more particularly, to a method for manufacturing a self-assembled nano-scale LED electrode assembly in which a nano-scale LED device can be self-aligned on two different electrodes without being chemically and physically damaged and the number of nano-scale LED devices to be mounted can be remarkably increased, and alignment and electrical connection of the LED devices can be further improved.