Abstract: Provided is an organic light emitting device including: an organic emission layer disposed between a first electrode and a second electrode and in a plurality of sub-pixel areas; a plurality of electroluminescence units which include the organic emission layer and are formed by stacking; and a charge generation layer between the plurality of electroluminescence units, where the charge generation layers respectively disposed in the plurality of sub-pixel areas have a step and are formed at different positions, and the second electrodes respectively disposed in the multiple sub-pixel areas have a step and are formed at different positions.

Abstract: Disclosed is a display device including a pixel portion having a plurality of pixels which have a display element and a transmissive portion. The display element includes a light-emitting element which does not transmit external light, while the transmissive portion is arranged to transmit external light. In the display element, a top-emission or bottom-emission type light-emitting element is provided. On the other hand, no light-emitting element or a dual-emission type light-emitting element which possesses an EL layer interposed between two light-transmissive electrodes is provided to the transmissive portion. The emission color of the display element is controlled by a color filter which overlaps with the light-emitting element in the display element, while no color filter is given to the transmissive portion.

Abstract: A pixel element structure is disclosed. The pixel element structure includes first, second, and third sub-pixel elements, each including a light-emitting region. At least one of the first, second, and third sub-pixel elements includes a light-transmitting region, where the light-emitting region includes an organic light-emitting diode light-emitting structure, and where the organic light-emitting diode light-emitting structure includes a first substrate, and a nontransparent anode, a pixel defining layer, an organic layer and a cathode, sequentially arranged above the first substrate.

Abstract: An organic light emitting device utilizing the micro-cavity effect in the RGB subpixel regions while suppressing the micro-cavity effect in the white subpixel region is provided. The organic light emitting device includes a lower substrate, an anode formed on the lower substrate, an organic emission layer formed on the anode, a cathode formed on the organic emission layer, and a reflection decreasing layer formed on at least a portion of the cathode for reducing reflection of the light emitted from the organic emission layer by the cathode to reduce the micro-cavity effect. Such a selective use of the micro-cavity effect in the organic light emitting device improves the color accuracy, the luminance efficiency and the lifespan of the top emission type organic light emitting device.

Abstract: An organic light emitting display including a substrate, a first electrode and a second electrode on the substrate and facing each other, at least two organic light emitting layers between the first electrode and the second electrode, and at least two color filters on the second electrode, the organic light emitting layers emitting a first color light, and the color filters emitting a second color light and a third color light.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate including a pixel region including a plurality of pixels. A plurality of lighting test transistors is formed in a peripheral region surrounding the pixel region and electrically connected to the pixels, and the lighting test transistors are configured to test lighting of the pixels. Each of the lighting test transistors includes a first active layer pattern formed over the substrate, a first gate electrode formed over the first active layer pattern, and a conductive pattern formed over the first gate electrodes. The conductive pattern is electrically connected to the first gate electrode, the first gate electrodes are spaced apart from each other and have substantially the same shape, and the conductive patterns are integrally formed.

Abstract: A bottom emission organic electroluminescence display, a preparation method thereof, and a display apparatus are provided. The display includes a base substrate (100), and at least one dielectric thin film layer group (200) and a thin film transistor (300) that are successively arranged on the base substrate; each dielectric thin film layer group (200) comprising at least two stacked dielectric thin film layers (201, 202, 203), the refractive indices of which are increased progressively from the base substrate towards the thin film transistor.

Abstract: A package structure includes a substrate and a package plate. A frame is formed of a seal glue arranged between the substrate and the package plate. An underfill is positioned inboard of the frame. The package plate has a spreading surface, and at least one groove is formed in a spreading path of the frame on the spreading surface of the package plate.

Abstract: The present invention discloses a light-emitting device, array substrate, display device and manufacturing method of light-emitting device. The light-emitting device comprises a substrate and a pixel define layer provided on the substrate, the pixel define layer defines at least one pixel unit, each of which comprises a plurality of first electrodes, an organic layer provided on the plurality of first electrodes, and a second electrode provided on the organic layer. The light-emitting device, array substrate, display device and manufacturing method provided by the present invention can allow the formed film of the organic layer on the first electrodes to have good flatness and allow portions of the organic layer on different first electrodes to have substantially the same thickness, thus flatness and uniformity of the formed film of the organic layer in the light-emitting device is improved and further display quality of the light-emitting device is improved.

Abstract: An organic light-emitting device includes at least an underlayer, a partition wall, and an organic film. The underlayer is disposed above a substrate. The partition wall covers a first part and surrounds a second part of the surface of the underlayer. The organic film includes organic material, is disposed in a recess formed by the partition wall surrounding the second part, and is in contact with the surface of the underlayer and a surface of the partition wall. The surface of the underlayer has a protruding portion that protrudes in an upward direction. The protruding portion is composed of a top surface and an inclined surface surrounding the top surface. The first part includes least the top surface and a portion of the inclined surface, and an inner edge of the partition wall is in contact with the inclined surface or a level portion of the surface of the underlayer.

Abstract: Provided is a light emitting display device. The emitting display device comprises: a substrate including a plurality of pixels which are arranged in a first direction and a second direction that crosses the first direction, the plurality of pixels comprising a first main pixel block and a second main pixel block; a planarization pattern arranged on the substrate; a first electrode on the planarization pattern for each of the plurality of pixels; a pixel defining layer partitioning the respective pixels on the substrate and having an opening for exposing the first electrode; an organic layer on the first electrode; and a second electrode on the organic layer, wherein a thickness of the planarization pattern of the pixel in the second main pixel block is larger than a thickness of the planarization pattern of the pixel in the first main pixel block.

Abstract: An organic light-emitting display apparatus, including a substrate, a reflection control layer disposed on the substrate and including a metal layer and dielectric layer, a thin-film transistor disposed on the reflection control layer and including an active layer, a gate electrode, a source electrode, and a drain electrode, a storage capacitor disposed on the reflection control layer and including a first electrode and a second electrode, a pixel electrode connected to one of the source electrode and the drain electrode, an intermediate layer disposed on the pixel electrode and including an organic emission layer, an opposite electrode disposed on the intermediate layer, in which a portion of the metal layer of the reflection control layer comprises the first electrode of the storage capacitor.

Abstract: A pad electrode structure including a substrate, an insulating layer on the substrate, a pad electrode on a portion of the insulating layer, and an organic insulating layer on the pad electrode and having an opening exposing an upper surface of the pad electrode, wherein an insertion area is in the insulating layer near the substrate, and wherein the organic insulating layer is separated from an end portion of the substrate, and a portion of the organic insulating layer is in the insertion area.

Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a multi-layer capacitor dielectric layer including an amorphous dielectric layer configured to mitigate the formation of leakage paths, and a method of formation. In some embodiments, the MIM (metal-insulator-metal) capacitor has a capacitor bottom metal layer. A multi-layer capacitor dielectric layer is disposed over the capacitor bottom metal layer. The multi-layer capacitor dielectric layer has an amorphous dielectric layer abutting a high-k dielectric layer. A capacitor top metal layer is disposed over the multi-layer capacitor dielectric layer. The high-k dielectric layer within the capacitor dielectric layer provides the MIM capacitor with a high capacitance density, while the amorphous dielectric layer prevents leakage by blocking the propagation of grain boundaries between the capacitor top metal layer and the capacitor bottom metal layer.

Abstract: An electrical device including a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer.

Abstract: A thin film electronic component includes: a substrate; a thin film electrode layer over the substrate; an inorganic insulation layer formed on the thin film electrode layer; an organic insulation layer formed on the inorganic insulation layer; and a lead-out electrode that electrically connects to the thin film electrode layer. The inorganic insulation layer has a through-hole formed therein, so as to expose a portion of the thin film electrode layer. The organic insulation layer has a through-hole formed therein, so as to expose the through-hole in the inorganic insulation layer. The lead-out electrode is formed in the through-hole in the inorganic insulation layer and the through-hole in the organic insulation layer. A shape of a borderline defining the through-hole at a top surface of the organic insulation layer in a plan view has chamfered corners.

Abstract: Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

Abstract: The present disclosure provides a capacitor structure, including a substrate having a conductive region; a trench in the conductive region and having a bottom portion and an inner sidewall portion; a spacer over the inner sidewall portion of the trench; a first conductive layer over the bottom portion and the spacer in the trench; a first dielectric layer over the first conductive layer and in the trench; a second conductive layer over the first dielectric layer and in the trench; and a second dielectric layer over the second conductive layer and in the trench, wherein the spacer comprises an angle in a range of from about 85 to about 89 degrees with respect to the bottom portion of the trench and comprises a flared opening opposite to the bottom portion of the trench. The present disclosure also provides a method for manufacturing the capacitor structure.

Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.

Abstract: A silicon carbide semiconductor device capable of achieving a decrease in ON resistance and an increase in breakdown voltage and a method for manufacturing a silicon carbide semiconductor device. A silicon carbide semiconductor device includes a silicon carbide substrate and a drift layer. The drift layer includes a breakdown voltage holding layer extending from a point where a doping concentration has a predetermined value to a surface of the drift layer. The doping concentration in the breakdown voltage holding layer continuously decreases from the point where the doping concentration has the predetermined value to a modulation point located further toward the surface of the drift layer than a midpoint in a film thickness direction of the breakdown voltage holding layer. The doping concentration in the breakdown voltage holding layer continuously increases from the modulation point to the surface of the drift layer.

Abstract: A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

Abstract: A high voltage integrated circuit device suppresses the quantity of holes that are implanted due to a negative voltage surge, thus preventing malfunction and destruction of a high side circuit. A p?-type aperture portion has a gap portion in an n-type well region that is a voltage resistant region, penetrating the n-type well region to reach a p-type substrate, so as to enclose an n-type well region that is a high potential region.

Abstract: A super junction semiconductor device includes a semiconductor portion with first and second surfaces parallel to one another and including a doped layer of a first conductivity type formed at least in a cell area. Columnar first super junction regions of a second conductivity type extend in a direction perpendicular to the first surface and are separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A first electrode structure directly adjoins the first surface and a second electrode structure directly adjoins the second surface. The first electrode structure has a first thickness and the second electrode structure has a second thickness. A sum of the first and second thicknesses is at least 20% of the thickness of the semiconductor portion between the first and second surfaces.

Abstract: An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

Abstract: A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: Formation of semiconductor structures employing selective removal of fins includes, for example, providing a substrate having a first plurality of fins having first hard masks thereon, a second plurality of fins having second hard masks thereon, the first hard mask being different from the second hard mask, depositing a first fill material between lower portions of the first and second fins, depositing a third hard mask layer on the first fill material between the first and second fins, depositing a second fill material on the third hard mask extending between upper portions of the first and second fins, selectively removing the second hard masks and the second fins to form open cavities in the first and second fill material, depositing a third fill material in the opened cavities, and removing the second fill material and the third fill material above the third hard mask to form a fin-cut region.

Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region. The first connection region is provided to include a first intersection and a second intersection, the first intersection being an intersection of a straight line along a first straight-line portion and a straight line along a second straight-line portion, the second intersection being an intersection of a straight line along a third straight-line portion and a straight line along a fourth straight-line portion, and the first connection region has a second conductivity type.

Abstract: A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface of the first and second main surfaces is made of single-crystal silicon carbide. In the one main surface, sulfur atoms are present at not less than 60×1010 atoms/cm2 and not more than 2000×1010 atoms/cm2, and carbon atoms as an impurity are present at not less than 3 at % and not more than 25 at %. Thereby, a silicon carbide substrate having a stable surface, a semiconductor device using the substrate, and methods for manufacturing them can be provided.

Abstract: A semiconductor device includes an n+ type silicon carbide substrate, and in the substrate an active region where primary current flows and an edge termination area surrounding the active region. The semiconductor device has a first p-type region and a second p-type region in the edge termination area, and the first p-type region includes therein a plurality of third p-type regions, and the second p-type region includes therein a plurality of fourth p-type regions. The widths between the respective plurality of third p-type regions and the widths between the respective plurality of fourth p-type regions become greater further away from the active region.

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

Abstract: Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type layer is formed on or in the p-doped layer. The n-type layer includes ZnO on the p-doped layer to form an electronic device.

Abstract: A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided.

Abstract: According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.

Abstract: A CMOS fabrication process provides metal gates and contact metallization protected by metal cap layers resistant to reagents employed in downstream processing. Cobalt gates and contact metallization are accordingly feasible in CMOS processing requiring downstream wet cleans and etch processes that would otherwise compromise or destroy them. Low resistivity metal cap materials can be employed.

Abstract: According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises depositing a transition layer on a substrate, depositing GaN material on the transition layer, forming a contact on the GaN material, depositing a stressor layer on the GaN material, separating the transition layer and the substrate from the GaN material, patterning and removing portions of the GaN material to expose portions of the stressor layer.

Abstract: Method for manufacturing an insulated gate bipolar transistor, which includes a drift layer of a first conductivity type between an emitter side, at which a gate and emitter electrode are arranged, and a collector side, at which a collector electrode is arranged including steps: providing a substrate of a second conductivity type, applying a dopant of the first conductivity type on the first side, creating a drift layer of the first conductivity type on the first layer, diffusing the ions such that a buffer layer is created, having a higher doping concentration than the drift layer, creating a base layer of the second conductivity type on the drift layer, creating an emitter layer of the first conductivity type on the base layer, thinning the substrate on the second side such that the remaining part of the substrate forms a collector layer.

Abstract: In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench.

Abstract: The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.

Abstract: A method of forming a finFET device includes forming a plurality of fins on a substrate; forming a plurality of dummy gate structures over the plurality of fins, the dummy gate structures including gate sidewall spacers; performing an epitaxial growth process to merge the plurality of fins at locations not covered by the dummy gate structures; forming an interlevel dielectric (ILD) layer over the dummy gate structures and merged fins, the ILD layer comprising a first dielectric material; removing portions of the ILD layer and the merged fins so as to define trenches; and filling the trenches with a second dielectric material having an etch selectivity with respect to the first dielectric material, and wherein the gate sidewall spacers also comprise the second dielectric material such that regions of the merged fins in active areas are surrounded by the second dielectric material.

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).