Abstract: A semiconductor device includes: an IGBT section including a vertical IGBT; and a diode section arranged along the IGBT section and including a diode. The diode section includes a hole injection reduction layer having a first conductivity type and arranged in an upper layer portion of a drift layer, extending to a depth deeper than an anode region constituted by a second conductivity type region in the diode section, having an impurity concentration lower than an impurity concentration of the anode region and higher than an impurity concentration of the drift layer.

Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

Abstract: A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor.

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

Abstract: A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

Abstract: A semiconductor device including fin type patterns is provided. The semiconductor device includes a first fin type pattern, a field insulation layer disposed in vicinity of the first fin type pattern and having a first part and a second part, the first part protruding from the second part, a first dummy gate stack formed on the first part of the field insulation layer and including a first dummy gate insulation layer having a first thickness, and a first gate stack formed on the second part of the field insulation layer to intersect the first fin type pattern and including a first gate insulation layer having a second thickness different from the first thickness.

Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Abstract: A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node.

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region. The device also includes a first and a second fin structures over the substrate in the NFET region and a third fin structure over the substrate in the PFET region. The device also includes a first high-k (HK)/metal gate (MG) stack in the NFET region, including wrapping over a portion of the first fin structure, a first subset of the first source/drain (S/D) features, adjacent to the first HK/MG stack, over the recessed first fin structure and a second subset of the first S/D features partially over the recessed second fin structure and partially over the recessed first fin structure.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose the first source/drain region. At least part of the spacer material is removed to expose the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Abstract: To provide a semiconductor device that holds data even when power supply is stopped. The semiconductor device includes a first transistor, a second transistor, a third transistor, and a capacitor. One of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor and one electrode of the capacitor. A gate electrode of the second transistor is electrically connected to the other of the source electrode and the drain electrode of the third transistor.

Abstract: Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, ds; and a distance to four of the six neighboring pillars is a long distance, dl. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, ds, and a distance between neighboring pillars that are not in common rows as one another is a long distance, dl.

Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: A monolithic three-dimensional memory device contains a high mobility metal dichalcogenide channel. A stack of alternating layers comprising first material layers and second material layers is formed over a substrate. A memory opening is formed through the stack of alternating layers. A memory film is formed in the memory opening. A metal dichalcogenide channel is formed on an inner sidewall of the memory film. A dielectric core is formed within the metal dichalcogenide channel. A stack of titanium and gold may be employed to form a drain region to enhance contact. A hafnium oxide, aluminum oxide or hafnium aluminum oxide hafnium aluminum oxide layer may be employed on either side, or on both sides, of the metal dichalcogenide channel to enhance the mobility of electrons in the metal dichalcogenide channel.

Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips. At least one of the insulating strips includes an insulating material with a dielectric constant equal to or lower than 3.6. A plurality of structures of a conductive material is arranged orthogonally over the stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the stacks and structures. The insulating strips can have equivalent oxide thicknesses EOT substantially greater than their respective physical thicknesses. The EOT can be at least 10% greater than the respective physical thicknesses. The at least one of the insulating strips can consist essentially of the insulating material with a dielectric constant equal to or lower than 3.6.

Abstract: Provided is a non-volatile memory device having a vertical channel cell. The non-volatile memory device includes a substrate having a well. A first vertical channel and a second vertical channel are in contact with the well, and protrude from the well. A pipe channel connecting the first and second vertical channels is disposed. A cut-off gate electrode stacked over the well, and surrounding side surfaces of the first and second vertical channels is disposed. A pipe gate electrode stacked over the cut-off gate electrode, and having the pipe channel is disposed. A plurality of memory-cell gate electrodes stacked over the pipe gate electrode, and surrounding the side surfaces of the first and second vertical channels is disposed. A select gate electrode stacked over the plurality of memory-cell gate electrodes, and surrounding the side surfaces of the first and second vertical channels is disposed.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer, a first gate electrode layer, a second gate electrode layer, a gate insulating film, a first interlayer insulating film, a second interlayer insulating film. The first electrode layer is separated from the substrate in a first direction. The second electrode layer is separated from the first electrode layer in a second direction. The third electrode layer is provided between the first electrode layer and the second electrode layer. The third electrode layer includes a first edge face. A second edge face of the first gate electrode layer at the second gate electrode layer side is along the first edge face.

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract: A semiconductor device with a novel structure that can consume less power and have a reduced size of a circuit. In the semiconductor device, when configuration operation is started in a path transistor in a configuration memory, supply of an H-level potential to a signal pass node is stopped and then the potential of the signal pass node is set at L level, whereby configuration data is input to a memory potential retaining node, which is a gate of the path transistor. After the configuration operation is completed, the supply of the H-level potential to the signal pass node is resumed so that capacitive coupling occurs between the path transistor and the memory potential retaining node and increase the gate potential of the path transistor, so that a boosting effect is obtained. The above structure eliminates the need for a keeper circuit, reducing the power consumption and the circuit area.

Abstract: Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin, patterning a second layer under the first layer to remove a portion of the second layer on sides of the at least one fin, forming a sacrificial gate electrode on the at least one fin, and a spacer on the sacrificial gate electrode, selectively removing the sacrificial gate electrode, depositing an oxide layer on top and side portions of the at least one fin corresponding to a channel region of the at least one fin, performing thermal oxidation to condense the at least one fin in the channel region until a bottom portion of the at least one fin is undercut, and stripping a resultant oxide layer from the thermal oxidation, leaving a gap in the channel region between a bottom portion of the at least one fin and the second layer.

Abstract: One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

Abstract: Provided are a thin film transistor substrate and a display using the same. A display includes: a first thin film transistor, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer being disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer, and an etch-stopper layer disposed on the oxide semiconductor layer.

Abstract: The present invention relates to an array substrate, a method for manufacturing the same and a display device. The array substrate comprises a substrate, and a first region and a second region that are provided on the substrate and adjacent to each other and a difference in level between the two exceeds a threshold, a difference-in-level compensation pattern is provided on the substrate, which overlaps with both the first region and the second region in a direction perpendicular to the substrate and does not exceed the first region and the second region. By the technical solution of the present invention, the difference in level between the data line and an adjacent region on the array substrate is reduced, so that during a rubbing process, the rubbing area of a polyimide solution is increased, and the risk of light leakage is reduced without a decrease of the pixel aperture ratio.

Abstract: A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.

Abstract: A thin film transistor and a fabrication method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a gate electrode (2), a source electrode (5) and a drain electrode (6) disposed in a same layer on a base substrate (1); a gate insulating layer (3) disposed on the gate electrode (2), the source electrode (5) and the drain electrode (6); an active layer (4) disposed on the gate insulating layer (3); a passivation layer (7) disposed on the active layer (4) and the gate insulating layer (3).

Abstract: A display device includes a substrate, a display element, a transistor as a drive element of the display element, and a holding capacitance element holding electric charge corresponding to a video signal, and including a first conductive film, a first semiconductor layer including an oxide semiconductor, an insulating film, and a second conductive film in order of closeness to the substrate. The display element, the transistor, and the holding capacitance element are provided on the substrate.

Abstract: Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

Abstract: A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.

Abstract: Described is an arrangement for registering light, comprising: a MOS-transistor structure having a first source/drain region, a second source/drain region, and a bulk region at least partially between the first source/drain region and the second source/drain region, wherein the bulk region has a doping type different from another doping type of the first and the second source/drain regions, wherein in the bulk region charge carriers are generated in dependence of light impinging on the bulk region, wherein the generated charge carriers control a current flowing from the first source/drain region to the second source/drain region via at least a portion of the bulk region.

Abstract: A pixel circuit includes a floating diffusion layer of a first conductivity-type between a drain/source of a second conductivity-type and a source/drain of the second conductivity-type. The source/drain and the drain/source touch the floating diffusion layer. A cathode of a photoelectric converter is electrically connected to the floating diffusion layer. An anode of the photoelectric converter touches the cathode. The cathode is of the first conductivity-type and the anode is of the second conductivity-type.

Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

Abstract: A semiconductor device includes a carrier substrate, a first color filter, a first photodetector, and a light enhancement structure. The first photodetector is disposed between the carrier substrate and the first color filter. The light enhancement structure is disposed between the first color filter and the carrier substrate and adjacent to the first photodetector for enhancing intensity of light incident the first photodetector.

Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.

Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.

Abstract: Provided is an image-capturing unit including an image-capturing chip that includes a first surface having a pixel and a second surface that is on an opposite side of the first surface and has provided thereon an output section that outputs a pixel signal read from the pixel; a transparent substrate that is arranged facing the first surface and includes a wire pattern; a mounting substrate that is arranged facing the second surface and supports the image-capturing chip; and a relay section that is arranged on the mounting substrate and relays, to the wire pattern, the pixel signal output from the output section. Also provided is an image-capturing apparatus including the image-capturing unit described above.

Abstract: The semiconductor device includes a semiconductor substrate, an isolation feature, a photodiode and a transistor gate. The isolation feature is disposed in the semiconductor substrate. The photodiode is disposed in the semiconductor substrate and adjacent to the isolation feature. The photodiode includes a first pinned photodiode (PPD) with a first dopant type and a second PPD with a second dopant type. The second PPD is embedded in the first PPD, and is different from the first dopant type. The transistor gate is disposed over the photodiode and includes a first portion and a second portion. The first portion with the first dopant type is used for controlling the operation of the semiconductor device. The second portion with the second dopant type is adjacent to the first portion. The second portion covers the photodiode and extends toward the isolation feature.

Abstract: Provided is a semiconductor device with improved performance. In a method for manufacturing a semiconductor device, after forming a gate electrode of a transfer transistor over a p-type well, a photodiode is formed in one part of the p-type well positioned on one side with respect to the gate electrode. Then, a cap insulating film including silicon and nitrogen is formed over the photodiode before implanting impurity ions for formation of an n-type low-concentration semiconductor region of the transfer transistor, into the other part of the p-type well positioned on a side opposite to the one side with respect to the gate electrode.

Abstract: An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.

Abstract: A magnetic tunnel junction cell includes a first electrode having an axis extending in a direction substantially perpendicular to an active surface of a substrate. The magnetic tunnel junction further includes a fixed layer, a U-shaped free layer, a tunnel layer sandwiched between the fixed layer and the U-shaped free layer and a second electrode embedded in the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer are disposed between the first electrode and the second electrode and constitute a magnetic tunnel junction. The tunnel layer may also be U-shaped.

Abstract: An organic optoelectronic component and a method for operating the organic optoelectronic component are disclosed. In an embodiment the organic optoelectronic component includes at least one organic light emitting element including an organic functional layer stack having at least one organic light emitting layer between two electrodes and at least one organic light detecting element including at least one organic light detecting layer, wherein the at least one organic light detecting element and the at least one organic light emitting element are laterally arranged on a common substrate.

Abstract: An organic optoelectronic component and a method for operating an organic optoelectronic component are disclosed.

Abstract: A method is specified for operating an organic optoelectronic component, which has at least one organic light-emitting element having an organic functional layer stack with at least one organic light-emitting layer between two electrodes and at least one organic light-emitting element having an organic light-detecting layer. These elements are arranged on a common substrate in laterally adjacent area regions. The at least one organic light-detecting element detects ambient light, which is incident onto the organic optoelectronic component. The intensity of the light emitted by the at least one organic light-emitting element is regulated depending on a signal of the at least one organic light-detecting element with a characteristic signal form.

Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, a photoelectric conversion layer, a termination layer, and an electrode layer. In the silicon substrate, first semiconductor regions and second semiconductor regions are alternately arranged along a first surface on a light incident side of the silicon substrate. The first semiconductor regions are doped with impurities of first concentration and have a conductivity of either one of p-type and n-type. The second semiconductor regions are doped with impurities of a second concentration lower than the first concentration and have a conductivity of the other type. The photoelectric conversion layer is disposed on a first surface side of the silicon substrate. The termination layer is disposed between the silicon substrate and the photoelectric conversion layer, in contact with the first surface, and to terminate dangling bonds of the silicon substrate. The electrode layer is provided on the light incident side.

Abstract: A display device includes a display unit in which pixels are arranged in a matrix. The pixels each include a first sub-pixel having the largest area among sub-pixels, a second sub-pixel adjacent to the first sub-pixel and having an area smaller than that of the first sub-pixel, and a third sub-pixel adjacent to the first and second sub-pixels, having an area smaller than that of the first sub-pixel, and arranged in the same column as that of second sub-pixels. First, second, and third pixels are aligned in at least one of a column direction or a row direction and each include the first, second, and third sub-pixels that can display different one of first, second, and third colors. Areas of the first, second, and third colors displayable by the first, second, and third pixels in total are equal to one another.