Abstract: A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge trapping barrier, and is electrically isolated from the semiconductor substrate by a charge blocking barrier. At least one of the charge trapping barrier and the charge blocking barrier contains a III-V semiconductor material. The charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.

Abstract: Provided is a semiconductor device manufacturing method. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.

Abstract: A solar cell having a P-type silicon substrate wherein one main surface is a light-receiving surface and another is a backside, a plurality of back surface electrodes formed on a part of the backside, an N-type layer in at least a part of the light-receiving surface, and contact areas in which the substrate contacts the electrodes; wherein the P-type silicon substrate is a silicon substrate doped with gallium and has a resistivity of 2.5 ?·cm or less; and a back surface electrode pitch Prm [mm] of the plurality of electrodes and the resistivity Rsub [?·cm] of the substrate satisfy the relation represented by the following formula (1). This provides a solar cell and a solar cell module having excellent conversion efficiency with resistance loss being prevented, with the solar cell using a substrate the light-induced degradation of which is eliminated. log(Rsub)??log(Pm)+1.0 ??(1).

Abstract: A photovoltaic device with increased efficiency and a method for making the same. The present invention provides a photovoltaic device including: a transparent substrate; a transparent conductive electrode layer disposed on the transparent substrate; an n-type layer disposed on the transparent conductive electrode layer; a chalcogen absorber layer disposed on the n-type layer; a p-type molybdenum trioxide (MoO3) interlayer disposed on the chalcogen absorber layer; and a conductive layer disposed on the interlayer. A photovoltaic device having a superstrate configuration with the order of the layers reversed is also provided. The present invention further provides methods for making the photovoltaic devices according to the present invention.

Abstract: A photovoltaic (PV) apparatus includes a substrate having a first substrate surface and a second substrate surface. A cavity fabricated in the substrate extends from the first substrate surface toward the second substrate surface. The cavity defines a first end to receive incident light, a second end opposite the first end, and a side surface, which extends from the first end to the second end to concentrate the incident light, received by the first end, toward the second end. The PV apparatus also includes a photovoltaic (PV) cell, in optical communication with the second end of the at least one cavity, to convert the incident light into electricity.

Abstract: A photovoltaic cell can include an interfacial layer in contact with a semiconductor layer.

Abstract: A conductive paste for forming a solar cell electrode, including: a conductive powder containing silver as a main component; glass frit; and an organic vehicle, wherein the glass frit contains tellurium glass frit having tellurium oxide as a network-forming component. The conductive paste of the present invention makes it possible to form a solar cell electrode having a low dependence on firing temperature without causing problems due to fire-through into the substrate, and to thereby obtain a solar cell having good solar cell characteristics.

Abstract: The present invention is a method for manufacturing a substrate for a solar cell composed of a single crystal silicon, including the steps of: producing a silicon single crystal ingot; slicing a silicon substrate from the silicon single crystal ingot; and subjecting the silicon substrate to low temperature thermal treatment at a temperature of 800° C. or more and less than 1200° C., wherein the silicon single crystal ingot or the silicon substrate is subjected to high temperature thermal treatment at a temperature of 1200° C. or more for 30 seconds or more before the low temperature thermal treatment. As a result, it is possible to provide a method for manufacturing a substrate for a solar cell that can prevent decrease in the minority carrier lifetime of the substrate even when the substrate has higher oxygen concentration.

Abstract: A method of creating cadmium telluride films is presented. The method demonstrates heterogeneous nucleation of CdTe directly on a substrate through sequential deposition of aqueous precursor solutions containing cadmium and telluride ions, respectively. The method can include (i) applying a cadmium precursor solution to the substrate to form a cadmium precursor film on the substrate, (ii) applying a telluride precursor solution to the cadmium precursor film. The telluride precursor solution includes Te2? in solution such that a CdTe film is adherently formed directly on the substrate.

Abstract: A semiconductor heterostructure for an optoelectronic device is disclosed. The semiconductor heterostructure includes at least one stress control layer within a plurality of semiconductor layers used in the optoelectronic device. Each stress control layer includes stress control regions separated from adjacent stress control regions by a predetermined spacing. The stress control layer induces one of a tensile stress and a compressive stress in an adjacent semiconductor layer.

Abstract: Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.

Abstract: A method for manufacturing a light emitting diode structure uses a removable prefilled layer to attach the flip-type chip on a temporary substrate. A growth substrate of the flip-type chip is removed by laser lift-off, and then the light emitting diode structure is attached to a transparent support body. Lastly, the temporary substrate and the prefilled layer are removed.

Abstract: A nanoparticle phosphor element includes a capsule-shaped material that has a plurality of concave portions in a surface, a medium that is sealed in the capsule-shaped material, and a semiconductor nanoparticle phosphor that is dispersed in the medium, and a light emitting element includes a sealing material, and the nanoparticle phosphor element of the disclosure that is dispersed in the sealing material.

Abstract: Provided is a semiconductor layer light-emitting element having tunneling blocking layers interposed between adjacent active regions, wherein the tunneling blocking layers are semiconductor layers, which do not allow the movement of an electron or a hole at an applied voltage sufficient to activate only one active region among all active regions, and independently separate two adjacent active regions in a quantum region range, so that the semiconductor light-emitting element comprises multiple independent active regions in a vertical direction in a single chip and thus can be driven at high voltages.

Abstract: A semiconductor light emitting element is disclosed. The element includes a substrate including a first surface, a second surface opposite to the first surface, and a side surface that connects the first surface and the second surface; a semiconductor layer formed on the first surface of the substrate and configured to generate light; and a light reflective layer formed on the second surface of the substrate to cover an entire region of the second surface of the substrate and configured to reflect the light generated by the semiconductor layer toward the semiconductor layer. A modified layer, which has a physical property different from that of the other portion of the substrate, is formed on the side surface of the substrate to be spaced apart from the first surface toward the second surface by altering a material forming the substrate.

Abstract: The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening.

Abstract: A light-emitting device including a window layer-cum-support substrate, a light-emitting portion provided on the window layer-cum-support substrate and including a second semiconductor layer of a second conductivity type, an active layer, and first semiconductor layer of a first conductivity type in stated order, a first ohmic electrode provided on the first semiconductor layer, and insulator top coat at least partially coating the first semiconductor layer surface and light-emitting portion side surface, wherein the first semiconductor layer surface and surface of the window layer-cum-support substrate are roughened, and the first semiconductor layer includes at least two layers of an active-layer-side layer and roughened-side layer, and roughened-side layer is formed of material having lower Al content than the active-layer-side layer.

Abstract: Provided are a horizontal light emitting diode (LED) device and a method for fabricating the same. The horizontal LED device includes a sapphire substrate; an n-type GaN layer disposed on the sapphire substrate; an activation layer disposed on the n-type GaN layer; a p-type GaN layer disposed on the activation layer; a current spreading layer disposed on the p-type GaN layer; a p-electrode disposed on the current spreading layer; a plurality of holes exposing the n-type GaN layer through the current spreading layer, the p-type GaN layer, and activation layer; and an n-electrode disposed on the exposed n-type GaN layer and being in ohmic contact with the exposed n-type GaN layer at a plurality of positions on bottom surfaces of the plurality of holes.

Abstract: The embodiment relates to a light emitting device, a method of fabricating the same, a light emitting device package, and a lighting system. According to the embodiment, a light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first electrode electrically connected with the first conductive semiconductor layer, a second electrode electrically connected with the second conductive semiconductor layer, an insulating member provided on the light emitting structure while exposing the first electrode and the second electrode, a third electrode provided on the first electrode, and a fourth electrode provided on the second electrode.

Abstract: A light emitting diode (LED) includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, a first conductive layer disposed on a portion of the second semiconductor layer, a second conductive layer disposed on the second semiconductor layer, and an insulation layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and overlapping the first semiconductor layer, the second semiconductor layer, and the second conductive layer, in which the insulation layer has a first region having different thicknesses and a second region having a substantially constant thickness.

Abstract: A street lamp includes a light emitter that is disposed at a height of at least 5 m and at most 15 m above a road and emits white light to illuminate the road. The white light has: a correlated color temperature in a range from 5000 K to 6500 K; a chromaticity deviation in a range from ?10 to +10; a scotopic/photopic (S/P) ratio of at least 2.0, the S/P ratio being a ratio of a scotopic luminous flux to a photopic luminous flux; and an average horizontal illuminance of at least 5 lx at an illumination area on the road illuminated with the white light.

Abstract: Embodiments of the invention include a semiconductor light emitting device, a first wavelength converting member disposed on a top surface of the semiconductor light emitting device, and a second wavelength converting member disposed on a side surface of the semiconductor light emitting device. The first and second wavelength converting members include different wavelength converting materials.

Abstract: Provided is a wavelength converting member which can reduce change in the light emission intensity over time as compared with conventional members and a method of producing the wavelength converting member. A wavelength converting member (1) includes a quantum dot layer (2) having quantum dots, barrier layers (3, 4) formed on at least both sides of the quantum dot layer (2). The moisture vapor transmission rate of the barrier layer is lower than 9 g/(m2·d). Thus, change in the light emission intensity over time can be effectively inhibited.

Abstract: A lens of an LED package structure includes a square-shaped base layer, a first light-guiding portion integrally connected to the base layer, a second light-guiding portion taperedly extended from the first light-guiding portion. The second light-guiding portion has an apex located away from the first light-guiding portion. The lens includes four side curved surfaces and four boundary curved surfaces connected to the apex. Four first projecting regions are defined by orthogonally projecting the four boundary curved surfaces onto the base layer, and the four first projecting regions are arranged on two diagonals of the base layer. Any two adjacent boundary curved surfaces are provided with one of the side curved surfaces there-between. Each boundary curved surface has a first radius of curvature (R1), a portion of each side curved surface arranged on the second light-guiding portion has a second radius of curvature (R2), wherein R1/R2=M?{square root over ( )}2 and M=0.8˜1.2.

Abstract: A light-emitting module provided in an embodiment comprises: a circuit board; a light-emitting diode arranged on the circuit board; an optical lens arranged on the light-emitting diode; a reflective sheet arranged between the optical lens and the circuit board; and an adhesive layer arranged between the reflective sheet and the circuit board, wherein the optical lens comprises: an incident surface having a recessed part on the light-emitting diode; a reflective surface for reflecting light incident on the incident surface; and a light-emitting surface arranged on the outer circumference thereof, wherein the reflective sheet includes an open area in which the light-emitting diode is arranged and the open area has a width wider than the width of the light-emitting diode and narrower than the width of the incident surface of the optical lens.

Abstract: A light source may comprise a thermally conductive frame comprising a base and a faceted portion extending from the base. The faceted portion may comprise a plurality of facets spaced circumferentially thereabout. Additionally, a hollow passageway may extend through the base and axially through the faceted portion. A plurality of LED chips may be arranged on the plurality of facets to provide an emission of light in an arc of 360 degrees.

Abstract: An an apparatus for manufacturing a thermoelectric module is provided. The apparatus includes a thermoelectric element interposed between a lower substrate that includes a lower electrode and an upper substrate that includes an upper electrode. Additionally, the apparatus includes a first block that is configured to support the lower substrate and a second block that is configured to move vertically with respect to the first block and support the upper substrate. A jig is configured to position the thermoelectric element in connection with the upper electrode and the lower electrode.

Abstract: A flexible Peltier device in which emitting heat conversion properties between Peltier elements and an object transferring heat may be improved and a flexible heat-emitting sheet having the Peltier elements bonded thereto may be bent without worrying the separation there between. A flexible Peltier device includes a single or plural Peltier element which is disposed on one surface side of a heat-emitting sheet having flexibility made from heat-conductive rubber containing a heat conductive filler and each semiconductor element which has a heating side and a cooling side and composes the Peltier element at least one of the heating side and the cooling side is bonded integrally to the heat-emitting sheet by a direct covalent bond and/or by an indirect covalent bond through a molecular adhesive at active groups existing on each other surfaces.

Abstract: A sensor and/or transducer device having at least one bending structure including at least one piezoelectric layer in each case, using which an intermediate volume between at least two electrodes of the bending structure is at least partially filled in each case, the sensor and/or transducer device including an electronic unit, which is designed to apply at least one predefined or established actuator voltage between two of the electrodes at a time of the bending structure in such a way that a deformation of the bending structure triggered by an intrinsic stress gradient in the bending structure may be at least partially compensated for. A method for operating a sensor and/or transducer device having at least one bending structure, which includes at least one piezoelectric layer, and a method for calibrating a microphone having at least one bending structure, which includes at least one piezoelectric layer, are also described.

Abstract: A piezoelectric actuator includes a piezoelectric element that includes a piezoelectric unit including a ferroelectric, which has an asymmetric bipolar P-E curve, a capacitor connected to the piezoelectric unit in series, and a resistor connected to the capacitor in series and connected to the ferroelectric in parallel; and a drive unit that inputs a drive waveform Vd, which includes a DC offset component of which polarity is opposite to polarization of the ferroelectric, to the piezoelectric element to drive the piezoelectric element. A value of a coercive electric field Ec1, a value of a coercive electric field Ec2, the capacitance Cs of the capacitor, the capacitance Cpz of the ferroelectric, combined resistance Rp of the resistance of the resistor and the resistance of the ferroelectric, and a fundamental angular frequency ? of the drive waveform satisfy Expressions I to III, wherein 1 / 3 ? ? Ec 1 + Ec 2 ? / ? Ec 1 - Ec 2 ? Expression ? ? I C s ? 1.

Abstract: A method is provided for fabricating a thin-film electronic device employing a piezoelectric plate. The method provides a plurality of piezoelectric plates, and a substrate with electronic devices, each electronic device including a top surface well. A piezoelectric plate suspension is formed and flowed over the substrate. In response to the piezoelectric plate suspension flow, piezoelectric plates are captured in the top surface wells. The electric device top surface wells have well bottom surfaces, with bottom electrical contacts formed on the bottom surfaces. Thus, the capture of a piezoelectric plate in a top surface well entails interfacing a piezoelectric plate electrode, either the first electrode or the second electrode, to the bottom electrical contact. Subsequent to capturing the piezoelectric plates in the top surface wells, a thin-film process forms a conductive line overlying the exposed piezoelectric device electrode (i.e., the electrode not connected to the bottom electrical contact).

Abstract: Use of an elastomeric film in the form of a gel, wherein said gel is a non-conductive hydrogel or organogel, as a dielectric electroactive polymer.

Abstract: A method is provided for fabricating piezoelectric plates. A sacrificial layer is formed overlying a growth substrate. A template layer, with openings exposing sacrificial layer surfaces, is formed over the sacrificial layer. An adhesion layer/first electrode stack is selectively deposited in the openings overlying the sacrificial layer surfaces, and a piezoelectric material formed in the openings overlying the stack. Then, a second electrode is formed overlying the piezoelectric material. Using the second electrode as a hardmask, the piezoelectric material is etched to form polygon-shaped structures, such as disks, attached to the sacrificial layer surfaces. After removing the template layer and annealing, the polygon-shaped structures are separated from the sacrificial layer. With the proper choice of growth substrate material, the annealing can be performed at a relatively high temperature.

Abstract: A one-dimensional magnetic field sensor comprises a support, a single elongated magnetic field concentrator or two magnetic field concentrators, which are separated by a first gap, and at least one magnetic sensor element. The magnetic field concentrator, or both thereof, consists of at least two parts which are separated from each other by second gaps. A two-dimensional magnetic field sensor comprises a support, a single magnetic field concentrator which consists of at least three parts which are separated from each other by gaps, and at least two magnetic sensor elements.

Abstract: A semiconductor memory device that includes at least a lower contact plug on a semiconductor substrate, a magnetic tunnel junction of the lower contact plug, and a barrier pattern on a sidewall of the lower contact plug may further include an insulation pattern on the sidewall of the lower contact plug. The insulation pattern may be between the barrier pattern and the magnetic tunnel junction pattern. The insulation pattern may include an upper portion and a lower portion whose width is greater than a width of the upper portion.

Abstract: Described is an interconnect which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a second magnetoelectric material layer coupled to the ferromagnetic layer, wherein the ferromagnetic layer extends from the first end to the second end. Described is a majority gate device which comprises: a ferromagnetic layer; and first, second, third, and fourth magnetoelectric material layers coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a tunnel junction device coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first terminal coupled to a tunneling junction device; a second terminal coupled to a layer coupling the tunneling junction device and a magnetoelectric device; and a third terminal coupled to the magnetoelectric device.

Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

Abstract: There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M8XY6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M8XY6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal.

Abstract: A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. Forming the first unit switching layer includes forming a first unit insulation layer, and injecting first dopants into the first unit insulation layer by performing a first ion implantation process. Forming the second unit switching layer includes forming a second unit insulation layer, and injecting second dopants into the second unit insulation layer by performing a second implantation process.

Abstract: Subject matter disclosed herein may relate to correlated electron switches that are capable of asymmetric set or reset operations.

Abstract: New organic materials having polyaromatic structure containing boron and high triplet energy are disclosed. The high triplet energy materials are useful as host materials in PHOLEDs and improve device quantum efficiency and stability.

Abstract: A method for forming an organic light emitting diode is provided. A substrate and an evaporating source are provided. A first electrode is formed on a surface of the substrate. The evaporating source is spaced from the first electrode. The carbon nanotube film structure is heated to gasify an organic light emitting material and form an organic light emitting layer on a surface of the first electrode. A second electrode is formed on a surface of the organic light emitting layer.

Abstract: A compound represented by Chemical Formula 1, and a photoelectric device, an image sensor, and an electronic device including the same are disclosed. In Chemical Formula 1, each substituent is the same as defined in the detailed description.

Abstract: PDI derivatives useful as opto-electronically active materials or for the synthesis of such materials. Certain compounds herein function as efficient electron acceptors and are useful as electron active components of electronic devices.

Abstract: The present invention discloses an organic electroluminescence device, comprising a luminescent layer, wherein, a host material of the luminescent layer comprises a thermally activated delayed fluorescence material, the host material is doped by a dye, and the dye comprises at least one phosphorescent dye. The present invention employs a thermally activated delayed fluorescence material, whose difference between the triplet state energy level and the singlet state energy level (?EST) is relatively small. The present invention employs the material as the phosphorescence host, so part of the triplet state exciton level transfers to the singlet state excitons, and the amount of the overall triplet state excitons is smaller.

Abstract: The present disclosure relates to an organic electroluminescent compound and an organic electroluminescent device comprising the same. By using the organic electroluminescent compound according to the present disclosure, it is possible to produce an organic electroluminescent device which has a low driving voltage, excellent current and power efficiencies, and improved operation lifespan.

Abstract: There is disclosed a compound which is an N-heterocycle having at least one substituent of Formula I In Formula I: Q1, Q2, Q3, Q4, and Q5 are the same or different and can be N or CR1; R1 is the same or different at each occurrence and can be H, D, CN, hydrocarbon aryl, heteroaryl, deuterated hydrocarbon aryl, or deuterated heteroaryl; and * represents a point of attachment to N in the N-heterocycle. In Formula I, at least one of Q1 through Q5 is N and at least one of Q1 through Q5 is C—CN.

Abstract: An organic light-emitting device including a first electrode, a second electrode facing the first electrode, and an organic layer disposed between the first electrode and the second electrode, wherein the organic layer has an emission layer, wherein the emission layer includes a host and a thermally activated delayed fluorescent dopant, wherein the dopant includes a condensed cyclic compound represented by Formula 1, and wherein an amount of the dopant is smaller than that of the host: Ar1—Ar2??Formula 1 wherein Ar1 and Ar2 are the same as described in the specification.