Abstract: An electrostatic chuck is described that has radio frequency coupling suitable for use in high power plasma environments. In some examples, the chuck includes a base plate, a top plate, a first electrode in the top plate proximate the top surface of the top plate to electrostatically grip a workpiece, and a second electrode in the top plate spaced apart from the first electrode, the first and second electrodes being coupled to a power supply to electrostatically charge the first electrode.

Abstract: An electrostatic chuck is described to carry a workpiece for processing such as high power plasma processing. In embodiments, the chuck includes a top plate to carry the workpiece, the top plate having an electrode to grip the workpiece, a cooling plate under the top plate to cool the top plate, a gas hole through the cooling plate and the top plate to feed a gas to the workpiece through the top plate, and an aperture-reducing plug in the cooling plate gas hole to conduct gas flow through the hole.

Abstract: A heated support assembly is disclosed which includes a body comprising aluminum nitride doped with magnesium oxide having a volume resistivity of about 1×1010 ?-cm at about 600 degrees Celsius, an electrode embedded in the body, and a heater mesh embedded in the body.

Abstract: An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate.

Abstract: A method for manufacturing a handling device includes depositing a single layer of an adhesive on a first surface of a first wafer; depositing an antiadhesive layer on a first surface of a second wafer different from the first wafer; bringing into contact the first wafer and the second wafer, the bringing into contact taking place at the level of the single adhesive layer of the first wafer and the antiadhesive layer of the second wafer; separating the first wafer and the second wafer; the first wafer including the single adhesive layer forming a handling device. The bringing into contact of the first wafer and the second wafer is carried out at a temperature TC such that TC>Tg°100°C. where Tg is the glass transition temperature of the material composing the single adhesive layer of the first wafer.

Abstract: An apparatus for expanding chips of a wafer, wherein the apparatus comprises an expansion mechanism configured for expanding a tape on which the chips of the wafer are arranged, and an inflation mechanism configured for inflating at least a part of an edge portion of the tape so that part of the edge portion approaches a frame.

Abstract: It is an object of the present invention to provide a high-flatness substrate holding table. According to a first aspect, a substrate processing apparatus is provided, and such a substrate processing apparatus includes a table for holding a substrate, a resin film attached to a top surface of the table and a heater provided inside the table, and the top surface of the table is formed of ceramics, the top surface of the table includes an opening connectable to a vacuum source, the resin film is formed of polyimide, and a through hole is formed at a position corresponding to the opening of the table when attached to the top surface of the table.

Abstract: An apparatus for treating a wafer is provided. The apparatus includes a platen, a chamber, an etch gas supplier and a tilting mechanism. The chamber has at least one aperture at least partially facing to the platen. The etch gas supplier is fluidly connected to the chamber. The tilting mechanism is coupled with the platen for allowing the platen to have at least one first degree of freedom to tilt relative to the aperture of the chamber.

Abstract: Susceptor assemblies comprising a susceptor base and a plurality of pie-shaped skins thereon are described. A pie anchor can be positioned in the center of the susceptor base to hold the pie-shaped skins in place during processing.

Abstract: A substrate placing table, which is installed inside a processing container for processing a wafer, includes: a stage configured to place a water on an upper surface thereof and including an inner peripheral flow channel and an outer peripheral flow channel formed therein to circulate a heat medium of a predetermined temperature therethrough; a support table configured to support the stage; and a temperature adjusting plate installed between the stage and the support table, and including a temperature adjusting mechanism configured to adjust a temperature of a heat radiation portion at which heat is radiated between the stage and the support table.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A semiconductor wafer in accordance with an embodiment includes: a support substrate semiconductor wafer having a first surface and a second surface opposite to the first surface; and an active layer formed on the first surface. The support substrate semiconductor wafer includes a support substrate semiconductor and an insulating film which is formed on a first surface side and a second surface side of the support substrate semiconductor. An area of the insulating film of the second surface is smaller than an area of the insulating film of the first surface.

Abstract: A process of forming an electronic device including providing a substrate having a first surface and a second surface opposite the first surface; etching the substrate along the first surface to define a trench; forming a via within the trench; applying a tape including an adhesive to the first surface, wherein the adhesive of the tape is spaced apart from the first surface by a distance; and operating on the second surface of the substrate.

Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b) providing a second structure successively including a substrate, an active layer, an intermediate layer, a first semiconducting layer and a porous second semiconducting layer; c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer; d) removing the substrate of the second structure so as to expose the active layer; e) adding dopants to the first semiconducting layer or to the active layer; f) irradiating the first semiconducting layer by a pulse laser so as to thermally activate the corresponding dopants.

Abstract: A first film having a repetitive line pattern is formed on an under film. A second film is formed on a side surface of the first film. The second film has an etching selectivity different from that of the first film. A third film is formed on an upper surface and a side surface of the second film. The third film has an etching selectivity different from those of the first and second films. A resist pattern with an opening is formed on the third film. A recess that exposes upper surfaces of the first, second and third films is formed by etching the third film by using the resist pattern as an etching mask. An upper surface of the under film is exposed by etching the first and third films. A through hole that penetrates through the under film is formed by etching the under film.

Abstract: An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a ? line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a ? line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an ? line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a ??? jog; a ??? jog; an ??? jog; a ??? jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.

Abstract: A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.

Abstract: An expansion sheet is adapted to be held and expanded by an expanding apparatus when a platelike workpiece is attached to the expansion sheet. The expansion sheet has a peripheral area around the workpiece where the expansion sheet is adapted to be held by first, second, third, and fourth holding units that are moveable away from each other. The expansion sheet includes a base sheet and an adhesive layer formed on the base sheet, the adhesive layer having adhesion adapted to be reduced by applying ultraviolet light. The adhesion of the adhesive layer in the peripheral area of the expansion sheet is lower than that in the other area of the expansion sheet.

Abstract: Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction product of a metal or metal alloy of an interconnect metallic region with a metal of either a metal cap or a metal layer. In some embodiments, the metal cap may include a metal nitride and thus a nitride-containing intermetallic compound can be formed. The formation of the intermetallic compound can improve the electromigration resistance of the interconnect structures and widen the process window for fabricating interconnect structures.

Abstract: Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction product of a metal or metal alloy of an interconnect metallic region with a metal of either a metal cap or a metal layer. In some embodiments, the metal cap may include a metal nitride and thus a nitride-containing intermetallic compound can be formed. The formation of the intermetallic compound can improve the electromigration resistance of the interconnect structures and widen the process window for fabricating interconnect structures.

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The wafer has first and second opposing major surfaces and a layer of material disposed along the second major surface. The method includes placing the wafer onto a carrier substrate and etching through the spaces to form singulation lines, wherein etching comprises stopping atop the layer of material. The method includes providing an apparatus comprising a compression structure, a support structure, and a transducer system configured to apply high frequency mechanical vibrations to the layer of material. The method includes placing the wafer and the carrier substrate onto the support structure, and, in one embodiment, applying pressure and mechanical vibrations to the wafer to separate the layer of material in the singulation lines.

Abstract: Disclosed is a display device that includes an array substrate that includes a display region and a first non-display region, and includes a signal line connected to a pixel in the display region; a first signal transfer line that is at the first non-display region and transfers a test signal, and a second signal transfer line that transfers a test enable signal; a connection pattern connected to the first signal transfer line; a test transistor that is connected between the signal line and the connection pattern, and is connected to the second signal transfer line; and an electrostatic induction element that includes a dummy device in the form of either a dummy pattern and/or a dummy test transistor, the dummy pattern including a dummy connection pattern connected to the first signal transfer line, the dummy test transistor connected to the second signal transfer line.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure, etching first mask layer and second mask layer to expose a portion of a first semiconductor fin not covered by the first gate structure, performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion of the first semiconductor fin located below the first gate structure, etching the first semiconductor fin to remove a portion of an exposed portion of the first semiconductor fin, and epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first source region and a first drain region.

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Abstract: A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first source/drain on the substrate corresponding to the n-type transistor, a second source/drain on the substrate corresponding to the p-type transistor, a first contact trench over the first source/drain and adjacent the first gate structure, a second contact trench over the second source/drain and adjacent the second gate structure, a first liner layer in the first trench positioned at a bottom part of the first trench, a second liner layer in the second trench and on the first liner layer in the first trench, a metallization layer in the first and second trenches on the second liner layer, and a first silicide contact between the first liner layer and the first source/drain and a second silicide contact between the second liner layer and the second source/drain.

Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.

Abstract: Manufacturing a device may include inspecting a surface of an inspection target device. The inspecting may include forming a metal layer on a surface of the inspection target device on which a minute pattern is formed, directing a beam of light to be incident and normal to the surface of the inspection target device, determining a spectrum of light reflected from the surface of the inspection target device, and generating, via the spectrum, information associated with a structural characteristic of the minute pattern formed on the inspection target device. The inspection target device may be selectively incorporated into the manufactured device based on the generated information.

Abstract: Provided is a semiconductor device capable of measuring a depth of removal of a silicon carbide (SiC) wafer with high accuracy through simple steps, and a method for producing the semiconductor device. The semiconductor device according to an aspect of the present invention includes at least one evaluation element disposed on a SiC wafer. The evaluation element includes a doped region doped with a dopant on the SiC wafer, and an insulating film partially covering the doped region. The insulating film includes a plurality of partial insulating films. The doped region includes a plurality of regions sectioned by the plurality of partial insulating films in a plan view.

Abstract: An electroluminescent light source is provided with an adjusted or adjustable luminance parameter wherein: the source includes a set of segments, each segment comprising a discrete electroluminescent element or multiple discrete electroluminescent elements connected permanently to one another and having an emission area; at least a portion of the segments has different emission areas; the source comprising means for controlling at least a portion of the segments.

Abstract: A semiconductor arrangement is presented.

Abstract: An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode portion located outside the die bond portion; a ceramic substrate buried in the sealing resin layer; and an electronic component disposed on the die bond portion. When viewed in plan, the die bond portion and the ceramic substrate are partially overlapped to be in contact with each other, and the terminal electrode portion and the ceramic substrate are partially overlapped to be in contact with each other. The electronic component is electrically connected to the terminal electrode portion. The metal member includes a first plating layer and a second plating layer, and the average crystal grain diameter of the first plating layer is smaller than the average crystal grain diameter of the second plating layer.

Abstract: In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.

Abstract: A novel heat sinking technology, uniquely adaptive to LED lighting devices in a generally LED array format containing multiple openings on said heat sink's base portions and optionally fin portions providing “short path cooling” technology. The “short path cooling” technology is thoroughly taught with multiple examples. Also taught, are methods of heat sink area maintenance when said openings are placed on said heat sinks. Indeed, even surface area increases are shown to be possible when multiple openings are placed on said heat sinks. Lastly, other non-LED semiconductor cooling is discussed and illustrated in various figures using said “short path cooling” technology.

Abstract: Aligned high quality boron nitride nanotubes (BNNTs) can be incorporated into groups and bundles and placed in electronic and electrical components (ECs) to enhance the heat removal and diminish the heat production. High quality BNNTs are excellent conductors of heat at the nano scale. High quality BNNTs are electrically insulating and can reduce dielectric heating. The BNNTs composite well with a broad range of ceramics, metals, polymers, epoxies and thermal greases thereby providing great flexibility in the design of ECs with improved thermal management. Controlling the alignment of the BNNTs both with respect to each other and the surfaces and layers of the ECs provides the preferred embodiments for ECs.

Abstract: A circuit board includes an insulating substrate; a metal circuit sheet joined to a first principal surface of the insulating substrate; and a heat dissipating sheet made of metal and joined to a second principal surface of the insulating substrate, the second principal surface being opposite the first principal surface. The thickness of the heat dissipating sheet is at least 3.75 times the thickness of the metal circuit sheet. The size of metal grains contained in the heat dissipating sheet is smaller than the size of metal grains contained in the metal circuit sheet, and decreases with increasing distance from the second principal surface of the insulating substrate.

Abstract: An electronic device for a vehicle includes a substrate and a semiconductor package. The substrate is arranged to extend along a flowing path of wind produced by a fan unit. The semiconductor package is disposed on the substrate to be cooled by the wind. When an inflow port from which the wind is drawn by the fan unit is defined to include a flowing path having a first cross-section area, the semiconductor package is disposed in a space including a flowing path having a cross-section area that is larger than the first cross-section area.

Abstract: A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised of greater than 50% solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised primarily of solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised entirely of solder.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

Abstract: An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.

Abstract: A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring layers includes a fine wiring, a barrier film, which is not in contact with the fine wiring, is formed at a more outer side than the base board than the wiring layer including the fine wiring, and different types of resin insulating films are used for a wiring layer at an inner side of the barrier film close to the base board and a wiring layer at an outer side of the barrier film, respectively.

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.